2 MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __IVY_BRIDGE_MSR_H__
19 #define __IVY_BRIDGE_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel processors based on the Ivy Bridge microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x3A || \
36 DisplayModel == 0x3E \
41 Package. See http://biosbits.org.
43 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
51 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
53 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
54 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
56 @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
58 #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE
61 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
65 /// Individual bit fields
70 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
71 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
74 UINT32 MaximumNonTurboRatio
:8;
77 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
78 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
79 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
80 /// Turbo mode is disabled.
84 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
85 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
86 /// and when set to 0, indicates TDP Limit for Turbo mode is not
92 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
93 /// indicates that LPM is supported, and when set to 0, indicates LPM is
96 UINT32 LowPowerModeSupport
:1;
98 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
99 /// TDP level available. 01: One additional TDP level available. 02: Two
100 /// additional TDP level available. 11: Reserved.
102 UINT32 ConfigTDPLevels
:2;
105 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
106 /// minimum ratio (maximum efficiency) that the processor can operates, in
109 UINT32 MaximumEfficiencyRatio
:8;
111 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
112 /// minimum supported operating ratio in units of 100 MHz.
114 UINT32 MinimumOperatingRatio
:8;
118 /// All bit fields as a 64-bit value
121 } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
;
125 Core. C-State Configuration Control (R/W) Note: C-state values are
126 processor specific C-state code names, unrelated to MWAIT extension C-state
127 parameters or ACPI C-States. See http://biosbits.org.
129 @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
130 @param EAX Lower 32-bits of MSR value.
131 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
132 @param EDX Upper 32-bits of MSR value.
133 Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
137 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
139 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
140 AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
142 @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
144 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
147 MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
151 /// Individual bit fields
155 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
156 /// processor-specific C-state code name (consuming the least power). for
157 /// the package. The default is set as factory-configured package C-state
158 /// limit. The following C-state code name encodings are supported: 000b:
159 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
160 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
161 /// This field cannot be used to limit package C-state to C3.
166 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
167 /// IO_read instructions sent to IO register specified by
168 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
173 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
174 /// until next reset.
179 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
180 /// will conditionally demote C6/C7 requests to C3 based on uncore
181 /// auto-demote information.
183 UINT32 C3AutoDemotion
:1;
185 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
186 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
187 /// auto-demote information.
189 UINT32 C1AutoDemotion
:1;
191 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
194 UINT32 C3Undemotion
:1;
196 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
199 UINT32 C1Undemotion
:1;
204 /// All bit fields as a 32-bit value
208 /// All bit fields as a 64-bit value
211 } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
215 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
218 @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
219 @param EAX Lower 32-bits of MSR value.
220 @param EDX Upper 32-bits of MSR value.
226 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);
228 @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
230 #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
234 Package. Base TDP Ratio (R/O).
236 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
237 @param EAX Lower 32-bits of MSR value.
238 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
239 @param EDX Upper 32-bits of MSR value.
240 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
244 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;
246 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
248 @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
250 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648
253 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
257 /// Individual bit fields
261 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
262 /// specific processor (in units of 100 MHz).
264 UINT32 Config_TDP_Base
:8;
269 /// All bit fields as a 32-bit value
273 /// All bit fields as a 64-bit value
276 } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
;
280 Package. ConfigTDP Level 1 ratio and power level (R/O).
282 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
283 @param EAX Lower 32-bits of MSR value.
284 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
285 @param EDX Upper 32-bits of MSR value.
286 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
290 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;
292 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
294 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
296 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649
299 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
303 /// Individual bit fields
307 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
309 UINT32 PKG_TDP_LVL1
:15;
312 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
313 /// for this specific processor.
315 UINT32 Config_TDP_LVL1_Ratio
:8;
318 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
321 UINT32 PKG_MAX_PWR_LVL1
:15;
324 /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
327 UINT32 PKG_MIN_PWR_LVL1
:15;
331 /// All bit fields as a 64-bit value
334 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
;
338 Package. ConfigTDP Level 2 ratio and power level (R/O).
340 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
341 @param EAX Lower 32-bits of MSR value.
342 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
343 @param EDX Upper 32-bits of MSR value.
344 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
348 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;
350 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
352 @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
354 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A
357 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
361 /// Individual bit fields
365 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
367 UINT32 PKG_TDP_LVL2
:15;
370 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
371 /// for this specific processor.
373 UINT32 Config_TDP_LVL2_Ratio
:8;
376 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
379 UINT32 PKG_MAX_PWR_LVL2
:15;
382 /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
385 UINT32 PKG_MIN_PWR_LVL2
:15;
389 /// All bit fields as a 64-bit value
392 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
;
396 Package. ConfigTDP Control (R/W).
398 @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
399 @param EAX Lower 32-bits of MSR value.
400 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
401 @param EDX Upper 32-bits of MSR value.
402 Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
406 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;
408 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
409 AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
411 @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
413 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B
416 MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
420 /// Individual bit fields
424 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
429 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
430 /// this register is locked until a reset.
432 UINT32 Config_TDP_Lock
:1;
436 /// All bit fields as a 32-bit value
440 /// All bit fields as a 64-bit value
443 } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
;
447 Package. ConfigTDP Control (R/W).
449 @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
450 @param EAX Lower 32-bits of MSR value.
451 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
452 @param EDX Upper 32-bits of MSR value.
453 Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
457 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;
459 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
460 AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
462 @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
464 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C
467 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
471 /// Individual bit fields
475 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
478 UINT32 MAX_NON_TURBO_RATIO
:8;
481 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
482 /// content of this register is locked until a reset.
484 UINT32 TURBO_ACTIVATION_RATIO_Lock
:1;
488 /// All bit fields as a 32-bit value
492 /// All bit fields as a 64-bit value
495 } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
;
499 Package. Protected Processor Inventory Number Enable Control (R/W).
501 @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
502 @param EAX Lower 32-bits of MSR value.
503 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
504 @param EDX Upper 32-bits of MSR value.
505 Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
509 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;
511 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
512 AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
514 @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
516 #define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E
519 MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
523 /// Individual bit fields
527 /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
528 /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
529 /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
530 /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
531 /// inventory initialization agent to access MSR_PPIN. After reading
532 /// MSR_PPIN, the privileged inventory initialization agent should write
533 /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
534 /// prevent unauthorized modification to MSR_PPIN_CTL.
538 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
539 /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
540 /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
543 UINT32 Enable_PPIN
:1;
548 /// All bit fields as a 32-bit value
552 /// All bit fields as a 64-bit value
555 } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER
;
559 Package. Protected Processor Inventory Number (R/O). Protected Processor
560 Inventory Number (R/O) A unique value within a given CPUID
561 family/model/stepping signature that a privileged inventory initialization
562 agent can access to identify each physical processor, when access to
563 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
564 MSR_PPIN_CTL[bits 1:0] = '10b'.
566 @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)
567 @param EAX Lower 32-bits of MSR value.
568 @param EDX Upper 32-bits of MSR value.
574 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
576 @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
578 #define MSR_IVY_BRIDGE_PPIN 0x0000004F
582 Package. See http://biosbits.org.
584 @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
585 @param EAX Lower 32-bits of MSR value.
586 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
587 @param EDX Upper 32-bits of MSR value.
588 Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
592 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;
594 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
595 AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
597 @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
599 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE
602 MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
606 /// Individual bit fields
611 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
612 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
615 UINT32 MaximumNonTurboRatio
:8;
618 /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
619 /// Protected Processor Inventory Number (PPIN) capability can be enabled
620 /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
621 /// set to 0, PPIN capability is not supported. An attempt to access
622 /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
627 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
628 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
629 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
630 /// Turbo mode is disabled.
634 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
635 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
636 /// and when set to 0, indicates TDP Limit for Turbo mode is not
641 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,
642 /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
643 /// specify an temperature offset.
649 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
650 /// minimum ratio (maximum efficiency) that the processor can operates, in
653 UINT32 MaximumEfficiencyRatio
:8;
657 /// All bit fields as a 64-bit value
660 } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER
;
664 Package. MC Bank Error Configuration (R/W).
666 @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
667 @param EAX Lower 32-bits of MSR value.
668 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
669 @param EDX Upper 32-bits of MSR value.
670 Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
674 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
676 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
677 AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
679 @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
681 #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F
684 MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
688 /// Individual bit fields
693 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
694 /// to log additional info in bits 36:32.
696 UINT32 MemErrorLogEnable
:1;
701 /// All bit fields as a 32-bit value
705 /// All bit fields as a 64-bit value
708 } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER
;
714 @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
715 @param EAX Lower 32-bits of MSR value.
716 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
717 @param EDX Upper 32-bits of MSR value.
718 Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
722 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
724 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
725 AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
727 @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
729 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
732 MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
736 /// Individual bit fields
741 /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which
742 /// PROCHOT# will be asserted. The value is degree C.
744 UINT32 TemperatureTarget
:8;
746 /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature
747 /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
748 /// will assert at the offset target temperature. Write is permitted only
749 /// MSR_PLATFORM_INFO.[30] is set.
751 UINT32 TCCActivationOffset
:4;
756 /// All bit fields as a 32-bit value
760 /// All bit fields as a 64-bit value
763 } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
767 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
768 RW if MSR_PLATFORM_INFO.[28] = 1.
770 @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
771 @param EAX Lower 32-bits of MSR value.
772 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
773 @param EDX Upper 32-bits of MSR value.
774 Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
778 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;
780 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
782 @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
784 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE
787 MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
791 /// Individual bit fields
795 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
796 /// limit of 9 core active.
800 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
801 /// limit of 10core active.
805 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
806 /// limit of 11 core active.
810 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
811 /// limit of 12 core active.
815 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
816 /// limit of 13 core active.
820 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
821 /// limit of 14 core active.
825 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
826 /// limit of 15 core active.
831 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
832 /// the processor uses override configuration specified in
833 /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
834 /// uses factory-set configuration (Default).
836 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
839 /// All bit fields as a 64-bit value
842 } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER
;
846 Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
848 @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
849 @param EAX Lower 32-bits of MSR value.
850 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
851 @param EDX Upper 32-bits of MSR value.
852 Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
856 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;
858 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
860 @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
862 #define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
865 MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
869 /// Individual bit fields
873 /// [Bits 5:0] Recoverable Address LSB.
875 UINT32 RecoverableAddressLSB
:6;
877 /// [Bits 8:6] Address Mode.
879 UINT32 AddressMode
:3;
882 /// [Bits 31:16] PCI Express Requestor ID.
884 UINT32 PCIExpressRequestorID
:16;
886 /// [Bits 39:32] PCI Express Segment Number.
888 UINT32 PCIExpressSegmentNumber
:8;
892 /// All bit fields as a 64-bit value
895 } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
;
899 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
900 15.3.2.4, "IA32_MCi_MISC MSRs.".
902 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
903 and its corresponding slice of L3.
905 @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL
906 @param EAX Lower 32-bits of MSR value.
907 @param EDX Upper 32-bits of MSR value.
913 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
914 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);
916 @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.
917 MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.
918 MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
921 #define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474
922 #define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478
923 #define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C
928 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
929 15.3.2.4, "IA32_MCi_MISC MSRs.".
931 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
932 and its corresponding slice of L3.
934 @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS
935 @param EAX Lower 32-bits of MSR value.
936 @param EDX Upper 32-bits of MSR value.
942 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
943 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);
945 @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.
946 MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.
947 MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
950 #define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475
951 #define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479
952 #define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D
957 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
958 15.3.2.4, "IA32_MCi_MISC MSRs.".
960 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
961 and its corresponding slice of L3.
963 @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR
964 @param EAX Lower 32-bits of MSR value.
965 @param EDX Upper 32-bits of MSR value.
971 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
972 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);
974 @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.
975 MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.
976 MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
979 #define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476
980 #define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A
981 #define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E
986 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
987 15.3.2.4, "IA32_MCi_MISC MSRs.".
989 Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
990 and its corresponding slice of L3.
992 @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC
993 @param EAX Lower 32-bits of MSR value.
994 @param EDX Upper 32-bits of MSR value.
1000 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
1001 AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);
1003 @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.
1004 MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.
1005 MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
1008 #define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477
1009 #define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B
1010 #define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F
1015 Package. Package RAPL Perf Status (R/O).
1017 @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
1018 @param EAX Lower 32-bits of MSR value.
1019 @param EDX Upper 32-bits of MSR value.
1021 <b>Example usage</b>
1025 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
1027 @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1029 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613
1033 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1036 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
1037 @param EAX Lower 32-bits of MSR value.
1038 @param EDX Upper 32-bits of MSR value.
1040 <b>Example usage</b>
1044 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
1045 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
1047 @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1049 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
1053 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1055 @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
1056 @param EAX Lower 32-bits of MSR value.
1057 @param EDX Upper 32-bits of MSR value.
1059 <b>Example usage</b>
1063 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
1065 @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1067 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
1071 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1074 @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
1075 @param EAX Lower 32-bits of MSR value.
1076 @param EDX Upper 32-bits of MSR value.
1078 <b>Example usage</b>
1082 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
1084 @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1086 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
1090 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1092 @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
1093 @param EAX Lower 32-bits of MSR value.
1094 @param EDX Upper 32-bits of MSR value.
1096 <b>Example usage</b>
1100 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
1101 AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
1103 @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1105 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C
1109 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1111 @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
1112 @param EAX Lower 32-bits of MSR value.
1113 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1114 @param EDX Upper 32-bits of MSR value.
1115 Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1117 <b>Example usage</b>
1119 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1121 Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
1122 AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1124 @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1126 #define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1
1129 MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
1133 /// Individual bit fields
1137 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1139 UINT32 PEBS_EN_PMC0
:1;
1141 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1143 UINT32 PEBS_EN_PMC1
:1;
1145 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1147 UINT32 PEBS_EN_PMC2
:1;
1149 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1151 UINT32 PEBS_EN_PMC3
:1;
1152 UINT32 Reserved1
:28;
1154 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1156 UINT32 LL_EN_PMC0
:1;
1158 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1160 UINT32 LL_EN_PMC1
:1;
1162 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1164 UINT32 LL_EN_PMC2
:1;
1166 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1168 UINT32 LL_EN_PMC3
:1;
1169 UINT32 Reserved2
:28;
1172 /// All bit fields as a 64-bit value
1175 } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER
;
1179 Package. Uncore perfmon per-socket global control.
1181 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
1182 @param EAX Lower 32-bits of MSR value.
1183 @param EDX Upper 32-bits of MSR value.
1185 <b>Example usage</b>
1189 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
1190 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
1192 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1194 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00
1198 Package. Uncore perfmon per-socket global status.
1200 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
1201 @param EAX Lower 32-bits of MSR value.
1202 @param EDX Upper 32-bits of MSR value.
1204 <b>Example usage</b>
1208 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
1209 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
1211 @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1213 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01
1217 Package. Uncore perfmon per-socket global configuration.
1219 @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
1220 @param EAX Lower 32-bits of MSR value.
1221 @param EDX Upper 32-bits of MSR value.
1223 <b>Example usage</b>
1227 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
1228 AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
1230 @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1232 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06
1236 Package. Uncore U-box perfmon U-box wide status.
1238 @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
1239 @param EAX Lower 32-bits of MSR value.
1240 @param EDX Upper 32-bits of MSR value.
1242 <b>Example usage</b>
1246 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
1247 AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
1249 @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1251 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15
1255 Package. Uncore PCU perfmon box wide status.
1257 @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
1258 @param EAX Lower 32-bits of MSR value.
1259 @param EDX Upper 32-bits of MSR value.
1261 <b>Example usage</b>
1265 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
1266 AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
1268 @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1270 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35
1274 Package. Uncore C-box 0 perfmon box wide filter1.
1276 @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
1277 @param EAX Lower 32-bits of MSR value.
1278 @param EDX Upper 32-bits of MSR value.
1280 <b>Example usage</b>
1284 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
1285 AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
1287 @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
1289 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A
1293 Package. Uncore C-box 1 perfmon box wide filter1.
1295 @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
1296 @param EAX Lower 32-bits of MSR value.
1297 @param EDX Upper 32-bits of MSR value.
1299 <b>Example usage</b>
1303 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
1304 AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
1306 @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
1308 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A
1312 Package. Uncore C-box 2 perfmon box wide filter1.
1314 @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
1315 @param EAX Lower 32-bits of MSR value.
1316 @param EDX Upper 32-bits of MSR value.
1318 <b>Example usage</b>
1322 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
1323 AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
1325 @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
1327 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A
1331 Package. Uncore C-box 3 perfmon box wide filter1.
1333 @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
1334 @param EAX Lower 32-bits of MSR value.
1335 @param EDX Upper 32-bits of MSR value.
1337 <b>Example usage</b>
1341 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
1342 AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
1344 @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
1346 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A
1350 Package. Uncore C-box 4 perfmon box wide filter1.
1352 @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
1353 @param EAX Lower 32-bits of MSR value.
1354 @param EDX Upper 32-bits of MSR value.
1356 <b>Example usage</b>
1360 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
1361 AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
1363 @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
1365 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A
1369 Package. Uncore C-box 5 perfmon box wide filter1.
1371 @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
1372 @param EAX Lower 32-bits of MSR value.
1373 @param EDX Upper 32-bits of MSR value.
1375 <b>Example usage</b>
1379 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
1380 AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
1382 @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
1384 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA
1388 Package. Uncore C-box 6 perfmon box wide filter1.
1390 @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
1391 @param EAX Lower 32-bits of MSR value.
1392 @param EDX Upper 32-bits of MSR value.
1394 <b>Example usage</b>
1398 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
1399 AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
1401 @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
1403 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA
1407 Package. Uncore C-box 7 perfmon box wide filter1.
1409 @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
1410 @param EAX Lower 32-bits of MSR value.
1411 @param EDX Upper 32-bits of MSR value.
1413 <b>Example usage</b>
1417 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
1418 AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
1420 @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
1422 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA
1426 Package. Uncore C-box 8 perfmon local box wide control.
1428 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
1429 @param EAX Lower 32-bits of MSR value.
1430 @param EDX Upper 32-bits of MSR value.
1432 <b>Example usage</b>
1436 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
1437 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
1439 @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
1441 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04
1445 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
1447 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
1448 @param EAX Lower 32-bits of MSR value.
1449 @param EDX Upper 32-bits of MSR value.
1451 <b>Example usage</b>
1455 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
1456 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
1458 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
1460 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10
1464 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
1466 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
1467 @param EAX Lower 32-bits of MSR value.
1468 @param EDX Upper 32-bits of MSR value.
1470 <b>Example usage</b>
1474 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
1475 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
1477 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
1479 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11
1483 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
1485 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
1486 @param EAX Lower 32-bits of MSR value.
1487 @param EDX Upper 32-bits of MSR value.
1489 <b>Example usage</b>
1493 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
1494 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
1496 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
1498 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12
1502 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
1504 @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
1505 @param EAX Lower 32-bits of MSR value.
1506 @param EDX Upper 32-bits of MSR value.
1508 <b>Example usage</b>
1512 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
1513 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
1515 @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
1517 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13
1521 Package. Uncore C-box 8 perfmon box wide filter.
1523 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
1524 @param EAX Lower 32-bits of MSR value.
1525 @param EDX Upper 32-bits of MSR value.
1527 <b>Example usage</b>
1531 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
1532 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
1534 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
1536 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14
1540 Package. Uncore C-box 8 perfmon counter 0.
1542 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
1543 @param EAX Lower 32-bits of MSR value.
1544 @param EDX Upper 32-bits of MSR value.
1546 <b>Example usage</b>
1550 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
1551 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
1553 @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
1555 #define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16
1559 Package. Uncore C-box 8 perfmon counter 1.
1561 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
1562 @param EAX Lower 32-bits of MSR value.
1563 @param EDX Upper 32-bits of MSR value.
1565 <b>Example usage</b>
1569 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
1570 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
1572 @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
1574 #define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17
1578 Package. Uncore C-box 8 perfmon counter 2.
1580 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
1581 @param EAX Lower 32-bits of MSR value.
1582 @param EDX Upper 32-bits of MSR value.
1584 <b>Example usage</b>
1588 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
1589 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
1591 @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
1593 #define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18
1597 Package. Uncore C-box 8 perfmon counter 3.
1599 @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
1600 @param EAX Lower 32-bits of MSR value.
1601 @param EDX Upper 32-bits of MSR value.
1603 <b>Example usage</b>
1607 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
1608 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
1610 @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
1612 #define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19
1616 Package. Uncore C-box 8 perfmon box wide filter1.
1618 @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
1619 @param EAX Lower 32-bits of MSR value.
1620 @param EDX Upper 32-bits of MSR value.
1622 <b>Example usage</b>
1626 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
1627 AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
1629 @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
1631 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A
1635 Package. Uncore C-box 9 perfmon local box wide control.
1637 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
1638 @param EAX Lower 32-bits of MSR value.
1639 @param EDX Upper 32-bits of MSR value.
1641 <b>Example usage</b>
1645 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
1646 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
1648 @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
1650 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24
1654 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
1656 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
1657 @param EAX Lower 32-bits of MSR value.
1658 @param EDX Upper 32-bits of MSR value.
1660 <b>Example usage</b>
1664 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
1665 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
1667 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
1669 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30
1673 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
1675 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
1676 @param EAX Lower 32-bits of MSR value.
1677 @param EDX Upper 32-bits of MSR value.
1679 <b>Example usage</b>
1683 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
1684 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
1686 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
1688 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31
1692 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
1694 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
1695 @param EAX Lower 32-bits of MSR value.
1696 @param EDX Upper 32-bits of MSR value.
1698 <b>Example usage</b>
1702 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
1703 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
1705 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
1707 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32
1711 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
1713 @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
1714 @param EAX Lower 32-bits of MSR value.
1715 @param EDX Upper 32-bits of MSR value.
1717 <b>Example usage</b>
1721 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
1722 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
1724 @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
1726 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33
1730 Package. Uncore C-box 9 perfmon box wide filter.
1732 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
1733 @param EAX Lower 32-bits of MSR value.
1734 @param EDX Upper 32-bits of MSR value.
1736 <b>Example usage</b>
1740 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
1741 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
1743 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
1745 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34
1749 Package. Uncore C-box 9 perfmon counter 0.
1751 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
1752 @param EAX Lower 32-bits of MSR value.
1753 @param EDX Upper 32-bits of MSR value.
1755 <b>Example usage</b>
1759 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
1760 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
1762 @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
1764 #define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36
1768 Package. Uncore C-box 9 perfmon counter 1.
1770 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
1771 @param EAX Lower 32-bits of MSR value.
1772 @param EDX Upper 32-bits of MSR value.
1774 <b>Example usage</b>
1778 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
1779 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
1781 @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
1783 #define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37
1787 Package. Uncore C-box 9 perfmon counter 2.
1789 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
1790 @param EAX Lower 32-bits of MSR value.
1791 @param EDX Upper 32-bits of MSR value.
1793 <b>Example usage</b>
1797 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
1798 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
1800 @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
1802 #define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38
1806 Package. Uncore C-box 9 perfmon counter 3.
1808 @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
1809 @param EAX Lower 32-bits of MSR value.
1810 @param EDX Upper 32-bits of MSR value.
1812 <b>Example usage</b>
1816 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
1817 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
1819 @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
1821 #define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39
1825 Package. Uncore C-box 9 perfmon box wide filter1.
1827 @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
1828 @param EAX Lower 32-bits of MSR value.
1829 @param EDX Upper 32-bits of MSR value.
1831 <b>Example usage</b>
1835 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
1836 AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
1838 @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
1840 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A
1844 Package. Uncore C-box 10 perfmon local box wide control.
1846 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
1847 @param EAX Lower 32-bits of MSR value.
1848 @param EDX Upper 32-bits of MSR value.
1850 <b>Example usage</b>
1854 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
1855 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
1857 @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
1859 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44
1863 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
1865 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
1866 @param EAX Lower 32-bits of MSR value.
1867 @param EDX Upper 32-bits of MSR value.
1869 <b>Example usage</b>
1873 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
1874 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
1876 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
1878 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50
1882 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
1884 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
1885 @param EAX Lower 32-bits of MSR value.
1886 @param EDX Upper 32-bits of MSR value.
1888 <b>Example usage</b>
1892 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
1893 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
1895 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
1897 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51
1901 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
1903 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
1904 @param EAX Lower 32-bits of MSR value.
1905 @param EDX Upper 32-bits of MSR value.
1907 <b>Example usage</b>
1911 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
1912 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
1914 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
1916 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52
1920 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
1922 @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
1923 @param EAX Lower 32-bits of MSR value.
1924 @param EDX Upper 32-bits of MSR value.
1926 <b>Example usage</b>
1930 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
1931 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
1933 @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
1935 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53
1939 Package. Uncore C-box 10 perfmon box wide filter.
1941 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
1942 @param EAX Lower 32-bits of MSR value.
1943 @param EDX Upper 32-bits of MSR value.
1945 <b>Example usage</b>
1949 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
1950 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
1952 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
1954 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54
1958 Package. Uncore C-box 10 perfmon counter 0.
1960 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
1961 @param EAX Lower 32-bits of MSR value.
1962 @param EDX Upper 32-bits of MSR value.
1964 <b>Example usage</b>
1968 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
1969 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
1971 @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
1973 #define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56
1977 Package. Uncore C-box 10 perfmon counter 1.
1979 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
1980 @param EAX Lower 32-bits of MSR value.
1981 @param EDX Upper 32-bits of MSR value.
1983 <b>Example usage</b>
1987 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
1988 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
1990 @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
1992 #define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57
1996 Package. Uncore C-box 10 perfmon counter 2.
1998 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
1999 @param EAX Lower 32-bits of MSR value.
2000 @param EDX Upper 32-bits of MSR value.
2002 <b>Example usage</b>
2006 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
2007 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
2009 @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
2011 #define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58
2015 Package. Uncore C-box 10 perfmon counter 3.
2017 @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
2018 @param EAX Lower 32-bits of MSR value.
2019 @param EDX Upper 32-bits of MSR value.
2021 <b>Example usage</b>
2025 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
2026 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
2028 @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
2030 #define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59
2034 Package. Uncore C-box 10 perfmon box wide filter1.
2036 @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
2037 @param EAX Lower 32-bits of MSR value.
2038 @param EDX Upper 32-bits of MSR value.
2040 <b>Example usage</b>
2044 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
2045 AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
2047 @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
2049 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A
2053 Package. Uncore C-box 11 perfmon local box wide control.
2055 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
2056 @param EAX Lower 32-bits of MSR value.
2057 @param EDX Upper 32-bits of MSR value.
2059 <b>Example usage</b>
2063 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
2064 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
2066 @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
2068 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64
2072 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
2074 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
2075 @param EAX Lower 32-bits of MSR value.
2076 @param EDX Upper 32-bits of MSR value.
2078 <b>Example usage</b>
2082 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
2083 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
2085 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
2087 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70
2091 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
2093 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
2094 @param EAX Lower 32-bits of MSR value.
2095 @param EDX Upper 32-bits of MSR value.
2097 <b>Example usage</b>
2101 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
2102 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
2104 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
2106 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71
2110 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
2112 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
2113 @param EAX Lower 32-bits of MSR value.
2114 @param EDX Upper 32-bits of MSR value.
2116 <b>Example usage</b>
2120 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
2121 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
2123 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
2125 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72
2129 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
2131 @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
2132 @param EAX Lower 32-bits of MSR value.
2133 @param EDX Upper 32-bits of MSR value.
2135 <b>Example usage</b>
2139 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
2140 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
2142 @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
2144 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73
2148 Package. Uncore C-box 11 perfmon box wide filter.
2150 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
2151 @param EAX Lower 32-bits of MSR value.
2152 @param EDX Upper 32-bits of MSR value.
2154 <b>Example usage</b>
2158 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
2159 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
2161 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
2163 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74
2167 Package. Uncore C-box 11 perfmon counter 0.
2169 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
2170 @param EAX Lower 32-bits of MSR value.
2171 @param EDX Upper 32-bits of MSR value.
2173 <b>Example usage</b>
2177 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
2178 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
2180 @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
2182 #define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76
2186 Package. Uncore C-box 11 perfmon counter 1.
2188 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
2189 @param EAX Lower 32-bits of MSR value.
2190 @param EDX Upper 32-bits of MSR value.
2192 <b>Example usage</b>
2196 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
2197 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
2199 @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
2201 #define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77
2205 Package. Uncore C-box 11 perfmon counter 2.
2207 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
2208 @param EAX Lower 32-bits of MSR value.
2209 @param EDX Upper 32-bits of MSR value.
2211 <b>Example usage</b>
2215 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
2216 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
2218 @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
2220 #define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78
2224 Package. Uncore C-box 11 perfmon counter 3.
2226 @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
2227 @param EAX Lower 32-bits of MSR value.
2228 @param EDX Upper 32-bits of MSR value.
2230 <b>Example usage</b>
2234 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
2235 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
2237 @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
2239 #define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79
2243 Package. Uncore C-box 11 perfmon box wide filter1.
2245 @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
2246 @param EAX Lower 32-bits of MSR value.
2247 @param EDX Upper 32-bits of MSR value.
2249 <b>Example usage</b>
2253 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
2254 AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
2256 @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
2258 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A
2262 Package. Uncore C-box 12 perfmon local box wide control.
2264 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
2265 @param EAX Lower 32-bits of MSR value.
2266 @param EDX Upper 32-bits of MSR value.
2268 <b>Example usage</b>
2272 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
2273 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
2275 @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
2277 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84
2281 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
2283 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
2284 @param EAX Lower 32-bits of MSR value.
2285 @param EDX Upper 32-bits of MSR value.
2287 <b>Example usage</b>
2291 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
2292 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
2294 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
2296 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90
2300 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
2302 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
2303 @param EAX Lower 32-bits of MSR value.
2304 @param EDX Upper 32-bits of MSR value.
2306 <b>Example usage</b>
2310 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
2311 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
2313 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
2315 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91
2319 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
2321 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
2322 @param EAX Lower 32-bits of MSR value.
2323 @param EDX Upper 32-bits of MSR value.
2325 <b>Example usage</b>
2329 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
2330 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
2332 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
2334 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92
2338 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
2340 @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
2341 @param EAX Lower 32-bits of MSR value.
2342 @param EDX Upper 32-bits of MSR value.
2344 <b>Example usage</b>
2348 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
2349 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
2351 @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
2353 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93
2357 Package. Uncore C-box 12 perfmon box wide filter.
2359 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
2360 @param EAX Lower 32-bits of MSR value.
2361 @param EDX Upper 32-bits of MSR value.
2363 <b>Example usage</b>
2367 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
2368 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
2370 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
2372 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94
2376 Package. Uncore C-box 12 perfmon counter 0.
2378 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
2379 @param EAX Lower 32-bits of MSR value.
2380 @param EDX Upper 32-bits of MSR value.
2382 <b>Example usage</b>
2386 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
2387 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
2389 @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
2391 #define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96
2395 Package. Uncore C-box 12 perfmon counter 1.
2397 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
2398 @param EAX Lower 32-bits of MSR value.
2399 @param EDX Upper 32-bits of MSR value.
2401 <b>Example usage</b>
2405 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
2406 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
2408 @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
2410 #define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97
2414 Package. Uncore C-box 12 perfmon counter 2.
2416 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
2417 @param EAX Lower 32-bits of MSR value.
2418 @param EDX Upper 32-bits of MSR value.
2420 <b>Example usage</b>
2424 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
2425 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
2427 @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
2429 #define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98
2433 Package. Uncore C-box 12 perfmon counter 3.
2435 @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
2436 @param EAX Lower 32-bits of MSR value.
2437 @param EDX Upper 32-bits of MSR value.
2439 <b>Example usage</b>
2443 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
2444 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
2446 @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
2448 #define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99
2452 Package. Uncore C-box 12 perfmon box wide filter1.
2454 @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
2455 @param EAX Lower 32-bits of MSR value.
2456 @param EDX Upper 32-bits of MSR value.
2458 <b>Example usage</b>
2462 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
2463 AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
2465 @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
2467 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A
2471 Package. Uncore C-box 13 perfmon local box wide control.
2473 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
2474 @param EAX Lower 32-bits of MSR value.
2475 @param EDX Upper 32-bits of MSR value.
2477 <b>Example usage</b>
2481 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
2482 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
2484 @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
2486 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4
2490 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
2492 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
2493 @param EAX Lower 32-bits of MSR value.
2494 @param EDX Upper 32-bits of MSR value.
2496 <b>Example usage</b>
2500 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
2501 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
2503 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
2505 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0
2509 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
2511 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
2512 @param EAX Lower 32-bits of MSR value.
2513 @param EDX Upper 32-bits of MSR value.
2515 <b>Example usage</b>
2519 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
2520 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
2522 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
2524 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1
2528 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
2530 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
2531 @param EAX Lower 32-bits of MSR value.
2532 @param EDX Upper 32-bits of MSR value.
2534 <b>Example usage</b>
2538 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
2539 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
2541 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
2543 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2
2547 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
2549 @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
2550 @param EAX Lower 32-bits of MSR value.
2551 @param EDX Upper 32-bits of MSR value.
2553 <b>Example usage</b>
2557 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
2558 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
2560 @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
2562 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3
2566 Package. Uncore C-box 13 perfmon box wide filter.
2568 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
2569 @param EAX Lower 32-bits of MSR value.
2570 @param EDX Upper 32-bits of MSR value.
2572 <b>Example usage</b>
2576 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
2577 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
2579 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
2581 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4
2585 Package. Uncore C-box 13 perfmon counter 0.
2587 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
2588 @param EAX Lower 32-bits of MSR value.
2589 @param EDX Upper 32-bits of MSR value.
2591 <b>Example usage</b>
2595 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
2596 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
2598 @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
2600 #define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6
2604 Package. Uncore C-box 13 perfmon counter 1.
2606 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
2607 @param EAX Lower 32-bits of MSR value.
2608 @param EDX Upper 32-bits of MSR value.
2610 <b>Example usage</b>
2614 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
2615 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
2617 @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
2619 #define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7
2623 Package. Uncore C-box 13 perfmon counter 2.
2625 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
2626 @param EAX Lower 32-bits of MSR value.
2627 @param EDX Upper 32-bits of MSR value.
2629 <b>Example usage</b>
2633 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
2634 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
2636 @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
2638 #define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8
2642 Package. Uncore C-box 13 perfmon counter 3.
2644 @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
2645 @param EAX Lower 32-bits of MSR value.
2646 @param EDX Upper 32-bits of MSR value.
2648 <b>Example usage</b>
2652 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
2653 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
2655 @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
2657 #define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9
2661 Package. Uncore C-box 13 perfmon box wide filter1.
2663 @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
2664 @param EAX Lower 32-bits of MSR value.
2665 @param EDX Upper 32-bits of MSR value.
2667 <b>Example usage</b>
2671 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
2672 AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
2674 @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
2676 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA
2680 Package. Uncore C-box 14 perfmon local box wide control.
2682 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
2683 @param EAX Lower 32-bits of MSR value.
2684 @param EDX Upper 32-bits of MSR value.
2686 <b>Example usage</b>
2690 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
2691 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
2693 @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
2695 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4
2699 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
2701 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
2702 @param EAX Lower 32-bits of MSR value.
2703 @param EDX Upper 32-bits of MSR value.
2705 <b>Example usage</b>
2709 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
2710 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
2712 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
2714 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0
2718 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
2720 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
2721 @param EAX Lower 32-bits of MSR value.
2722 @param EDX Upper 32-bits of MSR value.
2724 <b>Example usage</b>
2728 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
2729 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
2731 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
2733 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1
2737 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
2739 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
2740 @param EAX Lower 32-bits of MSR value.
2741 @param EDX Upper 32-bits of MSR value.
2743 <b>Example usage</b>
2747 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
2748 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
2750 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
2752 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2
2756 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
2758 @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
2759 @param EAX Lower 32-bits of MSR value.
2760 @param EDX Upper 32-bits of MSR value.
2762 <b>Example usage</b>
2766 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
2767 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
2769 @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
2771 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3
2775 Package. Uncore C-box 14 perfmon box wide filter.
2777 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
2778 @param EAX Lower 32-bits of MSR value.
2779 @param EDX Upper 32-bits of MSR value.
2781 <b>Example usage</b>
2785 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
2786 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
2788 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
2790 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4
2794 Package. Uncore C-box 14 perfmon counter 0.
2796 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
2797 @param EAX Lower 32-bits of MSR value.
2798 @param EDX Upper 32-bits of MSR value.
2800 <b>Example usage</b>
2804 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
2805 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
2807 @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
2809 #define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6
2813 Package. Uncore C-box 14 perfmon counter 1.
2815 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
2816 @param EAX Lower 32-bits of MSR value.
2817 @param EDX Upper 32-bits of MSR value.
2819 <b>Example usage</b>
2823 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
2824 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
2826 @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
2828 #define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7
2832 Package. Uncore C-box 14 perfmon counter 2.
2834 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
2835 @param EAX Lower 32-bits of MSR value.
2836 @param EDX Upper 32-bits of MSR value.
2838 <b>Example usage</b>
2842 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
2843 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
2845 @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
2847 #define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8
2851 Package. Uncore C-box 14 perfmon counter 3.
2853 @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
2854 @param EAX Lower 32-bits of MSR value.
2855 @param EDX Upper 32-bits of MSR value.
2857 <b>Example usage</b>
2861 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
2862 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
2864 @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
2866 #define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9
2870 Package. Uncore C-box 14 perfmon box wide filter1.
2872 @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
2873 @param EAX Lower 32-bits of MSR value.
2874 @param EDX Upper 32-bits of MSR value.
2876 <b>Example usage</b>
2880 Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
2881 AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
2883 @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
2885 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA