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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
2 Cache Maintenance Functions.
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
24 IN CONST VOID
*PalEntryPoint
,
32 Invalidates the entire instruction cache in cache coherency domain of the
35 Invalidates the entire instruction cache in cache coherency domain of the
41 InvalidateInstructionCache (
45 PalCallStatic (NULL
, 1, 1, 1, 0);
49 Writes Back and Invalidates the entire data cache in cache coherency domain
52 Writes Back and Invalidates the entire data cache in cache coherency domain
53 of the calling CPU. This function guarantees that all dirty cache lines are
54 written back to system memory, and also invalidates all the data cache lines
55 in the cache coherency domain of the calling CPU.
60 WriteBackInvalidateDataCache (
64 PalCallStatic (NULL
, 1, 2, 1, 0);
68 Writes Back and Invalidates a range of data cache lines in the cache
69 coherency domain of the calling CPU.
71 Writes Back and Invalidate the data cache lines specified by Address and
72 Length. If Address is not aligned on a cache line boundary, then entire data
73 cache line containing Address is written back and invalidated. If Address +
74 Length is not aligned on a cache line boundary, then the entire data cache
75 line containing Address + Length -1 is written back and invalidated. This
76 function may choose to write back and invalidate the entire data cache if
77 that is more efficient than writing back and invalidating the specified
78 range. If Length is 0, the no data cache lines are written back and
79 invalidated. Address is returned.
81 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
83 @param Address The base address of the data cache lines to write back and
84 invalidate. If the CPU is in a physical addressing mode, then
85 Address is a physical address. If the CPU is in a virtual
86 addressing mode, then Address is a virtual address.
87 @param Length The number of bytes to write back and invalidate from the
95 WriteBackInvalidateDataCacheRange (
100 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
103 WriteBackInvalidateDataCache ();
109 Writes Back the entire data cache in cache coherency domain of the calling
112 Writes Back the entire data cache in cache coherency domain of the calling
113 CPU. This function guarantees that all dirty cache lines are written back to
114 system memory. This function may also invalidate all the data cache lines in
115 the cache coherency domain of the calling CPU.
124 PalCallStatic (NULL
, 1, 2, 0, 0);
128 Writes Back a range of data cache lines in the cache coherency domain of the
131 Writes Back the data cache lines specified by Address and Length. If Address
132 is not aligned on a cache line boundary, then entire data cache line
133 containing Address is written back. If Address + Length is not aligned on a
134 cache line boundary, then the entire data cache line containing Address +
135 Length -1 is written back. This function may choose to write back the entire
136 data cache if that is more efficient than writing back the specified range.
137 If Length is 0, the no data cache lines are written back. This function may
138 also invalidate all the data cache lines in the specified range of the cache
139 coherency domain of the calling CPU. Address is returned.
141 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
143 @param Address The base address of the data cache lines to write back. If
144 the CPU is in a physical addressing mode, then Address is a
145 physical address. If the CPU is in a virtual addressing
146 mode, then Address is a virtual address.
147 @param Length The number of bytes to write back from the data cache.
154 WriteBackDataCacheRange (
159 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
162 WriteBackDataCache ();
168 Invalidates the entire data cache in cache coherency domain of the calling
171 Invalidates the entire data cache in cache coherency domain of the calling
172 CPU. This function must be used with care because dirty cache lines are not
173 written back to system memory. It is typically used for cache diagnostics. If
174 the CPU does not support invalidation of the entire data cache, then a write
175 back and invalidate operation should be performed on the entire data cache.
180 InvalidateDataCache (
184 WriteBackInvalidateDataCache ();
188 Invalidates a range of data cache lines in the cache coherency domain of the
191 Invalidates the data cache lines specified by Address and Length. If Address
192 is not aligned on a cache line boundary, then entire data cache line
193 containing Address is invalidated. If Address + Length is not aligned on a
194 cache line boundary, then the entire data cache line containing Address +
195 Length -1 is invalidated. This function must never invalidate any cache lines
196 outside the specified range. If Length is 0, the no data cache lines are
197 invalidated. Address is returned. This function must be used with care
198 because dirty cache lines are not written back to system memory. It is
199 typically used for cache diagnostics. If the CPU does not support
200 invalidation of a data cache range, then a write back and invalidate
201 operation should be performed on the data cache range.
203 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
205 @param Address The base address of the data cache lines to invalidate. If
206 the CPU is in a physical addressing mode, then Address is a
207 physical address. If the CPU is in a virtual addressing mode,
208 then Address is a virtual address.
209 @param Length The number of bytes to invalidate from the data cache.
216 InvalidateDataCacheRange (
221 return WriteBackInvalidateDataCacheRange (Address
, Length
);