]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciExpressLib.c
2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
30 Assert the validity of a PCI address. A valid PCI address should contain 1's
31 only in the low 28 bits.
33 @param A The address to validate.
36 #define ASSERT_INVALID_PCI_ADDRESS(A) \
37 ASSERT (((A) & ~0xfffffff) == 0)
41 Gets the base address of PCI Express.
43 This internal functions retrieves PCI Express Base Address via a PCD entry
44 PcdPciExpressBaseAddress.
46 @return The base address of PCI Express.
50 GetPciExpressBaseAddress (
54 return (VOID
*)(UINTN
) PcdGet64 (PcdPciExpressBaseAddress
);
58 Reads an 8-bit PCI configuration register.
60 Reads and returns the 8-bit PCI configuration register specified by Address.
61 This function must guarantee that all PCI read and write operations are
64 If Address > 0x0FFFFFFF, then ASSERT().
66 @param Address Address that encodes the PCI Bus, Device, Function and
69 @return The read value from the PCI configuration register.
78 ASSERT_INVALID_PCI_ADDRESS (Address
);
79 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
83 Writes an 8-bit PCI configuration register.
85 Writes the 8-bit PCI configuration register specified by Address with the
86 value specified by Value. Value is returned. This function must guarantee
87 that all PCI read and write operations are serialized.
89 If Address > 0x0FFFFFFF, then ASSERT().
91 @param Address Address that encodes the PCI Bus, Device, Function and
93 @param Value The value to write.
95 @return The value written to the PCI configuration register.
105 ASSERT_INVALID_PCI_ADDRESS (Address
);
106 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
110 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
113 Reads the 8-bit PCI configuration register specified by Address, performs a
114 bitwise inclusive OR between the read result and the value specified by
115 OrData, and writes the result to the 8-bit PCI configuration register
116 specified by Address. The value written to the PCI configuration register is
117 returned. This function must guarantee that all PCI read and write operations
120 If Address > 0x0FFFFFFF, then ASSERT().
122 @param Address Address that encodes the PCI Bus, Device, Function and
124 @param OrData The value to OR with the PCI configuration register.
126 @return The value written back to the PCI configuration register.
136 ASSERT_INVALID_PCI_ADDRESS (Address
);
137 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
141 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
144 Reads the 8-bit PCI configuration register specified by Address, performs a
145 bitwise AND between the read result and the value specified by AndData, and
146 writes the result to the 8-bit PCI configuration register specified by
147 Address. The value written to the PCI configuration register is returned.
148 This function must guarantee that all PCI read and write operations are
151 If Address > 0x0FFFFFFF, then ASSERT().
153 @param Address Address that encodes the PCI Bus, Device, Function and
155 @param AndData The value to AND with the PCI configuration register.
157 @return The value written back to the PCI configuration register.
167 ASSERT_INVALID_PCI_ADDRESS (Address
);
168 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
172 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
173 value, followed a bitwise inclusive OR with another 8-bit value.
175 Reads the 8-bit PCI configuration register specified by Address, performs a
176 bitwise AND between the read result and the value specified by AndData,
177 performs a bitwise inclusive OR between the result of the AND operation and
178 the value specified by OrData, and writes the result to the 8-bit PCI
179 configuration register specified by Address. The value written to the PCI
180 configuration register is returned. This function must guarantee that all PCI
181 read and write operations are serialized.
183 If Address > 0x0FFFFFFF, then ASSERT().
185 @param Address Address that encodes the PCI Bus, Device, Function and
187 @param AndData The value to AND with the PCI configuration register.
188 @param OrData The value to OR with the result of the AND operation.
190 @return The value written back to the PCI configuration register.
195 PciExpressAndThenOr8 (
201 ASSERT_INVALID_PCI_ADDRESS (Address
);
202 return MmioAndThenOr8 (
203 (UINTN
) GetPciExpressBaseAddress () + Address
,
210 Reads a bit field of a PCI configuration register.
212 Reads the bit field in an 8-bit PCI configuration register. The bit field is
213 specified by the StartBit and the EndBit. The value of the bit field is
216 If Address > 0x0FFFFFFF, then ASSERT().
217 If StartBit is greater than 7, then ASSERT().
218 If EndBit is greater than 7, then ASSERT().
219 If EndBit is less than StartBit, then ASSERT().
221 @param Address PCI configuration register to read.
222 @param StartBit The ordinal of the least significant bit in the bit field.
224 @param EndBit The ordinal of the most significant bit in the bit field.
227 @return The value of the bit field read from the PCI configuration register.
232 PciExpressBitFieldRead8 (
238 ASSERT_INVALID_PCI_ADDRESS (Address
);
239 return MmioBitFieldRead8 (
240 (UINTN
) GetPciExpressBaseAddress () + Address
,
247 Writes a bit field to a PCI configuration register.
249 Writes Value to the bit field of the PCI configuration register. The bit
250 field is specified by the StartBit and the EndBit. All other bits in the
251 destination PCI configuration register are preserved. The new value of the
252 8-bit register is returned.
254 If Address > 0x0FFFFFFF, then ASSERT().
255 If StartBit is greater than 7, then ASSERT().
256 If EndBit is greater than 7, then ASSERT().
257 If EndBit is less than StartBit, then ASSERT().
259 @param Address PCI configuration register to write.
260 @param StartBit The ordinal of the least significant bit in the bit field.
262 @param EndBit The ordinal of the most significant bit in the bit field.
264 @param Value New value of the bit field.
266 @return The value written back to the PCI configuration register.
271 PciExpressBitFieldWrite8 (
278 ASSERT_INVALID_PCI_ADDRESS (Address
);
279 return MmioBitFieldWrite8 (
280 (UINTN
) GetPciExpressBaseAddress () + Address
,
288 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
289 writes the result back to the bit field in the 8-bit port.
291 Reads the 8-bit PCI configuration register specified by Address, performs a
292 bitwise inclusive OR between the read result and the value specified by
293 OrData, and writes the result to the 8-bit PCI configuration register
294 specified by Address. The value written to the PCI configuration register is
295 returned. This function must guarantee that all PCI read and write operations
296 are serialized. Extra left bits in OrData are stripped.
298 If Address > 0x0FFFFFFF, then ASSERT().
299 If StartBit is greater than 7, then ASSERT().
300 If EndBit is greater than 7, then ASSERT().
301 If EndBit is less than StartBit, then ASSERT().
303 @param Address PCI configuration register to write.
304 @param StartBit The ordinal of the least significant bit in the bit field.
306 @param EndBit The ordinal of the most significant bit in the bit field.
308 @param OrData The value to OR with the PCI configuration register.
310 @return The value written back to the PCI configuration register.
315 PciExpressBitFieldOr8 (
322 ASSERT_INVALID_PCI_ADDRESS (Address
);
323 return MmioBitFieldOr8 (
324 (UINTN
) GetPciExpressBaseAddress () + Address
,
332 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
333 AND, and writes the result back to the bit field in the 8-bit register.
335 Reads the 8-bit PCI configuration register specified by Address, performs a
336 bitwise AND between the read result and the value specified by AndData, and
337 writes the result to the 8-bit PCI configuration register specified by
338 Address. The value written to the PCI configuration register is returned.
339 This function must guarantee that all PCI read and write operations are
340 serialized. Extra left bits in AndData are stripped.
342 If Address > 0x0FFFFFFF, then ASSERT().
343 If StartBit is greater than 7, then ASSERT().
344 If EndBit is greater than 7, then ASSERT().
345 If EndBit is less than StartBit, then ASSERT().
347 @param Address PCI configuration register to write.
348 @param StartBit The ordinal of the least significant bit in the bit field.
350 @param EndBit The ordinal of the most significant bit in the bit field.
352 @param AndData The value to AND with the PCI configuration register.
354 @return The value written back to the PCI configuration register.
359 PciExpressBitFieldAnd8 (
366 ASSERT_INVALID_PCI_ADDRESS (Address
);
367 return MmioBitFieldAnd8 (
368 (UINTN
) GetPciExpressBaseAddress () + Address
,
376 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
377 bitwise inclusive OR, and writes the result back to the bit field in the
380 Reads the 8-bit PCI configuration register specified by Address, performs a
381 bitwise AND followed by a bitwise inclusive OR between the read result and
382 the value specified by AndData, and writes the result to the 8-bit PCI
383 configuration register specified by Address. The value written to the PCI
384 configuration register is returned. This function must guarantee that all PCI
385 read and write operations are serialized. Extra left bits in both AndData and
388 If Address > 0x0FFFFFFF, then ASSERT().
389 If StartBit is greater than 7, then ASSERT().
390 If EndBit is greater than 7, then ASSERT().
391 If EndBit is less than StartBit, then ASSERT().
393 @param Address PCI configuration register to write.
394 @param StartBit The ordinal of the least significant bit in the bit field.
396 @param EndBit The ordinal of the most significant bit in the bit field.
398 @param AndData The value to AND with the PCI configuration register.
399 @param OrData The value to OR with the result of the AND operation.
401 @return The value written back to the PCI configuration register.
406 PciExpressBitFieldAndThenOr8 (
414 ASSERT_INVALID_PCI_ADDRESS (Address
);
415 return MmioBitFieldAndThenOr8 (
416 (UINTN
) GetPciExpressBaseAddress () + Address
,
425 Reads a 16-bit PCI configuration register.
427 Reads and returns the 16-bit PCI configuration register specified by Address.
428 This function must guarantee that all PCI read and write operations are
431 If Address > 0x0FFFFFFF, then ASSERT().
432 If Address is not aligned on a 16-bit boundary, then ASSERT().
434 @param Address Address that encodes the PCI Bus, Device, Function and
437 @return The read value from the PCI configuration register.
446 ASSERT_INVALID_PCI_ADDRESS (Address
);
447 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
451 Writes a 16-bit PCI configuration register.
453 Writes the 16-bit PCI configuration register specified by Address with the
454 value specified by Value. Value is returned. This function must guarantee
455 that all PCI read and write operations are serialized.
457 If Address > 0x0FFFFFFF, then ASSERT().
458 If Address is not aligned on a 16-bit boundary, then ASSERT().
460 @param Address Address that encodes the PCI Bus, Device, Function and
462 @param Value The value to write.
464 @return The value written to the PCI configuration register.
474 ASSERT_INVALID_PCI_ADDRESS (Address
);
475 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
479 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
482 Reads the 16-bit PCI configuration register specified by Address, performs a
483 bitwise inclusive OR between the read result and the value specified by
484 OrData, and writes the result to the 16-bit PCI configuration register
485 specified by Address. The value written to the PCI configuration register is
486 returned. This function must guarantee that all PCI read and write operations
489 If Address > 0x0FFFFFFF, then ASSERT().
490 If Address is not aligned on a 16-bit boundary, then ASSERT().
492 @param Address Address that encodes the PCI Bus, Device, Function and
494 @param OrData The value to OR with the PCI configuration register.
496 @return The value written back to the PCI configuration register.
506 ASSERT_INVALID_PCI_ADDRESS (Address
);
507 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
511 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
514 Reads the 16-bit PCI configuration register specified by Address, performs a
515 bitwise AND between the read result and the value specified by AndData, and
516 writes the result to the 16-bit PCI configuration register specified by
517 Address. The value written to the PCI configuration register is returned.
518 This function must guarantee that all PCI read and write operations are
521 If Address > 0x0FFFFFFF, then ASSERT().
522 If Address is not aligned on a 16-bit boundary, then ASSERT().
524 @param Address Address that encodes the PCI Bus, Device, Function and
526 @param AndData The value to AND with the PCI configuration register.
528 @return The value written back to the PCI configuration register.
538 ASSERT_INVALID_PCI_ADDRESS (Address
);
539 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
543 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
544 value, followed a bitwise inclusive OR with another 16-bit value.
546 Reads the 16-bit PCI configuration register specified by Address, performs a
547 bitwise AND between the read result and the value specified by AndData,
548 performs a bitwise inclusive OR between the result of the AND operation and
549 the value specified by OrData, and writes the result to the 16-bit PCI
550 configuration register specified by Address. The value written to the PCI
551 configuration register is returned. This function must guarantee that all PCI
552 read and write operations are serialized.
554 If Address > 0x0FFFFFFF, then ASSERT().
555 If Address is not aligned on a 16-bit boundary, then ASSERT().
557 @param Address Address that encodes the PCI Bus, Device, Function and
559 @param AndData The value to AND with the PCI configuration register.
560 @param OrData The value to OR with the result of the AND operation.
562 @return The value written back to the PCI configuration register.
567 PciExpressAndThenOr16 (
573 ASSERT_INVALID_PCI_ADDRESS (Address
);
574 return MmioAndThenOr16 (
575 (UINTN
) GetPciExpressBaseAddress () + Address
,
582 Reads a bit field of a PCI configuration register.
584 Reads the bit field in a 16-bit PCI configuration register. The bit field is
585 specified by the StartBit and the EndBit. The value of the bit field is
588 If Address > 0x0FFFFFFF, then ASSERT().
589 If Address is not aligned on a 16-bit boundary, then ASSERT().
590 If StartBit is greater than 15, then ASSERT().
591 If EndBit is greater than 15, then ASSERT().
592 If EndBit is less than StartBit, then ASSERT().
594 @param Address PCI configuration register to read.
595 @param StartBit The ordinal of the least significant bit in the bit field.
597 @param EndBit The ordinal of the most significant bit in the bit field.
600 @return The value of the bit field read from the PCI configuration register.
605 PciExpressBitFieldRead16 (
611 ASSERT_INVALID_PCI_ADDRESS (Address
);
612 return MmioBitFieldRead16 (
613 (UINTN
) GetPciExpressBaseAddress () + Address
,
620 Writes a bit field to a PCI configuration register.
622 Writes Value to the bit field of the PCI configuration register. The bit
623 field is specified by the StartBit and the EndBit. All other bits in the
624 destination PCI configuration register are preserved. The new value of the
625 16-bit register is returned.
627 If Address > 0x0FFFFFFF, then ASSERT().
628 If Address is not aligned on a 16-bit boundary, then ASSERT().
629 If StartBit is greater than 15, then ASSERT().
630 If EndBit is greater than 15, then ASSERT().
631 If EndBit is less than StartBit, then ASSERT().
633 @param Address PCI configuration register to write.
634 @param StartBit The ordinal of the least significant bit in the bit field.
636 @param EndBit The ordinal of the most significant bit in the bit field.
638 @param Value New value of the bit field.
640 @return The value written back to the PCI configuration register.
645 PciExpressBitFieldWrite16 (
652 ASSERT_INVALID_PCI_ADDRESS (Address
);
653 return MmioBitFieldWrite16 (
654 (UINTN
) GetPciExpressBaseAddress () + Address
,
662 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
663 writes the result back to the bit field in the 16-bit port.
665 Reads the 16-bit PCI configuration register specified by Address, performs a
666 bitwise inclusive OR between the read result and the value specified by
667 OrData, and writes the result to the 16-bit PCI configuration register
668 specified by Address. The value written to the PCI configuration register is
669 returned. This function must guarantee that all PCI read and write operations
670 are serialized. Extra left bits in OrData are stripped.
672 If Address > 0x0FFFFFFF, then ASSERT().
673 If Address is not aligned on a 16-bit boundary, then ASSERT().
674 If StartBit is greater than 15, then ASSERT().
675 If EndBit is greater than 15, then ASSERT().
676 If EndBit is less than StartBit, then ASSERT().
678 @param Address PCI configuration register to write.
679 @param StartBit The ordinal of the least significant bit in the bit field.
681 @param EndBit The ordinal of the most significant bit in the bit field.
683 @param OrData The value to OR with the PCI configuration register.
685 @return The value written back to the PCI configuration register.
690 PciExpressBitFieldOr16 (
697 ASSERT_INVALID_PCI_ADDRESS (Address
);
698 return MmioBitFieldOr16 (
699 (UINTN
) GetPciExpressBaseAddress () + Address
,
707 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
708 AND, and writes the result back to the bit field in the 16-bit register.
710 Reads the 16-bit PCI configuration register specified by Address, performs a
711 bitwise AND between the read result and the value specified by AndData, and
712 writes the result to the 16-bit PCI configuration register specified by
713 Address. The value written to the PCI configuration register is returned.
714 This function must guarantee that all PCI read and write operations are
715 serialized. Extra left bits in AndData are stripped.
717 If Address > 0x0FFFFFFF, then ASSERT().
718 If Address is not aligned on a 16-bit boundary, then ASSERT().
719 If StartBit is greater than 15, then ASSERT().
720 If EndBit is greater than 15, then ASSERT().
721 If EndBit is less than StartBit, then ASSERT().
723 @param Address PCI configuration register to write.
724 @param StartBit The ordinal of the least significant bit in the bit field.
726 @param EndBit The ordinal of the most significant bit in the bit field.
728 @param AndData The value to AND with the PCI configuration register.
730 @return The value written back to the PCI configuration register.
735 PciExpressBitFieldAnd16 (
742 ASSERT_INVALID_PCI_ADDRESS (Address
);
743 return MmioBitFieldAnd16 (
744 (UINTN
) GetPciExpressBaseAddress () + Address
,
752 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
753 bitwise inclusive OR, and writes the result back to the bit field in the
756 Reads the 16-bit PCI configuration register specified by Address, performs a
757 bitwise AND followed by a bitwise inclusive OR between the read result and
758 the value specified by AndData, and writes the result to the 16-bit PCI
759 configuration register specified by Address. The value written to the PCI
760 configuration register is returned. This function must guarantee that all PCI
761 read and write operations are serialized. Extra left bits in both AndData and
764 If Address > 0x0FFFFFFF, then ASSERT().
765 If Address is not aligned on a 16-bit boundary, then ASSERT().
766 If StartBit is greater than 15, then ASSERT().
767 If EndBit is greater than 15, then ASSERT().
768 If EndBit is less than StartBit, then ASSERT().
770 @param Address PCI configuration register to write.
771 @param StartBit The ordinal of the least significant bit in the bit field.
773 @param EndBit The ordinal of the most significant bit in the bit field.
775 @param AndData The value to AND with the PCI configuration register.
776 @param OrData The value to OR with the result of the AND operation.
778 @return The value written back to the PCI configuration register.
783 PciExpressBitFieldAndThenOr16 (
791 ASSERT_INVALID_PCI_ADDRESS (Address
);
792 return MmioBitFieldAndThenOr16 (
793 (UINTN
) GetPciExpressBaseAddress () + Address
,
802 Reads a 32-bit PCI configuration register.
804 Reads and returns the 32-bit PCI configuration register specified by Address.
805 This function must guarantee that all PCI read and write operations are
808 If Address > 0x0FFFFFFF, then ASSERT().
809 If Address is not aligned on a 32-bit boundary, then ASSERT().
811 @param Address Address that encodes the PCI Bus, Device, Function and
814 @return The read value from the PCI configuration register.
823 ASSERT_INVALID_PCI_ADDRESS (Address
);
824 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
828 Writes a 32-bit PCI configuration register.
830 Writes the 32-bit PCI configuration register specified by Address with the
831 value specified by Value. Value is returned. This function must guarantee
832 that all PCI read and write operations are serialized.
834 If Address > 0x0FFFFFFF, then ASSERT().
835 If Address is not aligned on a 32-bit boundary, then ASSERT().
837 @param Address Address that encodes the PCI Bus, Device, Function and
839 @param Value The value to write.
841 @return The value written to the PCI configuration register.
851 ASSERT_INVALID_PCI_ADDRESS (Address
);
852 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
856 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
859 Reads the 32-bit PCI configuration register specified by Address, performs a
860 bitwise inclusive OR between the read result and the value specified by
861 OrData, and writes the result to the 32-bit PCI configuration register
862 specified by Address. The value written to the PCI configuration register is
863 returned. This function must guarantee that all PCI read and write operations
866 If Address > 0x0FFFFFFF, then ASSERT().
867 If Address is not aligned on a 32-bit boundary, then ASSERT().
869 @param Address Address that encodes the PCI Bus, Device, Function and
871 @param OrData The value to OR with the PCI configuration register.
873 @return The value written back to the PCI configuration register.
883 ASSERT_INVALID_PCI_ADDRESS (Address
);
884 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
888 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
891 Reads the 32-bit PCI configuration register specified by Address, performs a
892 bitwise AND between the read result and the value specified by AndData, and
893 writes the result to the 32-bit PCI configuration register specified by
894 Address. The value written to the PCI configuration register is returned.
895 This function must guarantee that all PCI read and write operations are
898 If Address > 0x0FFFFFFF, then ASSERT().
899 If Address is not aligned on a 32-bit boundary, then ASSERT().
901 @param Address Address that encodes the PCI Bus, Device, Function and
903 @param AndData The value to AND with the PCI configuration register.
905 @return The value written back to the PCI configuration register.
915 ASSERT_INVALID_PCI_ADDRESS (Address
);
916 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
920 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
921 value, followed a bitwise inclusive OR with another 32-bit value.
923 Reads the 32-bit PCI configuration register specified by Address, performs a
924 bitwise AND between the read result and the value specified by AndData,
925 performs a bitwise inclusive OR between the result of the AND operation and
926 the value specified by OrData, and writes the result to the 32-bit PCI
927 configuration register specified by Address. The value written to the PCI
928 configuration register is returned. This function must guarantee that all PCI
929 read and write operations are serialized.
931 If Address > 0x0FFFFFFF, then ASSERT().
932 If Address is not aligned on a 32-bit boundary, then ASSERT().
934 @param Address Address that encodes the PCI Bus, Device, Function and
936 @param AndData The value to AND with the PCI configuration register.
937 @param OrData The value to OR with the result of the AND operation.
939 @return The value written back to the PCI configuration register.
944 PciExpressAndThenOr32 (
950 ASSERT_INVALID_PCI_ADDRESS (Address
);
951 return MmioAndThenOr32 (
952 (UINTN
) GetPciExpressBaseAddress () + Address
,
959 Reads a bit field of a PCI configuration register.
961 Reads the bit field in a 32-bit PCI configuration register. The bit field is
962 specified by the StartBit and the EndBit. The value of the bit field is
965 If Address > 0x0FFFFFFF, then ASSERT().
966 If Address is not aligned on a 32-bit boundary, then ASSERT().
967 If StartBit is greater than 31, then ASSERT().
968 If EndBit is greater than 31, then ASSERT().
969 If EndBit is less than StartBit, then ASSERT().
971 @param Address PCI configuration register to read.
972 @param StartBit The ordinal of the least significant bit in the bit field.
974 @param EndBit The ordinal of the most significant bit in the bit field.
977 @return The value of the bit field read from the PCI configuration register.
982 PciExpressBitFieldRead32 (
988 ASSERT_INVALID_PCI_ADDRESS (Address
);
989 return MmioBitFieldRead32 (
990 (UINTN
) GetPciExpressBaseAddress () + Address
,
997 Writes a bit field to a PCI configuration register.
999 Writes Value to the bit field of the PCI configuration register. The bit
1000 field is specified by the StartBit and the EndBit. All other bits in the
1001 destination PCI configuration register are preserved. The new value of the
1002 32-bit register is returned.
1004 If Address > 0x0FFFFFFF, then ASSERT().
1005 If Address is not aligned on a 32-bit boundary, then ASSERT().
1006 If StartBit is greater than 31, then ASSERT().
1007 If EndBit is greater than 31, then ASSERT().
1008 If EndBit is less than StartBit, then ASSERT().
1010 @param Address PCI configuration register to write.
1011 @param StartBit The ordinal of the least significant bit in the bit field.
1013 @param EndBit The ordinal of the most significant bit in the bit field.
1015 @param Value New value of the bit field.
1017 @return The value written back to the PCI configuration register.
1022 PciExpressBitFieldWrite32 (
1029 ASSERT_INVALID_PCI_ADDRESS (Address
);
1030 return MmioBitFieldWrite32 (
1031 (UINTN
) GetPciExpressBaseAddress () + Address
,
1039 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1040 writes the result back to the bit field in the 32-bit port.
1042 Reads the 32-bit PCI configuration register specified by Address, performs a
1043 bitwise inclusive OR between the read result and the value specified by
1044 OrData, and writes the result to the 32-bit PCI configuration register
1045 specified by Address. The value written to the PCI configuration register is
1046 returned. This function must guarantee that all PCI read and write operations
1047 are serialized. Extra left bits in OrData are stripped.
1049 If Address > 0x0FFFFFFF, then ASSERT().
1050 If Address is not aligned on a 32-bit boundary, then ASSERT().
1051 If StartBit is greater than 31, then ASSERT().
1052 If EndBit is greater than 31, then ASSERT().
1053 If EndBit is less than StartBit, then ASSERT().
1055 @param Address PCI configuration register to write.
1056 @param StartBit The ordinal of the least significant bit in the bit field.
1058 @param EndBit The ordinal of the most significant bit in the bit field.
1060 @param OrData The value to OR with the PCI configuration register.
1062 @return The value written back to the PCI configuration register.
1067 PciExpressBitFieldOr32 (
1074 ASSERT_INVALID_PCI_ADDRESS (Address
);
1075 return MmioBitFieldOr32 (
1076 (UINTN
) GetPciExpressBaseAddress () + Address
,
1084 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1085 AND, and writes the result back to the bit field in the 32-bit register.
1087 Reads the 32-bit PCI configuration register specified by Address, performs a
1088 bitwise AND between the read result and the value specified by AndData, and
1089 writes the result to the 32-bit PCI configuration register specified by
1090 Address. The value written to the PCI configuration register is returned.
1091 This function must guarantee that all PCI read and write operations are
1092 serialized. Extra left bits in AndData are stripped.
1094 If Address > 0x0FFFFFFF, then ASSERT().
1095 If Address is not aligned on a 32-bit boundary, then ASSERT().
1096 If StartBit is greater than 31, then ASSERT().
1097 If EndBit is greater than 31, then ASSERT().
1098 If EndBit is less than StartBit, then ASSERT().
1100 @param Address PCI configuration register to write.
1101 @param StartBit The ordinal of the least significant bit in the bit field.
1103 @param EndBit The ordinal of the most significant bit in the bit field.
1105 @param AndData The value to AND with the PCI configuration register.
1107 @return The value written back to the PCI configuration register.
1112 PciExpressBitFieldAnd32 (
1119 ASSERT_INVALID_PCI_ADDRESS (Address
);
1120 return MmioBitFieldAnd32 (
1121 (UINTN
) GetPciExpressBaseAddress () + Address
,
1129 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1130 bitwise inclusive OR, and writes the result back to the bit field in the
1133 Reads the 32-bit PCI configuration register specified by Address, performs a
1134 bitwise AND followed by a bitwise inclusive OR between the read result and
1135 the value specified by AndData, and writes the result to the 32-bit PCI
1136 configuration register specified by Address. The value written to the PCI
1137 configuration register is returned. This function must guarantee that all PCI
1138 read and write operations are serialized. Extra left bits in both AndData and
1139 OrData are stripped.
1141 If Address > 0x0FFFFFFF, then ASSERT().
1142 If Address is not aligned on a 32-bit boundary, then ASSERT().
1143 If StartBit is greater than 31, then ASSERT().
1144 If EndBit is greater than 31, then ASSERT().
1145 If EndBit is less than StartBit, then ASSERT().
1147 @param Address PCI configuration register to write.
1148 @param StartBit The ordinal of the least significant bit in the bit field.
1150 @param EndBit The ordinal of the most significant bit in the bit field.
1152 @param AndData The value to AND with the PCI configuration register.
1153 @param OrData The value to OR with the result of the AND operation.
1155 @return The value written back to the PCI configuration register.
1160 PciExpressBitFieldAndThenOr32 (
1168 ASSERT_INVALID_PCI_ADDRESS (Address
);
1169 return MmioBitFieldAndThenOr32 (
1170 (UINTN
) GetPciExpressBaseAddress () + Address
,
1179 Reads a range of PCI configuration registers into a caller supplied buffer.
1181 Reads the range of PCI configuration registers specified by StartAddress and
1182 Size into the buffer specified by Buffer. This function only allows the PCI
1183 configuration registers from a single PCI function to be read. Size is
1184 returned. When possible 32-bit PCI configuration read cycles are used to read
1185 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1186 and 16-bit PCI configuration read cycles may be used at the beginning and the
1189 If StartAddress > 0x0FFFFFFF, then ASSERT().
1190 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1191 If Size > 0 and Buffer is NULL, then ASSERT().
1193 @param StartAddress Starting address that encodes the PCI Bus, Device,
1194 Function and Register.
1195 @param Size Size in bytes of the transfer.
1196 @param Buffer Pointer to a buffer receiving the data read.
1203 PciExpressReadBuffer (
1204 IN UINTN StartAddress
,
1211 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1212 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1218 ASSERT (Buffer
!= NULL
);
1221 // Save Size for return
1225 if ((StartAddress
& 1) != 0) {
1227 // Read a byte if StartAddress is byte aligned
1229 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1230 StartAddress
+= sizeof (UINT8
);
1231 Size
-= sizeof (UINT8
);
1232 Buffer
= (UINT8
*)Buffer
+ 1;
1235 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1237 // Read a word if StartAddress is word aligned
1239 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1241 StartAddress
+= sizeof (UINT16
);
1242 Size
-= sizeof (UINT16
);
1243 Buffer
= (UINT16
*)Buffer
+ 1;
1246 while (Size
>= sizeof (UINT32
)) {
1248 // Read as many double words as possible
1250 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1252 StartAddress
+= sizeof (UINT32
);
1253 Size
-= sizeof (UINT32
);
1254 Buffer
= (UINT32
*)Buffer
+ 1;
1257 if (Size
>= sizeof (UINT16
)) {
1259 // Read the last remaining word if exist
1261 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1262 StartAddress
+= sizeof (UINT16
);
1263 Size
-= sizeof (UINT16
);
1264 Buffer
= (UINT16
*)Buffer
+ 1;
1267 if (Size
>= sizeof (UINT8
)) {
1269 // Read the last remaining byte if exist
1271 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1278 Copies the data in a caller supplied buffer to a specified range of PCI
1279 configuration space.
1281 Writes the range of PCI configuration registers specified by StartAddress and
1282 Size from the buffer specified by Buffer. This function only allows the PCI
1283 configuration registers from a single PCI function to be written. Size is
1284 returned. When possible 32-bit PCI configuration write cycles are used to
1285 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1286 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1287 and the end of the range.
1289 If StartAddress > 0x0FFFFFFF, then ASSERT().
1290 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1291 If Size > 0 and Buffer is NULL, then ASSERT().
1293 @param StartAddress Starting address that encodes the PCI Bus, Device,
1294 Function and Register.
1295 @param Size Size in bytes of the transfer.
1296 @param Buffer Pointer to a buffer containing the data to write.
1303 PciExpressWriteBuffer (
1304 IN UINTN StartAddress
,
1311 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1312 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1318 ASSERT (Buffer
!= NULL
);
1321 // Save Size for return
1325 if ((StartAddress
& 1) != 0) {
1327 // Write a byte if StartAddress is byte aligned
1329 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1330 StartAddress
+= sizeof (UINT8
);
1331 Size
-= sizeof (UINT8
);
1332 Buffer
= (UINT8
*)Buffer
+ 1;
1335 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1337 // Write a word if StartAddress is word aligned
1339 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1340 StartAddress
+= sizeof (UINT16
);
1341 Size
-= sizeof (UINT16
);
1342 Buffer
= (UINT16
*)Buffer
+ 1;
1345 while (Size
>= sizeof (UINT32
)) {
1347 // Write as many double words as possible
1349 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1350 StartAddress
+= sizeof (UINT32
);
1351 Size
-= sizeof (UINT32
);
1352 Buffer
= (UINT32
*)Buffer
+ 1;
1355 if (Size
>= sizeof (UINT16
)) {
1357 // Write the last remaining word if exist
1359 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1360 StartAddress
+= sizeof (UINT16
);
1361 Size
-= sizeof (UINT16
);
1362 Buffer
= (UINT16
*)Buffer
+ 1;
1365 if (Size
>= sizeof (UINT8
)) {
1367 // Write the last remaining byte if exist
1369 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);