]>
git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BasePciExpressLib/PciLib.c
4 Functions in this library instance make use of MMIO functions in IoLib to
5 access memory mapped PCI configuration space.
7 All assertions for I/O operations are handled in MMIO functions in the IoLib
10 Copyright (c) 2006, Intel Corporation<BR>
11 All rights reserved. This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
24 Assert the validity of a PCI address. A valid PCI address should contain 1's
25 only in the low 28 bits.
27 @param A The address to validate.
30 #define ASSERT_INVALID_PCI_ADDRESS(A) \
31 ASSERT (((A) & ~0xfffffff) == 0)
36 GetPciExpressBaseAddress (
40 return (UINTN
)PcdGet64 (PcdPciExpressBaseAddress
);
44 Reads an 8-bit PCI configuration register.
46 Reads and returns the 8-bit PCI configuration register specified by Address.
47 This function must guarantee that all PCI read and write operations are
50 If Address > 0x0FFFFFFF, then ASSERT().
52 @param Address Address that encodes the PCI Bus, Device, Function and
55 @return The read value from the PCI configuration register.
64 ASSERT_INVALID_PCI_ADDRESS (Address
);
65 return MmioRead8 (GetPciExpressBaseAddress () + Address
);
69 Writes an 8-bit PCI configuration register.
71 Writes the 8-bit PCI configuration register specified by Address with the
72 value specified by Value. Value is returned. This function must guarantee
73 that all PCI read and write operations are serialized.
75 If Address > 0x0FFFFFFF, then ASSERT().
77 @param Address Address that encodes the PCI Bus, Device, Function and
79 @param Value The value to write.
81 @return The value written to the PCI configuration register.
91 ASSERT_INVALID_PCI_ADDRESS (Address
);
92 return MmioWrite8 (GetPciExpressBaseAddress () + Address
, Value
);
96 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
99 Reads the 8-bit PCI configuration register specified by Address, performs a
100 bitwise inclusive OR between the read result and the value specified by
101 OrData, and writes the result to the 8-bit PCI configuration register
102 specified by Address. The value written to the PCI configuration register is
103 returned. This function must guarantee that all PCI read and write operations
106 If Address > 0x0FFFFFFF, then ASSERT().
108 @param Address Address that encodes the PCI Bus, Device, Function and
110 @param OrData The value to OR with the PCI configuration register.
112 @return The value written back to the PCI configuration register.
122 ASSERT_INVALID_PCI_ADDRESS (Address
);
123 return MmioOr8 (GetPciExpressBaseAddress () + Address
, OrData
);
127 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
130 Reads the 8-bit PCI configuration register specified by Address, performs a
131 bitwise AND between the read result and the value specified by AndData, and
132 writes the result to the 8-bit PCI configuration register specified by
133 Address. The value written to the PCI configuration register is returned.
134 This function must guarantee that all PCI read and write operations are
137 If Address > 0x0FFFFFFF, then ASSERT().
139 @param Address Address that encodes the PCI Bus, Device, Function and
141 @param AndData The value to AND with the PCI configuration register.
143 @return The value written back to the PCI configuration register.
153 ASSERT_INVALID_PCI_ADDRESS (Address
);
154 return MmioAnd8 (GetPciExpressBaseAddress () + Address
, AndData
);
158 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
159 value, followed a bitwise inclusive OR with another 8-bit value.
161 Reads the 8-bit PCI configuration register specified by Address, performs a
162 bitwise AND between the read result and the value specified by AndData,
163 performs a bitwise inclusive OR between the result of the AND operation and
164 the value specified by OrData, and writes the result to the 8-bit PCI
165 configuration register specified by Address. The value written to the PCI
166 configuration register is returned. This function must guarantee that all PCI
167 read and write operations are serialized.
169 If Address > 0x0FFFFFFF, then ASSERT().
171 @param Address Address that encodes the PCI Bus, Device, Function and
173 @param AndData The value to AND with the PCI configuration register.
174 @param OrData The value to OR with the result of the AND operation.
176 @return The value written back to the PCI configuration register.
181 PciExpressAndThenOr8 (
187 ASSERT_INVALID_PCI_ADDRESS (Address
);
188 return MmioAndThenOr8 (
189 GetPciExpressBaseAddress () + Address
,
196 Reads a bit field of a PCI configuration register.
198 Reads the bit field in an 8-bit PCI configuration register. The bit field is
199 specified by the StartBit and the EndBit. The value of the bit field is
202 If Address > 0x0FFFFFFF, then ASSERT().
203 If StartBit is greater than 7, then ASSERT().
204 If EndBit is greater than 7, then ASSERT().
205 If EndBit is less than StartBit, then ASSERT().
207 @param Address PCI configuration register to read.
208 @param StartBit The ordinal of the least significant bit in the bit field.
210 @param EndBit The ordinal of the most significant bit in the bit field.
213 @return The value of the bit field read from the PCI configuration register.
218 PciExpressBitFieldRead8 (
224 ASSERT_INVALID_PCI_ADDRESS (Address
);
225 return MmioBitFieldRead8 (
226 GetPciExpressBaseAddress () + Address
,
233 Writes a bit field to a PCI configuration register.
235 Writes Value to the bit field of the PCI configuration register. The bit
236 field is specified by the StartBit and the EndBit. All other bits in the
237 destination PCI configuration register are preserved. The new value of the
238 8-bit register is returned.
240 If Address > 0x0FFFFFFF, then ASSERT().
241 If StartBit is greater than 7, then ASSERT().
242 If EndBit is greater than 7, then ASSERT().
243 If EndBit is less than StartBit, then ASSERT().
245 @param Address PCI configuration register to write.
246 @param StartBit The ordinal of the least significant bit in the bit field.
248 @param EndBit The ordinal of the most significant bit in the bit field.
250 @param Value New value of the bit field.
252 @return The value written back to the PCI configuration register.
257 PciExpressBitFieldWrite8 (
264 ASSERT_INVALID_PCI_ADDRESS (Address
);
265 return MmioBitFieldWrite8 (
266 GetPciExpressBaseAddress () + Address
,
274 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
275 writes the result back to the bit field in the 8-bit port.
277 Reads the 8-bit PCI configuration register specified by Address, performs a
278 bitwise inclusive OR between the read result and the value specified by
279 OrData, and writes the result to the 8-bit PCI configuration register
280 specified by Address. The value written to the PCI configuration register is
281 returned. This function must guarantee that all PCI read and write operations
282 are serialized. Extra left bits in OrData are stripped.
284 If Address > 0x0FFFFFFF, then ASSERT().
285 If StartBit is greater than 7, then ASSERT().
286 If EndBit is greater than 7, then ASSERT().
287 If EndBit is less than StartBit, then ASSERT().
289 @param Address PCI configuration register to write.
290 @param StartBit The ordinal of the least significant bit in the bit field.
292 @param EndBit The ordinal of the most significant bit in the bit field.
294 @param OrData The value to OR with the PCI configuration register.
296 @return The value written back to the PCI configuration register.
301 PciExpressBitFieldOr8 (
308 ASSERT_INVALID_PCI_ADDRESS (Address
);
309 return MmioBitFieldOr8 (
310 GetPciExpressBaseAddress () + Address
,
318 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
319 AND, and writes the result back to the bit field in the 8-bit register.
321 Reads the 8-bit PCI configuration register specified by Address, performs a
322 bitwise AND between the read result and the value specified by AndData, and
323 writes the result to the 8-bit PCI configuration register specified by
324 Address. The value written to the PCI configuration register is returned.
325 This function must guarantee that all PCI read and write operations are
326 serialized. Extra left bits in AndData are stripped.
328 If Address > 0x0FFFFFFF, then ASSERT().
329 If StartBit is greater than 7, then ASSERT().
330 If EndBit is greater than 7, then ASSERT().
331 If EndBit is less than StartBit, then ASSERT().
333 @param Address PCI configuration register to write.
334 @param StartBit The ordinal of the least significant bit in the bit field.
336 @param EndBit The ordinal of the most significant bit in the bit field.
338 @param AndData The value to AND with the PCI configuration register.
340 @return The value written back to the PCI configuration register.
345 PciExpressBitFieldAnd8 (
352 ASSERT_INVALID_PCI_ADDRESS (Address
);
353 return MmioBitFieldAnd8 (
354 GetPciExpressBaseAddress () + Address
,
362 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
363 bitwise inclusive OR, and writes the result back to the bit field in the
366 Reads the 8-bit PCI configuration register specified by Address, performs a
367 bitwise AND followed by a bitwise inclusive OR between the read result and
368 the value specified by AndData, and writes the result to the 8-bit PCI
369 configuration register specified by Address. The value written to the PCI
370 configuration register is returned. This function must guarantee that all PCI
371 read and write operations are serialized. Extra left bits in both AndData and
374 If Address > 0x0FFFFFFF, then ASSERT().
375 If StartBit is greater than 7, then ASSERT().
376 If EndBit is greater than 7, then ASSERT().
377 If EndBit is less than StartBit, then ASSERT().
379 @param Address PCI configuration register to write.
380 @param StartBit The ordinal of the least significant bit in the bit field.
382 @param EndBit The ordinal of the most significant bit in the bit field.
384 @param AndData The value to AND with the PCI configuration register.
385 @param OrData The value to OR with the result of the AND operation.
387 @return The value written back to the PCI configuration register.
392 PciExpressBitFieldAndThenOr8 (
400 ASSERT_INVALID_PCI_ADDRESS (Address
);
401 return MmioBitFieldAndThenOr8 (
402 GetPciExpressBaseAddress () + Address
,
411 Reads a 16-bit PCI configuration register.
413 Reads and returns the 16-bit PCI configuration register specified by Address.
414 This function must guarantee that all PCI read and write operations are
417 If Address > 0x0FFFFFFF, then ASSERT().
418 If Address is not aligned on a 16-bit boundary, then ASSERT().
420 @param Address Address that encodes the PCI Bus, Device, Function and
423 @return The read value from the PCI configuration register.
432 ASSERT_INVALID_PCI_ADDRESS (Address
);
433 return MmioRead16 (GetPciExpressBaseAddress () + Address
);
437 Writes a 16-bit PCI configuration register.
439 Writes the 16-bit PCI configuration register specified by Address with the
440 value specified by Value. Value is returned. This function must guarantee
441 that all PCI read and write operations are serialized.
443 If Address > 0x0FFFFFFF, then ASSERT().
444 If Address is not aligned on a 16-bit boundary, then ASSERT().
446 @param Address Address that encodes the PCI Bus, Device, Function and
448 @param Value The value to write.
450 @return The value written to the PCI configuration register.
460 ASSERT_INVALID_PCI_ADDRESS (Address
);
461 return MmioWrite16 (GetPciExpressBaseAddress () + Address
, Value
);
465 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
468 Reads the 16-bit PCI configuration register specified by Address, performs a
469 bitwise inclusive OR between the read result and the value specified by
470 OrData, and writes the result to the 16-bit PCI configuration register
471 specified by Address. The value written to the PCI configuration register is
472 returned. This function must guarantee that all PCI read and write operations
475 If Address > 0x0FFFFFFF, then ASSERT().
476 If Address is not aligned on a 16-bit boundary, then ASSERT().
478 @param Address Address that encodes the PCI Bus, Device, Function and
480 @param OrData The value to OR with the PCI configuration register.
482 @return The value written back to the PCI configuration register.
492 ASSERT_INVALID_PCI_ADDRESS (Address
);
493 return MmioOr16 (GetPciExpressBaseAddress () + Address
, OrData
);
497 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
500 Reads the 16-bit PCI configuration register specified by Address, performs a
501 bitwise AND between the read result and the value specified by AndData, and
502 writes the result to the 16-bit PCI configuration register specified by
503 Address. The value written to the PCI configuration register is returned.
504 This function must guarantee that all PCI read and write operations are
507 If Address > 0x0FFFFFFF, then ASSERT().
508 If Address is not aligned on a 16-bit boundary, then ASSERT().
510 @param Address Address that encodes the PCI Bus, Device, Function and
512 @param AndData The value to AND with the PCI configuration register.
514 @return The value written back to the PCI configuration register.
524 ASSERT_INVALID_PCI_ADDRESS (Address
);
525 return MmioAnd16 (GetPciExpressBaseAddress () + Address
, AndData
);
529 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
530 value, followed a bitwise inclusive OR with another 16-bit value.
532 Reads the 16-bit PCI configuration register specified by Address, performs a
533 bitwise AND between the read result and the value specified by AndData,
534 performs a bitwise inclusive OR between the result of the AND operation and
535 the value specified by OrData, and writes the result to the 16-bit PCI
536 configuration register specified by Address. The value written to the PCI
537 configuration register is returned. This function must guarantee that all PCI
538 read and write operations are serialized.
540 If Address > 0x0FFFFFFF, then ASSERT().
541 If Address is not aligned on a 16-bit boundary, then ASSERT().
543 @param Address Address that encodes the PCI Bus, Device, Function and
545 @param AndData The value to AND with the PCI configuration register.
546 @param OrData The value to OR with the result of the AND operation.
548 @return The value written back to the PCI configuration register.
553 PciExpressAndThenOr16 (
559 ASSERT_INVALID_PCI_ADDRESS (Address
);
560 return MmioAndThenOr16 (
561 GetPciExpressBaseAddress () + Address
,
568 Reads a bit field of a PCI configuration register.
570 Reads the bit field in a 16-bit PCI configuration register. The bit field is
571 specified by the StartBit and the EndBit. The value of the bit field is
574 If Address > 0x0FFFFFFF, then ASSERT().
575 If Address is not aligned on a 16-bit boundary, then ASSERT().
576 If StartBit is greater than 15, then ASSERT().
577 If EndBit is greater than 15, then ASSERT().
578 If EndBit is less than StartBit, then ASSERT().
580 @param Address PCI configuration register to read.
581 @param StartBit The ordinal of the least significant bit in the bit field.
583 @param EndBit The ordinal of the most significant bit in the bit field.
586 @return The value of the bit field read from the PCI configuration register.
591 PciExpressBitFieldRead16 (
597 ASSERT_INVALID_PCI_ADDRESS (Address
);
598 return MmioBitFieldRead16 (
599 GetPciExpressBaseAddress () + Address
,
606 Writes a bit field to a PCI configuration register.
608 Writes Value to the bit field of the PCI configuration register. The bit
609 field is specified by the StartBit and the EndBit. All other bits in the
610 destination PCI configuration register are preserved. The new value of the
611 16-bit register is returned.
613 If Address > 0x0FFFFFFF, then ASSERT().
614 If Address is not aligned on a 16-bit boundary, then ASSERT().
615 If StartBit is greater than 15, then ASSERT().
616 If EndBit is greater than 15, then ASSERT().
617 If EndBit is less than StartBit, then ASSERT().
619 @param Address PCI configuration register to write.
620 @param StartBit The ordinal of the least significant bit in the bit field.
622 @param EndBit The ordinal of the most significant bit in the bit field.
624 @param Value New value of the bit field.
626 @return The value written back to the PCI configuration register.
631 PciExpressBitFieldWrite16 (
638 ASSERT_INVALID_PCI_ADDRESS (Address
);
639 return MmioBitFieldWrite16 (
640 GetPciExpressBaseAddress () + Address
,
648 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
649 writes the result back to the bit field in the 16-bit port.
651 Reads the 16-bit PCI configuration register specified by Address, performs a
652 bitwise inclusive OR between the read result and the value specified by
653 OrData, and writes the result to the 16-bit PCI configuration register
654 specified by Address. The value written to the PCI configuration register is
655 returned. This function must guarantee that all PCI read and write operations
656 are serialized. Extra left bits in OrData are stripped.
658 If Address > 0x0FFFFFFF, then ASSERT().
659 If Address is not aligned on a 16-bit boundary, then ASSERT().
660 If StartBit is greater than 15, then ASSERT().
661 If EndBit is greater than 15, then ASSERT().
662 If EndBit is less than StartBit, then ASSERT().
664 @param Address PCI configuration register to write.
665 @param StartBit The ordinal of the least significant bit in the bit field.
667 @param EndBit The ordinal of the most significant bit in the bit field.
669 @param OrData The value to OR with the PCI configuration register.
671 @return The value written back to the PCI configuration register.
676 PciExpressBitFieldOr16 (
683 ASSERT_INVALID_PCI_ADDRESS (Address
);
684 return MmioBitFieldOr16 (
685 GetPciExpressBaseAddress () + Address
,
693 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
694 AND, and writes the result back to the bit field in the 16-bit register.
696 Reads the 16-bit PCI configuration register specified by Address, performs a
697 bitwise AND between the read result and the value specified by AndData, and
698 writes the result to the 16-bit PCI configuration register specified by
699 Address. The value written to the PCI configuration register is returned.
700 This function must guarantee that all PCI read and write operations are
701 serialized. Extra left bits in AndData are stripped.
703 If Address > 0x0FFFFFFF, then ASSERT().
704 If Address is not aligned on a 16-bit boundary, then ASSERT().
705 If StartBit is greater than 15, then ASSERT().
706 If EndBit is greater than 15, then ASSERT().
707 If EndBit is less than StartBit, then ASSERT().
709 @param Address PCI configuration register to write.
710 @param StartBit The ordinal of the least significant bit in the bit field.
712 @param EndBit The ordinal of the most significant bit in the bit field.
714 @param AndData The value to AND with the PCI configuration register.
716 @return The value written back to the PCI configuration register.
721 PciExpressBitFieldAnd16 (
728 ASSERT_INVALID_PCI_ADDRESS (Address
);
729 return MmioBitFieldAnd16 (
730 GetPciExpressBaseAddress () + Address
,
738 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
739 bitwise inclusive OR, and writes the result back to the bit field in the
742 Reads the 16-bit PCI configuration register specified by Address, performs a
743 bitwise AND followed by a bitwise inclusive OR between the read result and
744 the value specified by AndData, and writes the result to the 16-bit PCI
745 configuration register specified by Address. The value written to the PCI
746 configuration register is returned. This function must guarantee that all PCI
747 read and write operations are serialized. Extra left bits in both AndData and
750 If Address > 0x0FFFFFFF, then ASSERT().
751 If Address is not aligned on a 16-bit boundary, then ASSERT().
752 If StartBit is greater than 15, then ASSERT().
753 If EndBit is greater than 15, then ASSERT().
754 If EndBit is less than StartBit, then ASSERT().
756 @param Address PCI configuration register to write.
757 @param StartBit The ordinal of the least significant bit in the bit field.
759 @param EndBit The ordinal of the most significant bit in the bit field.
761 @param AndData The value to AND with the PCI configuration register.
762 @param OrData The value to OR with the result of the AND operation.
764 @return The value written back to the PCI configuration register.
769 PciExpressBitFieldAndThenOr16 (
777 ASSERT_INVALID_PCI_ADDRESS (Address
);
778 return MmioBitFieldAndThenOr16 (
779 GetPciExpressBaseAddress () + Address
,
788 Reads a 32-bit PCI configuration register.
790 Reads and returns the 32-bit PCI configuration register specified by Address.
791 This function must guarantee that all PCI read and write operations are
794 If Address > 0x0FFFFFFF, then ASSERT().
795 If Address is not aligned on a 32-bit boundary, then ASSERT().
797 @param Address Address that encodes the PCI Bus, Device, Function and
800 @return The read value from the PCI configuration register.
809 ASSERT_INVALID_PCI_ADDRESS (Address
);
810 return MmioRead32 (GetPciExpressBaseAddress () + Address
);
814 Writes a 32-bit PCI configuration register.
816 Writes the 32-bit PCI configuration register specified by Address with the
817 value specified by Value. Value is returned. This function must guarantee
818 that all PCI read and write operations are serialized.
820 If Address > 0x0FFFFFFF, then ASSERT().
821 If Address is not aligned on a 32-bit boundary, then ASSERT().
823 @param Address Address that encodes the PCI Bus, Device, Function and
825 @param Value The value to write.
827 @return The value written to the PCI configuration register.
837 ASSERT_INVALID_PCI_ADDRESS (Address
);
838 return MmioWrite32 (GetPciExpressBaseAddress () + Address
, Value
);
842 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
845 Reads the 32-bit PCI configuration register specified by Address, performs a
846 bitwise inclusive OR between the read result and the value specified by
847 OrData, and writes the result to the 32-bit PCI configuration register
848 specified by Address. The value written to the PCI configuration register is
849 returned. This function must guarantee that all PCI read and write operations
852 If Address > 0x0FFFFFFF, then ASSERT().
853 If Address is not aligned on a 32-bit boundary, then ASSERT().
855 @param Address Address that encodes the PCI Bus, Device, Function and
857 @param OrData The value to OR with the PCI configuration register.
859 @return The value written back to the PCI configuration register.
869 ASSERT_INVALID_PCI_ADDRESS (Address
);
870 return MmioOr32 (GetPciExpressBaseAddress () + Address
, OrData
);
874 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
877 Reads the 32-bit PCI configuration register specified by Address, performs a
878 bitwise AND between the read result and the value specified by AndData, and
879 writes the result to the 32-bit PCI configuration register specified by
880 Address. The value written to the PCI configuration register is returned.
881 This function must guarantee that all PCI read and write operations are
884 If Address > 0x0FFFFFFF, then ASSERT().
885 If Address is not aligned on a 32-bit boundary, then ASSERT().
887 @param Address Address that encodes the PCI Bus, Device, Function and
889 @param AndData The value to AND with the PCI configuration register.
891 @return The value written back to the PCI configuration register.
901 ASSERT_INVALID_PCI_ADDRESS (Address
);
902 return MmioAnd32 (GetPciExpressBaseAddress () + Address
, AndData
);
906 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
907 value, followed a bitwise inclusive OR with another 32-bit value.
909 Reads the 32-bit PCI configuration register specified by Address, performs a
910 bitwise AND between the read result and the value specified by AndData,
911 performs a bitwise inclusive OR between the result of the AND operation and
912 the value specified by OrData, and writes the result to the 32-bit PCI
913 configuration register specified by Address. The value written to the PCI
914 configuration register is returned. This function must guarantee that all PCI
915 read and write operations are serialized.
917 If Address > 0x0FFFFFFF, then ASSERT().
918 If Address is not aligned on a 32-bit boundary, then ASSERT().
920 @param Address Address that encodes the PCI Bus, Device, Function and
922 @param AndData The value to AND with the PCI configuration register.
923 @param OrData The value to OR with the result of the AND operation.
925 @return The value written back to the PCI configuration register.
930 PciExpressAndThenOr32 (
936 ASSERT_INVALID_PCI_ADDRESS (Address
);
937 return MmioAndThenOr32 (
938 GetPciExpressBaseAddress () + Address
,
945 Reads a bit field of a PCI configuration register.
947 Reads the bit field in a 32-bit PCI configuration register. The bit field is
948 specified by the StartBit and the EndBit. The value of the bit field is
951 If Address > 0x0FFFFFFF, then ASSERT().
952 If Address is not aligned on a 32-bit boundary, then ASSERT().
953 If StartBit is greater than 31, then ASSERT().
954 If EndBit is greater than 31, then ASSERT().
955 If EndBit is less than StartBit, then ASSERT().
957 @param Address PCI configuration register to read.
958 @param StartBit The ordinal of the least significant bit in the bit field.
960 @param EndBit The ordinal of the most significant bit in the bit field.
963 @return The value of the bit field read from the PCI configuration register.
968 PciExpressBitFieldRead32 (
974 ASSERT_INVALID_PCI_ADDRESS (Address
);
975 return MmioBitFieldRead32 (
976 GetPciExpressBaseAddress () + Address
,
983 Writes a bit field to a PCI configuration register.
985 Writes Value to the bit field of the PCI configuration register. The bit
986 field is specified by the StartBit and the EndBit. All other bits in the
987 destination PCI configuration register are preserved. The new value of the
988 32-bit register is returned.
990 If Address > 0x0FFFFFFF, then ASSERT().
991 If Address is not aligned on a 32-bit boundary, then ASSERT().
992 If StartBit is greater than 31, then ASSERT().
993 If EndBit is greater than 31, then ASSERT().
994 If EndBit is less than StartBit, then ASSERT().
996 @param Address PCI configuration register to write.
997 @param StartBit The ordinal of the least significant bit in the bit field.
999 @param EndBit The ordinal of the most significant bit in the bit field.
1001 @param Value New value of the bit field.
1003 @return The value written back to the PCI configuration register.
1008 PciExpressBitFieldWrite32 (
1015 ASSERT_INVALID_PCI_ADDRESS (Address
);
1016 return MmioBitFieldWrite32 (
1017 GetPciExpressBaseAddress () + Address
,
1025 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1026 writes the result back to the bit field in the 32-bit port.
1028 Reads the 32-bit PCI configuration register specified by Address, performs a
1029 bitwise inclusive OR between the read result and the value specified by
1030 OrData, and writes the result to the 32-bit PCI configuration register
1031 specified by Address. The value written to the PCI configuration register is
1032 returned. This function must guarantee that all PCI read and write operations
1033 are serialized. Extra left bits in OrData are stripped.
1035 If Address > 0x0FFFFFFF, then ASSERT().
1036 If Address is not aligned on a 32-bit boundary, then ASSERT().
1037 If StartBit is greater than 31, then ASSERT().
1038 If EndBit is greater than 31, then ASSERT().
1039 If EndBit is less than StartBit, then ASSERT().
1041 @param Address PCI configuration register to write.
1042 @param StartBit The ordinal of the least significant bit in the bit field.
1044 @param EndBit The ordinal of the most significant bit in the bit field.
1046 @param OrData The value to OR with the PCI configuration register.
1048 @return The value written back to the PCI configuration register.
1053 PciExpressBitFieldOr32 (
1060 ASSERT_INVALID_PCI_ADDRESS (Address
);
1061 return MmioBitFieldOr32 (
1062 GetPciExpressBaseAddress () + Address
,
1070 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1071 AND, and writes the result back to the bit field in the 32-bit register.
1073 Reads the 32-bit PCI configuration register specified by Address, performs a
1074 bitwise AND between the read result and the value specified by AndData, and
1075 writes the result to the 32-bit PCI configuration register specified by
1076 Address. The value written to the PCI configuration register is returned.
1077 This function must guarantee that all PCI read and write operations are
1078 serialized. Extra left bits in AndData are stripped.
1080 If Address > 0x0FFFFFFF, then ASSERT().
1081 If Address is not aligned on a 32-bit boundary, then ASSERT().
1082 If StartBit is greater than 31, then ASSERT().
1083 If EndBit is greater than 31, then ASSERT().
1084 If EndBit is less than StartBit, then ASSERT().
1086 @param Address PCI configuration register to write.
1087 @param StartBit The ordinal of the least significant bit in the bit field.
1089 @param EndBit The ordinal of the most significant bit in the bit field.
1091 @param AndData The value to AND with the PCI configuration register.
1093 @return The value written back to the PCI configuration register.
1098 PciExpressBitFieldAnd32 (
1105 ASSERT_INVALID_PCI_ADDRESS (Address
);
1106 return MmioBitFieldAnd32 (
1107 GetPciExpressBaseAddress () + Address
,
1115 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1116 bitwise inclusive OR, and writes the result back to the bit field in the
1119 Reads the 32-bit PCI configuration register specified by Address, performs a
1120 bitwise AND followed by a bitwise inclusive OR between the read result and
1121 the value specified by AndData, and writes the result to the 32-bit PCI
1122 configuration register specified by Address. The value written to the PCI
1123 configuration register is returned. This function must guarantee that all PCI
1124 read and write operations are serialized. Extra left bits in both AndData and
1125 OrData are stripped.
1127 If Address > 0x0FFFFFFF, then ASSERT().
1128 If Address is not aligned on a 32-bit boundary, then ASSERT().
1129 If StartBit is greater than 31, then ASSERT().
1130 If EndBit is greater than 31, then ASSERT().
1131 If EndBit is less than StartBit, then ASSERT().
1133 @param Address PCI configuration register to write.
1134 @param StartBit The ordinal of the least significant bit in the bit field.
1136 @param EndBit The ordinal of the most significant bit in the bit field.
1138 @param AndData The value to AND with the PCI configuration register.
1139 @param OrData The value to OR with the result of the AND operation.
1141 @return The value written back to the PCI configuration register.
1146 PciExpressBitFieldAndThenOr32 (
1154 ASSERT_INVALID_PCI_ADDRESS (Address
);
1155 return MmioBitFieldAndThenOr32 (
1156 GetPciExpressBaseAddress () + Address
,
1165 Reads a range of PCI configuration registers into a caller supplied buffer.
1167 Reads the range of PCI configuration registers specified by StartAddress and
1168 Size into the buffer specified by Buffer. This function only allows the PCI
1169 configuration registers from a single PCI function to be read. Size is
1170 returned. When possible 32-bit PCI configuration read cycles are used to read
1171 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1172 and 16-bit PCI configuration read cycles may be used at the beginning and the
1175 If StartAddress > 0x0FFFFFFF, then ASSERT().
1176 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1177 If Size > 0 and Buffer is NULL, then ASSERT().
1179 @param StartAddress Starting address that encodes the PCI Bus, Device,
1180 Function and Register.
1181 @param Size Size in bytes of the transfer.
1182 @param Buffer Pointer to a buffer receiving the data read.
1189 PciExpressReadBuffer (
1190 IN UINTN StartAddress
,
1197 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1198 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1204 ASSERT (Buffer
!= NULL
);
1207 // Save Size for return
1211 if ((StartAddress
& 1) != 0) {
1213 // Read a byte if StartAddress is byte aligned
1215 *(UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1216 StartAddress
+= sizeof (UINT8
);
1217 Size
-= sizeof (UINT8
);
1218 Buffer
= (UINT8
*)Buffer
+ 1;
1221 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1223 // Read a word if StartAddress is word aligned
1225 *(UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1226 StartAddress
+= sizeof (UINT16
);
1227 Size
-= sizeof (UINT16
);
1228 Buffer
= (UINT16
*)Buffer
+ 1;
1231 while (Size
>= sizeof (UINT32
)) {
1233 // Read as many double words as possible
1235 *(UINT32
*)Buffer
= PciExpressRead32 (StartAddress
);
1236 StartAddress
+= sizeof (UINT32
);
1237 Size
-= sizeof (UINT32
);
1238 Buffer
= (UINT32
*)Buffer
+ 1;
1241 if (Size
>= sizeof (UINT16
)) {
1243 // Read the last remaining word if exist
1245 *(UINT16
*)Buffer
= PciExpressRead16 (StartAddress
);
1246 StartAddress
+= sizeof (UINT16
);
1247 Size
-= sizeof (UINT16
);
1248 Buffer
= (UINT16
*)Buffer
+ 1;
1251 if (Size
>= sizeof (UINT8
)) {
1253 // Read the last remaining byte if exist
1255 *(UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1262 Copies the data in a caller supplied buffer to a specified range of PCI
1263 configuration space.
1265 Writes the range of PCI configuration registers specified by StartAddress and
1266 Size from the buffer specified by Buffer. This function only allows the PCI
1267 configuration registers from a single PCI function to be written. Size is
1268 returned. When possible 32-bit PCI configuration write cycles are used to
1269 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1270 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1271 and the end of the range.
1273 If StartAddress > 0x0FFFFFFF, then ASSERT().
1274 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1275 If Size > 0 and Buffer is NULL, then ASSERT().
1277 @param StartAddress Starting address that encodes the PCI Bus, Device,
1278 Function and Register.
1279 @param Size Size in bytes of the transfer.
1280 @param Buffer Pointer to a buffer containing the data to write.
1287 PciExpressWriteBuffer (
1288 IN UINTN StartAddress
,
1295 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1296 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1302 ASSERT (Buffer
!= NULL
);
1305 // Save Size for return
1309 if ((StartAddress
& 1) != 0) {
1311 // Write a byte if StartAddress is byte aligned
1313 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1314 StartAddress
+= sizeof (UINT8
);
1315 Size
-= sizeof (UINT8
);
1316 Buffer
= (UINT8
*)Buffer
+ 1;
1319 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1321 // Write a word if StartAddress is word aligned
1323 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1324 StartAddress
+= sizeof (UINT16
);
1325 Size
-= sizeof (UINT16
);
1326 Buffer
= (UINT16
*)Buffer
+ 1;
1329 while (Size
>= sizeof (UINT32
)) {
1331 // Write as many double words as possible
1333 PciExpressWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1334 StartAddress
+= sizeof (UINT32
);
1335 Size
-= sizeof (UINT32
);
1336 Buffer
= (UINT32
*)Buffer
+ 1;
1339 if (Size
>= sizeof (UINT16
)) {
1341 // Write the last remaining word if exist
1343 PciExpressWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1344 StartAddress
+= sizeof (UINT16
);
1345 Size
-= sizeof (UINT16
);
1346 Buffer
= (UINT16
*)Buffer
+ 1;
1349 if (Size
>= sizeof (UINT8
)) {
1351 // Write the last remaining byte if exist
1353 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);