2 PCI Library using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Protocol/PciRootBridgeIo.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/UefiBootServicesTableLib.h>
23 #include <Library/DebugLib.h>
26 Assert the validity of a PCI address. A valid PCI address should contain 1's
27 only in the low 28 bits.
29 @param A The address to validate.
30 @param M Additional bits to assert to be zero.
33 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
34 ASSERT (((A) & (~0xfffffff | (M))) == 0)
37 Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
39 @param A The address that encodes the PCI Bus, Device, Function and
43 #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
44 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
47 // Global varible to cache pointer to PCI Root Bridge I/O protocol.
49 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
= NULL
;
52 The constructor function caches the pointer to PCI Root Bridge I/O protocol.
54 The constructor function locates PCI Root Bridge I/O protocol from protocol database.
55 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
57 @param ImageHandle The firmware allocated handle for the EFI image.
58 @param SystemTable A pointer to the EFI System Table.
60 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
66 IN EFI_HANDLE ImageHandle
,
67 IN EFI_SYSTEM_TABLE
*SystemTable
72 Status
= gBS
->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid
, NULL
, (VOID
**) &mPciRootBridgeIo
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (mPciRootBridgeIo
!= NULL
);
80 Internal worker function to read a PCI configuration register.
82 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
83 It reads and returns the PCI configuration register specified by Address,
84 the width of data is specified by Width.
86 @param Address The address that encodes the PCI Bus, Device, Function and
88 @param Width The width of data to read
90 @return The value read from the PCI configuration register.
94 DxePciLibPciRootBridgeIoReadWorker (
96 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
101 mPciRootBridgeIo
->Pci
.Read (
104 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
113 Internal worker function to writes a PCI configuration register.
115 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
116 It writes the PCI configuration register specified by Address with the
117 value specified by Data. The width of data is specified by Width.
120 @param Address The address that encodes the PCI Bus, Device, Function and
122 @param Width The width of data to write
123 @param Data The value to write.
125 @return The value written to the PCI configuration register.
129 DxePciLibPciRootBridgeIoWriteWorker (
131 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
135 mPciRootBridgeIo
->Pci
.Write (
138 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
146 Registers a PCI device so PCI configuration registers may be accessed after
147 SetVirtualAddressMap().
149 Registers the PCI device specified by Address so all the PCI configuration registers
150 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
152 If Address > 0x0FFFFFFF, then ASSERT().
154 @param Address The address that encodes the PCI Bus, Device, Function and
157 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
158 @retval RETURN_UNSUPPORTED An attempt was made to call this function
159 after ExitBootServices().
160 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
161 at runtime could not be mapped.
162 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
163 complete the registration.
168 PciRegisterForRuntimeAccess (
172 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
173 return RETURN_UNSUPPORTED
;
177 Reads an 8-bit PCI configuration register.
179 Reads and returns the 8-bit PCI configuration register specified by Address.
180 This function must guarantee that all PCI read and write operations are
183 If Address > 0x0FFFFFFF, then ASSERT().
185 @param Address The address that encodes the PCI Bus, Device, Function and
188 @return The read value from the PCI configuration register.
197 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
199 return (UINT8
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
203 Writes an 8-bit PCI configuration register.
205 Writes the 8-bit PCI configuration register specified by Address with the
206 value specified by Value. Value is returned. This function must guarantee
207 that all PCI read and write operations are serialized.
209 If Address > 0x0FFFFFFF, then ASSERT().
211 @param Address The address that encodes the PCI Bus, Device, Function and
213 @param Value The value to write.
215 @return The value written to the PCI configuration register.
225 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
227 return (UINT8
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Value
);
231 Performs a bitwise OR of an 8-bit PCI configuration register with
234 Reads the 8-bit PCI configuration register specified by Address, performs a
235 bitwise OR between the read result and the value specified by
236 OrData, and writes the result to the 8-bit PCI configuration register
237 specified by Address. The value written to the PCI configuration register is
238 returned. This function must guarantee that all PCI read and write operations
241 If Address > 0x0FFFFFFF, then ASSERT().
243 @param Address The address that encodes the PCI Bus, Device, Function and
245 @param OrData The value to OR with the PCI configuration register.
247 @return The value written back to the PCI configuration register.
257 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
261 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
264 Reads the 8-bit PCI configuration register specified by Address, performs a
265 bitwise AND between the read result and the value specified by AndData, and
266 writes the result to the 8-bit PCI configuration register specified by
267 Address. The value written to the PCI configuration register is returned.
268 This function must guarantee that all PCI read and write operations are
271 If Address > 0x0FFFFFFF, then ASSERT().
273 @param Address The address that encodes the PCI Bus, Device, Function and
275 @param AndData The value to AND with the PCI configuration register.
277 @return The value written back to the PCI configuration register.
287 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
291 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
292 value, followed a bitwise OR with another 8-bit value.
294 Reads the 8-bit PCI configuration register specified by Address, performs a
295 bitwise AND between the read result and the value specified by AndData,
296 performs a bitwise OR between the result of the AND operation and
297 the value specified by OrData, and writes the result to the 8-bit PCI
298 configuration register specified by Address. The value written to the PCI
299 configuration register is returned. This function must guarantee that all PCI
300 read and write operations are serialized.
302 If Address > 0x0FFFFFFF, then ASSERT().
304 @param Address The address that encodes the PCI Bus, Device, Function and
306 @param AndData The value to AND with the PCI configuration register.
307 @param OrData The value to OR with the result of the AND operation.
309 @return The value written back to the PCI configuration register.
320 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
324 Reads a bit field of a PCI configuration register.
326 Reads the bit field in an 8-bit PCI configuration register. The bit field is
327 specified by the StartBit and the EndBit. The value of the bit field is
330 If Address > 0x0FFFFFFF, then ASSERT().
331 If StartBit is greater than 7, then ASSERT().
332 If EndBit is greater than 7, then ASSERT().
333 If EndBit is less than StartBit, then ASSERT().
335 @param Address The PCI configuration register to read.
336 @param StartBit The ordinal of the least significant bit in the bit field.
338 @param EndBit The ordinal of the most significant bit in the bit field.
341 @return The value of the bit field read from the PCI configuration register.
352 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
356 Writes a bit field to a PCI configuration register.
358 Writes Value to the bit field of the PCI configuration register. The bit
359 field is specified by the StartBit and the EndBit. All other bits in the
360 destination PCI configuration register are preserved. The new value of the
361 8-bit register is returned.
363 If Address > 0x0FFFFFFF, then ASSERT().
364 If StartBit is greater than 7, then ASSERT().
365 If EndBit is greater than 7, then ASSERT().
366 If EndBit is less than StartBit, then ASSERT().
367 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
369 @param Address The PCI configuration register to write.
370 @param StartBit The ordinal of the least significant bit in the bit field.
372 @param EndBit The ordinal of the most significant bit in the bit field.
374 @param Value The new value of the bit field.
376 @return The value written back to the PCI configuration register.
390 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
395 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
396 writes the result back to the bit field in the 8-bit port.
398 Reads the 8-bit PCI configuration register specified by Address, performs a
399 bitwise OR between the read result and the value specified by
400 OrData, and writes the result to the 8-bit PCI configuration register
401 specified by Address. The value written to the PCI configuration register is
402 returned. This function must guarantee that all PCI read and write operations
403 are serialized. Extra left bits in OrData are stripped.
405 If Address > 0x0FFFFFFF, then ASSERT().
406 If StartBit is greater than 7, then ASSERT().
407 If EndBit is greater than 7, then ASSERT().
408 If EndBit is less than StartBit, then ASSERT().
409 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
411 @param Address The PCI configuration register to write.
412 @param StartBit The ordinal of the least significant bit in the bit field.
414 @param EndBit The ordinal of the most significant bit in the bit field.
416 @param OrData The value to OR with the PCI configuration register.
418 @return The value written back to the PCI configuration register.
432 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
437 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
438 AND, and writes the result back to the bit field in the 8-bit register.
440 Reads the 8-bit PCI configuration register specified by Address, performs a
441 bitwise AND between the read result and the value specified by AndData, and
442 writes the result to the 8-bit PCI configuration register specified by
443 Address. The value written to the PCI configuration register is returned.
444 This function must guarantee that all PCI read and write operations are
445 serialized. Extra left bits in AndData are stripped.
447 If Address > 0x0FFFFFFF, then ASSERT().
448 If StartBit is greater than 7, then ASSERT().
449 If EndBit is greater than 7, then ASSERT().
450 If EndBit is less than StartBit, then ASSERT().
451 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
453 @param Address The PCI configuration register to write.
454 @param StartBit The ordinal of the least significant bit in the bit field.
456 @param EndBit The ordinal of the most significant bit in the bit field.
458 @param AndData The value to AND with the PCI configuration register.
460 @return The value written back to the PCI configuration register.
474 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
479 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
480 bitwise OR, and writes the result back to the bit field in the
483 Reads the 8-bit PCI configuration register specified by Address, performs a
484 bitwise AND followed by a bitwise OR between the read result and
485 the value specified by AndData, and writes the result to the 8-bit PCI
486 configuration register specified by Address. The value written to the PCI
487 configuration register is returned. This function must guarantee that all PCI
488 read and write operations are serialized. Extra left bits in both AndData and
491 If Address > 0x0FFFFFFF, then ASSERT().
492 If StartBit is greater than 7, then ASSERT().
493 If EndBit is greater than 7, then ASSERT().
494 If EndBit is less than StartBit, then ASSERT().
495 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
496 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
498 @param Address The PCI configuration register to write.
499 @param StartBit The ordinal of the least significant bit in the bit field.
501 @param EndBit The ordinal of the most significant bit in the bit field.
503 @param AndData The value to AND with the PCI configuration register.
504 @param OrData The value to OR with the result of the AND operation.
506 @return The value written back to the PCI configuration register.
511 PciBitFieldAndThenOr8 (
521 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
526 Reads a 16-bit PCI configuration register.
528 Reads and returns the 16-bit PCI configuration register specified by Address.
529 This function must guarantee that all PCI read and write operations are
532 If Address > 0x0FFFFFFF, then ASSERT().
533 If Address is not aligned on a 16-bit boundary, then ASSERT().
535 @param Address The address that encodes the PCI Bus, Device, Function and
538 @return The read value from the PCI configuration register.
547 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
549 return (UINT16
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
553 Writes a 16-bit PCI configuration register.
555 Writes the 16-bit PCI configuration register specified by Address with the
556 value specified by Value. Value is returned. This function must guarantee
557 that all PCI read and write operations are serialized.
559 If Address > 0x0FFFFFFF, then ASSERT().
560 If Address is not aligned on a 16-bit boundary, then ASSERT().
562 @param Address The address that encodes the PCI Bus, Device, Function and
564 @param Value The value to write.
566 @return The value written to the PCI configuration register.
576 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
578 return (UINT16
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Value
);
582 Performs a bitwise OR of a 16-bit PCI configuration register with
585 Reads the 16-bit PCI configuration register specified by Address, performs a
586 bitwise OR between the read result and the value specified by
587 OrData, and writes the result to the 16-bit PCI configuration register
588 specified by Address. The value written to the PCI configuration register is
589 returned. This function must guarantee that all PCI read and write operations
592 If Address > 0x0FFFFFFF, then ASSERT().
593 If Address is not aligned on a 16-bit boundary, then ASSERT().
595 @param Address The address that encodes the PCI Bus, Device, Function and
597 @param OrData The value to OR with the PCI configuration register.
599 @return The value written back to the PCI configuration register.
609 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
613 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
616 Reads the 16-bit PCI configuration register specified by Address, performs a
617 bitwise AND between the read result and the value specified by AndData, and
618 writes the result to the 16-bit PCI configuration register specified by
619 Address. The value written to the PCI configuration register is returned.
620 This function must guarantee that all PCI read and write operations are
623 If Address > 0x0FFFFFFF, then ASSERT().
624 If Address is not aligned on a 16-bit boundary, then ASSERT().
626 @param Address The address that encodes the PCI Bus, Device, Function and
628 @param AndData The value to AND with the PCI configuration register.
630 @return The value written back to the PCI configuration register.
640 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
644 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
645 value, followed a bitwise OR with another 16-bit value.
647 Reads the 16-bit PCI configuration register specified by Address, performs a
648 bitwise AND between the read result and the value specified by AndData,
649 performs a bitwise OR between the result of the AND operation and
650 the value specified by OrData, and writes the result to the 16-bit PCI
651 configuration register specified by Address. The value written to the PCI
652 configuration register is returned. This function must guarantee that all PCI
653 read and write operations are serialized.
655 If Address > 0x0FFFFFFF, then ASSERT().
656 If Address is not aligned on a 16-bit boundary, then ASSERT().
658 @param Address The address that encodes the PCI Bus, Device, Function and
660 @param AndData The value to AND with the PCI configuration register.
661 @param OrData The value to OR with the result of the AND operation.
663 @return The value written back to the PCI configuration register.
674 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
678 Reads a bit field of a PCI configuration register.
680 Reads the bit field in a 16-bit PCI configuration register. The bit field is
681 specified by the StartBit and the EndBit. The value of the bit field is
684 If Address > 0x0FFFFFFF, then ASSERT().
685 If Address is not aligned on a 16-bit boundary, then ASSERT().
686 If StartBit is greater than 15, then ASSERT().
687 If EndBit is greater than 15, then ASSERT().
688 If EndBit is less than StartBit, then ASSERT().
690 @param Address The PCI configuration register to read.
691 @param StartBit The ordinal of the least significant bit in the bit field.
693 @param EndBit The ordinal of the most significant bit in the bit field.
696 @return The value of the bit field read from the PCI configuration register.
707 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
711 Writes a bit field to a PCI configuration register.
713 Writes Value to the bit field of the PCI configuration register. The bit
714 field is specified by the StartBit and the EndBit. All other bits in the
715 destination PCI configuration register are preserved. The new value of the
716 16-bit register is returned.
718 If Address > 0x0FFFFFFF, then ASSERT().
719 If Address is not aligned on a 16-bit boundary, then ASSERT().
720 If StartBit is greater than 15, then ASSERT().
721 If EndBit is greater than 15, then ASSERT().
722 If EndBit is less than StartBit, then ASSERT().
723 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
725 @param Address The PCI configuration register to write.
726 @param StartBit The ordinal of the least significant bit in the bit field.
728 @param EndBit The ordinal of the most significant bit in the bit field.
730 @param Value The new value of the bit field.
732 @return The value written back to the PCI configuration register.
746 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
751 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
752 writes the result back to the bit field in the 16-bit port.
754 Reads the 16-bit PCI configuration register specified by Address, performs a
755 bitwise OR between the read result and the value specified by
756 OrData, and writes the result to the 16-bit PCI configuration register
757 specified by Address. The value written to the PCI configuration register is
758 returned. This function must guarantee that all PCI read and write operations
759 are serialized. Extra left bits in OrData are stripped.
761 If Address > 0x0FFFFFFF, then ASSERT().
762 If Address is not aligned on a 16-bit boundary, then ASSERT().
763 If StartBit is greater than 15, then ASSERT().
764 If EndBit is greater than 15, then ASSERT().
765 If EndBit is less than StartBit, then ASSERT().
766 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
768 @param Address The PCI configuration register to write.
769 @param StartBit The ordinal of the least significant bit in the bit field.
771 @param EndBit The ordinal of the most significant bit in the bit field.
773 @param OrData The value to OR with the PCI configuration register.
775 @return The value written back to the PCI configuration register.
789 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
794 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
795 AND, and writes the result back to the bit field in the 16-bit register.
797 Reads the 16-bit PCI configuration register specified by Address, performs a
798 bitwise AND between the read result and the value specified by AndData, and
799 writes the result to the 16-bit PCI configuration register specified by
800 Address. The value written to the PCI configuration register is returned.
801 This function must guarantee that all PCI read and write operations are
802 serialized. Extra left bits in AndData are stripped.
804 If Address > 0x0FFFFFFF, then ASSERT().
805 If Address is not aligned on a 16-bit boundary, then ASSERT().
806 If StartBit is greater than 15, then ASSERT().
807 If EndBit is greater than 15, then ASSERT().
808 If EndBit is less than StartBit, then ASSERT().
809 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
811 @param Address The PCI configuration register to write.
812 @param StartBit The ordinal of the least significant bit in the bit field.
814 @param EndBit The ordinal of the most significant bit in the bit field.
816 @param AndData The value to AND with the PCI configuration register.
818 @return The value written back to the PCI configuration register.
832 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
837 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
838 bitwise OR, and writes the result back to the bit field in the
841 Reads the 16-bit PCI configuration register specified by Address, performs a
842 bitwise AND followed by a bitwise OR between the read result and
843 the value specified by AndData, and writes the result to the 16-bit PCI
844 configuration register specified by Address. The value written to the PCI
845 configuration register is returned. This function must guarantee that all PCI
846 read and write operations are serialized. Extra left bits in both AndData and
849 If Address > 0x0FFFFFFF, then ASSERT().
850 If Address is not aligned on a 16-bit boundary, then ASSERT().
851 If StartBit is greater than 15, then ASSERT().
852 If EndBit is greater than 15, then ASSERT().
853 If EndBit is less than StartBit, then ASSERT().
854 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
855 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
857 @param Address The PCI configuration register to write.
858 @param StartBit The ordinal of the least significant bit in the bit field.
860 @param EndBit The ordinal of the most significant bit in the bit field.
862 @param AndData The value to AND with the PCI configuration register.
863 @param OrData The value to OR with the result of the AND operation.
865 @return The value written back to the PCI configuration register.
870 PciBitFieldAndThenOr16 (
880 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
885 Reads a 32-bit PCI configuration register.
887 Reads and returns the 32-bit PCI configuration register specified by Address.
888 This function must guarantee that all PCI read and write operations are
891 If Address > 0x0FFFFFFF, then ASSERT().
892 If Address is not aligned on a 32-bit boundary, then ASSERT().
894 @param Address The address that encodes the PCI Bus, Device, Function and
897 @return The read value from the PCI configuration register.
906 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
908 return DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
912 Writes a 32-bit PCI configuration register.
914 Writes the 32-bit PCI configuration register specified by Address with the
915 value specified by Value. Value is returned. This function must guarantee
916 that all PCI read and write operations are serialized.
918 If Address > 0x0FFFFFFF, then ASSERT().
919 If Address is not aligned on a 32-bit boundary, then ASSERT().
921 @param Address The address that encodes the PCI Bus, Device, Function and
923 @param Value The value to write.
925 @return The value written to the PCI configuration register.
935 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
937 return DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Value
);
941 Performs a bitwise OR of a 32-bit PCI configuration register with
944 Reads the 32-bit PCI configuration register specified by Address, performs a
945 bitwise OR between the read result and the value specified by
946 OrData, and writes the result to the 32-bit PCI configuration register
947 specified by Address. The value written to the PCI configuration register is
948 returned. This function must guarantee that all PCI read and write operations
951 If Address > 0x0FFFFFFF, then ASSERT().
952 If Address is not aligned on a 32-bit boundary, then ASSERT().
954 @param Address The address that encodes the PCI Bus, Device, Function and
956 @param OrData The value to OR with the PCI configuration register.
958 @return The value written back to the PCI configuration register.
968 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
972 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
975 Reads the 32-bit PCI configuration register specified by Address, performs a
976 bitwise AND between the read result and the value specified by AndData, and
977 writes the result to the 32-bit PCI configuration register specified by
978 Address. The value written to the PCI configuration register is returned.
979 This function must guarantee that all PCI read and write operations are
982 If Address > 0x0FFFFFFF, then ASSERT().
983 If Address is not aligned on a 32-bit boundary, then ASSERT().
985 @param Address The address that encodes the PCI Bus, Device, Function and
987 @param AndData The value to AND with the PCI configuration register.
989 @return The value written back to the PCI configuration register.
999 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
1003 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
1004 value, followed a bitwise OR with another 32-bit value.
1006 Reads the 32-bit PCI configuration register specified by Address, performs a
1007 bitwise AND between the read result and the value specified by AndData,
1008 performs a bitwise OR between the result of the AND operation and
1009 the value specified by OrData, and writes the result to the 32-bit PCI
1010 configuration register specified by Address. The value written to the PCI
1011 configuration register is returned. This function must guarantee that all PCI
1012 read and write operations are serialized.
1014 If Address > 0x0FFFFFFF, then ASSERT().
1015 If Address is not aligned on a 32-bit boundary, then ASSERT().
1017 @param Address The address that encodes the PCI Bus, Device, Function and
1019 @param AndData The value to AND with the PCI configuration register.
1020 @param OrData The value to OR with the result of the AND operation.
1022 @return The value written back to the PCI configuration register.
1033 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1037 Reads a bit field of a PCI configuration register.
1039 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1040 specified by the StartBit and the EndBit. The value of the bit field is
1043 If Address > 0x0FFFFFFF, then ASSERT().
1044 If Address is not aligned on a 32-bit boundary, then ASSERT().
1045 If StartBit is greater than 31, then ASSERT().
1046 If EndBit is greater than 31, then ASSERT().
1047 If EndBit is less than StartBit, then ASSERT().
1049 @param Address The PCI configuration register to read.
1050 @param StartBit The ordinal of the least significant bit in the bit field.
1052 @param EndBit The ordinal of the most significant bit in the bit field.
1055 @return The value of the bit field read from the PCI configuration register.
1066 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1070 Writes a bit field to a PCI configuration register.
1072 Writes Value to the bit field of the PCI configuration register. The bit
1073 field is specified by the StartBit and the EndBit. All other bits in the
1074 destination PCI configuration register are preserved. The new value of the
1075 32-bit register is returned.
1077 If Address > 0x0FFFFFFF, then ASSERT().
1078 If Address is not aligned on a 32-bit boundary, then ASSERT().
1079 If StartBit is greater than 31, then ASSERT().
1080 If EndBit is greater than 31, then ASSERT().
1081 If EndBit is less than StartBit, then ASSERT().
1082 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1084 @param Address The PCI configuration register to write.
1085 @param StartBit The ordinal of the least significant bit in the bit field.
1087 @param EndBit The ordinal of the most significant bit in the bit field.
1089 @param Value The new value of the bit field.
1091 @return The value written back to the PCI configuration register.
1096 PciBitFieldWrite32 (
1105 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1110 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1111 writes the result back to the bit field in the 32-bit port.
1113 Reads the 32-bit PCI configuration register specified by Address, performs a
1114 bitwise OR between the read result and the value specified by
1115 OrData, and writes the result to the 32-bit PCI configuration register
1116 specified by Address. The value written to the PCI configuration register is
1117 returned. This function must guarantee that all PCI read and write operations
1118 are serialized. Extra left bits in OrData are stripped.
1120 If Address > 0x0FFFFFFF, then ASSERT().
1121 If Address is not aligned on a 32-bit boundary, then ASSERT().
1122 If StartBit is greater than 31, then ASSERT().
1123 If EndBit is greater than 31, then ASSERT().
1124 If EndBit is less than StartBit, then ASSERT().
1125 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1127 @param Address The PCI configuration register to write.
1128 @param StartBit The ordinal of the least significant bit in the bit field.
1130 @param EndBit The ordinal of the most significant bit in the bit field.
1132 @param OrData The value to OR with the PCI configuration register.
1134 @return The value written back to the PCI configuration register.
1148 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1153 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1154 AND, and writes the result back to the bit field in the 32-bit register.
1156 Reads the 32-bit PCI configuration register specified by Address, performs a
1157 bitwise AND between the read result and the value specified by AndData, and
1158 writes the result to the 32-bit PCI configuration register specified by
1159 Address. The value written to the PCI configuration register is returned.
1160 This function must guarantee that all PCI read and write operations are
1161 serialized. Extra left bits in AndData are stripped.
1163 If Address > 0x0FFFFFFF, then ASSERT().
1164 If Address is not aligned on a 32-bit boundary, then ASSERT().
1165 If StartBit is greater than 31, then ASSERT().
1166 If EndBit is greater than 31, then ASSERT().
1167 If EndBit is less than StartBit, then ASSERT().
1168 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1170 @param Address The PCI configuration register to write.
1171 @param StartBit The ordinal of the least significant bit in the bit field.
1173 @param EndBit The ordinal of the most significant bit in the bit field.
1175 @param AndData The value to AND with the PCI configuration register.
1177 @return The value written back to the PCI configuration register.
1191 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1196 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1197 bitwise OR, and writes the result back to the bit field in the
1200 Reads the 32-bit PCI configuration register specified by Address, performs a
1201 bitwise AND followed by a bitwise OR between the read result and
1202 the value specified by AndData, and writes the result to the 32-bit PCI
1203 configuration register specified by Address. The value written to the PCI
1204 configuration register is returned. This function must guarantee that all PCI
1205 read and write operations are serialized. Extra left bits in both AndData and
1206 OrData are stripped.
1208 If Address > 0x0FFFFFFF, then ASSERT().
1209 If Address is not aligned on a 32-bit boundary, then ASSERT().
1210 If StartBit is greater than 31, then ASSERT().
1211 If EndBit is greater than 31, then ASSERT().
1212 If EndBit is less than StartBit, then ASSERT().
1213 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1214 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1216 @param Address The PCI configuration register to write.
1217 @param StartBit The ordinal of the least significant bit in the bit field.
1219 @param EndBit The ordinal of the most significant bit in the bit field.
1221 @param AndData The value to AND with the PCI configuration register.
1222 @param OrData The value to OR with the result of the AND operation.
1224 @return The value written back to the PCI configuration register.
1229 PciBitFieldAndThenOr32 (
1239 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1244 Reads a range of PCI configuration registers into a caller supplied buffer.
1246 Reads the range of PCI configuration registers specified by StartAddress and
1247 Size into the buffer specified by Buffer. This function only allows the PCI
1248 configuration registers from a single PCI function to be read. Size is
1249 returned. When possible 32-bit PCI configuration read cycles are used to read
1250 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1251 and 16-bit PCI configuration read cycles may be used at the beginning and the
1254 If StartAddress > 0x0FFFFFFF, then ASSERT().
1255 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1256 If Size > 0 and Buffer is NULL, then ASSERT().
1258 @param StartAddress The starting address that encodes the PCI Bus, Device,
1259 Function and Register.
1260 @param Size The size in bytes of the transfer.
1261 @param Buffer The pointer to a buffer receiving the data read.
1269 IN UINTN StartAddress
,
1276 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1277 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1283 ASSERT (Buffer
!= NULL
);
1286 // Save Size for return
1290 if ((StartAddress
& BIT0
) != 0) {
1292 // Read a byte if StartAddress is byte aligned
1294 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1295 StartAddress
+= sizeof (UINT8
);
1296 Size
-= sizeof (UINT8
);
1297 Buffer
= (UINT8
*)Buffer
+ 1;
1300 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1302 // Read a word if StartAddress is word aligned
1304 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1305 StartAddress
+= sizeof (UINT16
);
1306 Size
-= sizeof (UINT16
);
1307 Buffer
= (UINT16
*)Buffer
+ 1;
1310 while (Size
>= sizeof (UINT32
)) {
1312 // Read as many double words as possible
1314 WriteUnaligned32 (Buffer
, PciRead32 (StartAddress
));
1315 StartAddress
+= sizeof (UINT32
);
1316 Size
-= sizeof (UINT32
);
1317 Buffer
= (UINT32
*)Buffer
+ 1;
1320 if (Size
>= sizeof (UINT16
)) {
1322 // Read the last remaining word if exist
1324 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1325 StartAddress
+= sizeof (UINT16
);
1326 Size
-= sizeof (UINT16
);
1327 Buffer
= (UINT16
*)Buffer
+ 1;
1330 if (Size
>= sizeof (UINT8
)) {
1332 // Read the last remaining byte if exist
1334 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1341 Copies the data in a caller supplied buffer to a specified range of PCI
1342 configuration space.
1344 Writes the range of PCI configuration registers specified by StartAddress and
1345 Size from the buffer specified by Buffer. This function only allows the PCI
1346 configuration registers from a single PCI function to be written. Size is
1347 returned. When possible 32-bit PCI configuration write cycles are used to
1348 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1349 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1350 and the end of the range.
1352 If StartAddress > 0x0FFFFFFF, then ASSERT().
1353 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1354 If Size > 0 and Buffer is NULL, then ASSERT().
1356 @param StartAddress The starting address that encodes the PCI Bus, Device,
1357 Function and Register.
1358 @param Size The size in bytes of the transfer.
1359 @param Buffer The pointer to a buffer containing the data to write.
1361 @return Size written to StartAddress.
1367 IN UINTN StartAddress
,
1374 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1375 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1381 ASSERT (Buffer
!= NULL
);
1384 // Save Size for return
1388 if ((StartAddress
& BIT0
) != 0) {
1390 // Write a byte if StartAddress is byte aligned
1392 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1393 StartAddress
+= sizeof (UINT8
);
1394 Size
-= sizeof (UINT8
);
1395 Buffer
= (UINT8
*)Buffer
+ 1;
1398 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1400 // Write a word if StartAddress is word aligned
1402 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1403 StartAddress
+= sizeof (UINT16
);
1404 Size
-= sizeof (UINT16
);
1405 Buffer
= (UINT16
*)Buffer
+ 1;
1408 while (Size
>= sizeof (UINT32
)) {
1410 // Write as many double words as possible
1412 PciWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1413 StartAddress
+= sizeof (UINT32
);
1414 Size
-= sizeof (UINT32
);
1415 Buffer
= (UINT32
*)Buffer
+ 1;
1418 if (Size
>= sizeof (UINT16
)) {
1420 // Write the last remaining word if exist
1422 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1423 StartAddress
+= sizeof (UINT16
);
1424 Size
-= sizeof (UINT16
);
1425 Buffer
= (UINT16
*)Buffer
+ 1;
1428 if (Size
>= sizeof (UINT8
)) {
1430 // Write the last remaining byte if exist
1432 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);