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git.proxmox.com Git - mirror_edk2.git/blob - OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
2 Various register numbers and value bits based on the following publications:
3 - Intel(R) datasheet 316966-002
4 - Intel(R) datasheet 316972-004
6 Copyright (C) 2015, Red Hat, Inc.
7 Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
9 This program and the accompanying materials are licensed and made available
10 under the terms and conditions of the BSD License which accompanies this
11 distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
15 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #ifndef __Q35_MCH_ICH9_H__
19 #define __Q35_MCH_ICH9_H__
21 #include <Library/PciLib.h>
22 #include <Uefi/UefiBaseType.h>
23 #include <Uefi/UefiSpec.h>
24 #include <Protocol/PciRootBridgeIo.h>
27 // Host Bridge Device ID (DID) value for Q35/MCH
29 #define INTEL_Q35_MCH_DEVICE_ID 0x29C0
32 // B/D/F/Type: 0/0/0/PCI
34 #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
36 #define MCH_EXT_TSEG_MB 0x50
37 #define MCH_EXT_TSEG_MB_QUERY 0xFFFF
40 #define MCH_GGC_IVD BIT1
42 #define MCH_PCIEXBAR_LOW 0x60
43 #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
44 #define MCH_PCIEXBAR_BUS_FF 0
45 #define MCH_PCIEXBAR_EN BIT0
47 #define MCH_PCIEXBAR_HIGH 0x64
48 #define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
58 #define MCH_SMRAM 0x9D
59 #define MCH_SMRAM_D_LCK BIT4
60 #define MCH_SMRAM_G_SMRAME BIT3
62 #define MCH_ESMRAMC 0x9E
63 #define MCH_ESMRAMC_H_SMRAME BIT7
64 #define MCH_ESMRAMC_E_SMERR BIT6
65 #define MCH_ESMRAMC_SM_CACHE BIT5
66 #define MCH_ESMRAMC_SM_L1 BIT4
67 #define MCH_ESMRAMC_SM_L2 BIT3
68 #define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)
69 #define MCH_ESMRAMC_TSEG_8MB BIT2
70 #define MCH_ESMRAMC_TSEG_2MB BIT1
71 #define MCH_ESMRAMC_TSEG_1MB 0
72 #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)
73 #define MCH_ESMRAMC_T_EN BIT0
76 #define MCH_GBSM_MB_SHIFT 20
79 #define MCH_BGSM_MB_SHIFT 20
81 #define MCH_TSEGMB 0xAC
82 #define MCH_TSEGMB_MB_SHIFT 20
84 #define MCH_TOLUD 0xB0
85 #define MCH_TOLUD_MB_SHIFT 4
88 // B/D/F/Type: 0/0x1f/0/PCI
90 #define POWER_MGMT_REGISTER_Q35(Offset) \
91 PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
93 #define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \
94 EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))
96 #define ICH9_PMBASE 0x40
97 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
98 BIT10 | BIT9 | BIT8 | BIT7)
100 #define ICH9_ACPI_CNTL 0x44
101 #define ICH9_ACPI_CNTL_ACPI_EN BIT7
103 #define ICH9_GEN_PMCON_1 0xA0
104 #define ICH9_GEN_PMCON_1_SMI_LOCK BIT4
106 #define ICH9_RCBA 0xF0
107 #define ICH9_RCBA_EN BIT0
112 #define ICH9_APM_CNT 0xB2
113 #define ICH9_APM_STS 0xB3
116 // IO ports relative to PMBASE
118 #define ICH9_PMBASE_OFS_SMI_EN 0x30
119 #define ICH9_SMI_EN_APMC_EN BIT5
120 #define ICH9_SMI_EN_GBL_SMI_EN BIT0
122 #define ICH9_ROOT_COMPLEX_BASE 0xFED1C000