2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
5 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "UefiShellDebug1CommandsLib.h"
17 #include <Protocol/PciRootBridgeIo.h>
18 #include <Library/ShellLib.h>
19 #include <IndustryStandard/Pci.h>
20 #include <IndustryStandard/Acpi.h>
23 #define PCI_CLASS_STRING_LIMIT 54
25 // Printable strings for Pci class code
28 CHAR16
*BaseClass
; // Pointer to the PCI base class string
29 CHAR16
*SubClass
; // Pointer to the PCI sub class string
30 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
34 // a structure holding a single entry, which also points to its lower level
37 typedef struct PCI_CLASS_ENTRY_TAG
{
38 UINT8 Code
; // Class, subclass or I/F code
39 CHAR16
*DescText
; // Description string
40 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
44 // Declarations of entries which contain printable strings for class codes
45 // in PCI configuration space
47 PCI_CLASS_ENTRY PCIBlankEntry
[];
48 PCI_CLASS_ENTRY PCISubClass_00
[];
49 PCI_CLASS_ENTRY PCISubClass_01
[];
50 PCI_CLASS_ENTRY PCISubClass_02
[];
51 PCI_CLASS_ENTRY PCISubClass_03
[];
52 PCI_CLASS_ENTRY PCISubClass_04
[];
53 PCI_CLASS_ENTRY PCISubClass_05
[];
54 PCI_CLASS_ENTRY PCISubClass_06
[];
55 PCI_CLASS_ENTRY PCISubClass_07
[];
56 PCI_CLASS_ENTRY PCISubClass_08
[];
57 PCI_CLASS_ENTRY PCISubClass_09
[];
58 PCI_CLASS_ENTRY PCISubClass_0a
[];
59 PCI_CLASS_ENTRY PCISubClass_0b
[];
60 PCI_CLASS_ENTRY PCISubClass_0c
[];
61 PCI_CLASS_ENTRY PCISubClass_0d
[];
62 PCI_CLASS_ENTRY PCISubClass_0e
[];
63 PCI_CLASS_ENTRY PCISubClass_0f
[];
64 PCI_CLASS_ENTRY PCISubClass_10
[];
65 PCI_CLASS_ENTRY PCISubClass_11
[];
66 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
82 // Base class strings entries
84 PCI_CLASS_ENTRY gClassStringList
[] = {
92 L
"Mass Storage Controller",
97 L
"Network Controller",
102 L
"Display Controller",
107 L
"Multimedia Device",
112 L
"Memory Controller",
122 L
"Simple Communications Controllers",
127 L
"Base System Peripherals",
147 L
"Serial Bus Controllers",
152 L
"Wireless Controllers",
157 L
"Intelligent IO Controllers",
162 L
"Satellite Communications Controllers",
167 L
"Encryption/Decryption Controllers",
172 L
"Data Acquisition & Signal Processing Controllers",
177 L
"Device does not fit in any defined classes",
183 /* null string ends the list */NULL
188 // Subclass strings entries
190 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
199 /* null string ends the list */NULL
203 PCI_CLASS_ENTRY PCISubClass_00
[] = {
206 L
"All devices other than VGA",
211 L
"VGA-compatible devices",
217 /* null string ends the list */NULL
221 PCI_CLASS_ENTRY PCISubClass_01
[] = {
234 L
"Floppy disk controller",
249 L
"Other mass storage controller",
255 /* null string ends the list */NULL
259 PCI_CLASS_ENTRY PCISubClass_02
[] = {
262 L
"Ethernet controller",
267 L
"Token ring controller",
287 L
"Other network controller",
293 /* null string ends the list */NULL
297 PCI_CLASS_ENTRY PCISubClass_03
[] = {
300 L
"VGA/8514 controller",
315 L
"Other display controller",
321 /* null string ends the list */PCIBlankEntry
325 PCI_CLASS_ENTRY PCISubClass_04
[] = {
338 L
"Computer Telephony device",
343 L
"Other multimedia device",
349 /* null string ends the list */NULL
353 PCI_CLASS_ENTRY PCISubClass_05
[] = {
356 L
"RAM memory controller",
361 L
"Flash memory controller",
366 L
"Other memory controller",
372 /* null string ends the list */NULL
376 PCI_CLASS_ENTRY PCISubClass_06
[] = {
394 L
"PCI/Micro Channel bridge",
404 L
"PCI/PCMCIA bridge",
424 L
"Other bridge type",
430 /* null string ends the list */NULL
434 PCI_CLASS_ENTRY PCISubClass_07
[] = {
437 L
"Serial controller",
447 L
"Multiport serial controller",
457 L
"Other communication device",
463 /* null string ends the list */NULL
467 PCI_CLASS_ENTRY PCISubClass_08
[] = {
490 L
"Generic PCI Hot-Plug controller",
495 L
"Other system peripheral",
501 /* null string ends the list */NULL
505 PCI_CLASS_ENTRY PCISubClass_09
[] = {
508 L
"Keyboard controller",
523 L
"Scanner controller",
528 L
"Gameport controller",
533 L
"Other input controller",
539 /* null string ends the list */NULL
543 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
546 L
"Generic docking station",
551 L
"Other type of docking station",
557 /* null string ends the list */NULL
561 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
605 /* null string ends the list */NULL
609 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
612 L
"Firewire(IEEE 1394)",
637 L
"System Management Bus",
648 /* null string ends the list */NULL
652 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
655 L
"iRDA compatible controller",
660 L
"Consumer IR controller",
670 L
"Other type of wireless controller",
676 /* null string ends the list */NULL
680 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
689 /* null string ends the list */NULL
693 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
717 /* null string ends the list */NULL
721 PCI_CLASS_ENTRY PCISubClass_10
[] = {
724 L
"Network & computing Encrypt/Decrypt",
729 L
"Entertainment Encrypt/Decrypt",
734 L
"Other Encrypt/Decrypt",
740 /* null string ends the list */NULL
744 PCI_CLASS_ENTRY PCISubClass_11
[] = {
752 L
"Other DAQ & SP controllers",
758 /* null string ends the list */NULL
763 // Programming Interface entries
765 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
793 L
"OM-primary, OM-secondary",
798 L
"PI-primary, OM-secondary",
803 L
"OM/PI-primary, OM-secondary",
813 L
"OM-primary, PI-secondary",
818 L
"PI-primary, PI-secondary",
823 L
"OM/PI-primary, PI-secondary",
833 L
"OM-primary, OM/PI-secondary",
838 L
"PI-primary, OM/PI-secondary",
843 L
"OM/PI-primary, OM/PI-secondary",
853 L
"Master, OM-primary",
858 L
"Master, PI-primary",
863 L
"Master, OM/PI-primary",
868 L
"Master, OM-secondary",
873 L
"Master, OM-primary, OM-secondary",
878 L
"Master, PI-primary, OM-secondary",
883 L
"Master, OM/PI-primary, OM-secondary",
888 L
"Master, OM-secondary",
893 L
"Master, OM-primary, PI-secondary",
898 L
"Master, PI-primary, PI-secondary",
903 L
"Master, OM/PI-primary, PI-secondary",
908 L
"Master, OM-secondary",
913 L
"Master, OM-primary, OM/PI-secondary",
918 L
"Master, PI-primary, OM/PI-secondary",
923 L
"Master, OM/PI-primary, OM/PI-secondary",
929 /* null string ends the list */NULL
933 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
947 /* null string ends the list */NULL
951 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
959 L
"Subtractive decode",
965 /* null string ends the list */NULL
969 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
972 L
"Generic XT-compatible",
1002 L
"16950-compatible",
1008 /* null string ends the list */NULL
1012 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1025 L
"ECP 1.X-compliant",
1035 L
"IEEE 1284 target (not a controller)",
1041 /* null string ends the list */NULL
1045 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1053 L
"Hayes-compatible 16450",
1058 L
"Hayes-compatible 16550",
1063 L
"Hayes-compatible 16650",
1068 L
"Hayes-compatible 16750",
1074 /* null string ends the list */NULL
1078 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1101 L
"IO(x) APIC interrupt controller",
1107 /* null string ends the list */NULL
1111 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1130 /* null string ends the list */NULL
1134 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1153 /* null string ends the list */NULL
1157 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1176 /* null string ends the list */NULL
1180 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1194 /* null string ends the list */NULL
1198 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1201 L
"Universal Host Controller spec",
1206 L
"Open Host Controller spec",
1211 L
"No specific programming interface",
1216 L
"(Not Host Controller)",
1222 /* null string ends the list */NULL
1226 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1234 L
"Using 1394 OpenHCI spec",
1240 /* null string ends the list */NULL
1244 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1247 L
"Message FIFO at offset 40h",
1258 /* null string ends the list */NULL
1264 Generates printable Unicode strings that represent PCI device class,
1265 subclass and programmed I/F based on a value passed to the function.
1267 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1268 PCI device. The encodings are:
1269 bits 23:16 - Base Class Code
1270 bits 15:8 - Sub-Class Code
1271 bits 7:0 - Programming Interface
1272 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1273 printable class strings corresponding to ClassCode. The
1274 caller must not modify the strings that are pointed by
1275 the fields in ClassStrings.
1278 PciGetClassStrings (
1279 IN UINT32 ClassCode
,
1280 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1285 PCI_CLASS_ENTRY
*CurrentClass
;
1288 // Assume no strings found
1290 ClassStrings
->BaseClass
= L
"UNDEFINED";
1291 ClassStrings
->SubClass
= L
"UNDEFINED";
1292 ClassStrings
->PIFClass
= L
"UNDEFINED";
1294 CurrentClass
= gClassStringList
;
1295 Code
= (UINT8
) (ClassCode
>> 16);
1299 // Go through all entries of the base class, until the entry with a matching
1300 // base class code is found. If reaches an entry with a null description
1301 // text, the last entry is met, which means no text for the base class was
1302 // found, so no more action is needed.
1304 while (Code
!= CurrentClass
[Index
].Code
) {
1305 if (NULL
== CurrentClass
[Index
].DescText
) {
1312 // A base class was found. Assign description, and check if this class has
1313 // sub-class defined. If sub-class defined, no more action is needed,
1314 // otherwise, continue to find description for the sub-class code.
1316 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1317 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1321 // find Subclass entry
1323 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1324 Code
= (UINT8
) (ClassCode
>> 8);
1328 // Go through all entries of the sub-class, until the entry with a matching
1329 // sub-class code is found. If reaches an entry with a null description
1330 // text, the last entry is met, which means no text for the sub-class was
1331 // found, so no more action is needed.
1333 while (Code
!= CurrentClass
[Index
].Code
) {
1334 if (NULL
== CurrentClass
[Index
].DescText
) {
1341 // A class was found for the sub-class code. Assign description, and check if
1342 // this sub-class has programming interface defined. If no, no more action is
1343 // needed, otherwise, continue to find description for the programming
1346 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1347 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1351 // Find programming interface entry
1353 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1354 Code
= (UINT8
) ClassCode
;
1358 // Go through all entries of the I/F entries, until the entry with a
1359 // matching I/F code is found. If reaches an entry with a null description
1360 // text, the last entry is met, which means no text was found, so no more
1361 // action is needed.
1363 while (Code
!= CurrentClass
[Index
].Code
) {
1364 if (NULL
== CurrentClass
[Index
].DescText
) {
1371 // A class was found for the I/F code. Assign description, done!
1373 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1378 Print strings that represent PCI device class, subclass and programmed I/F.
1380 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1382 @param[in] IncludePIF If the printed string should include the programming I/F part
1386 IN UINT8
*ClassCodePtr
,
1387 IN BOOLEAN IncludePIF
1391 PCI_CLASS_STRINGS ClassStrings
;
1394 ClassCode
|= ClassCodePtr
[0];
1395 ClassCode
|= (ClassCodePtr
[1] << 8);
1396 ClassCode
|= (ClassCodePtr
[2] << 16);
1399 // Get name from class code
1401 PciGetClassStrings (ClassCode
, &ClassStrings
);
1405 // Print base class, sub class, and programming inferface name
1407 ShellPrintEx (-1, -1, L
"%s - %s - %s",
1408 ClassStrings
.BaseClass
,
1409 ClassStrings
.SubClass
,
1410 ClassStrings
.PIFClass
1415 // Only print base class and sub class name
1417 ShellPrintEx (-1, -1, L
"%s - %s",
1418 ClassStrings
.BaseClass
,
1419 ClassStrings
.SubClass
1425 This function finds out the protocol which is in charge of the given
1426 segment, and its bus range covers the current bus number. It lookes
1427 each instances of RootBridgeIoProtocol handle, until the one meets the
1430 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1431 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1432 @param[in] Segment Segment number of device we are dealing with.
1433 @param[in] Bus Bus number of device we are dealing with.
1434 @param[out] IoDev Handle used to access configuration space of PCI device.
1436 @retval EFI_SUCCESS The command completed successfully.
1437 @retval EFI_INVALID_PARAMETER Invalid parameter.
1441 PciFindProtocolInterface (
1442 IN EFI_HANDLE
*HandleBuf
,
1443 IN UINTN HandleCount
,
1446 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1450 This function gets the protocol interface from the given handle, and
1451 obtains its address space descriptors.
1453 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1454 @param[out] IoDev Handle used to access configuration space of PCI device.
1455 @param[out] Descriptors Points to the address space descriptors.
1457 @retval EFI_SUCCESS The command completed successfully
1460 PciGetProtocolAndResource (
1461 IN EFI_HANDLE Handle
,
1462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1463 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1467 This function get the next bus range of given address space descriptors.
1468 It also moves the pointer backward a node, to get prepared to be called
1471 @param[in, out] Descriptors Points to current position of a serial of address space
1473 @param[out] MinBus The lower range of bus number.
1474 @param[out] MaxBus The upper range of bus number.
1475 @param[out] IsEnd Meet end of the serial of descriptors.
1477 @retval EFI_SUCCESS The command completed successfully.
1480 PciGetNextBusRange (
1481 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1488 Explain the data in PCI configuration space. The part which is common for
1489 PCI device and bridge is interpreted in this function. It calls other
1490 functions to interpret data unique for device or bridge.
1492 @param[in] ConfigSpace Data in PCI configuration space.
1493 @param[in] Address Address used to access configuration space of this PCI device.
1494 @param[in] IoDev Handle used to access configuration space of PCI device.
1496 @retval EFI_SUCCESS The command completed successfully.
1500 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1502 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1506 Explain the device specific part of data in PCI configuration space.
1508 @param[in] Device Data in PCI configuration space.
1509 @param[in] Address Address used to access configuration space of this PCI device.
1510 @param[in] IoDev Handle used to access configuration space of PCI device.
1512 @retval EFI_SUCCESS The command completed successfully.
1515 PciExplainDeviceData (
1516 IN PCI_DEVICE_HEADER
*Device
,
1518 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1522 Explain the bridge specific part of data in PCI configuration space.
1524 @param[in] Bridge Bridge specific data region in PCI configuration space.
1525 @param[in] Address Address used to access configuration space of this PCI device.
1526 @param[in] IoDev Handle used to access configuration space of PCI device.
1528 @retval EFI_SUCCESS The command completed successfully.
1531 PciExplainBridgeData (
1532 IN PCI_BRIDGE_HEADER
*Bridge
,
1534 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1538 Explain the Base Address Register(Bar) in PCI configuration space.
1540 @param[in] Bar Points to the Base Address Register intended to interpret.
1541 @param[in] Command Points to the register Command.
1542 @param[in] Address Address used to access configuration space of this PCI device.
1543 @param[in] IoDev Handle used to access configuration space of PCI device.
1544 @param[in, out] Index The Index.
1546 @retval EFI_SUCCESS The command completed successfully.
1553 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1558 Explain the cardbus specific part of data in PCI configuration space.
1560 @param[in] CardBus CardBus specific region of PCI configuration space.
1561 @param[in] Address Address used to access configuration space of this PCI device.
1562 @param[in] IoDev Handle used to access configuration space of PCI device.
1564 @retval EFI_SUCCESS The command completed successfully.
1567 PciExplainCardBusData (
1568 IN PCI_CARDBUS_HEADER
*CardBus
,
1570 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1574 Explain each meaningful bit of register Status. The definition of Status is
1575 slightly different depending on the PCI header type.
1577 @param[in] Status Points to the content of register Status.
1578 @param[in] MainStatus Indicates if this register is main status(not secondary
1580 @param[in] HeaderType Header type of this PCI device.
1582 @retval EFI_SUCCESS The command completed successfully.
1587 IN BOOLEAN MainStatus
,
1588 IN PCI_HEADER_TYPE HeaderType
1592 Explain each meaningful bit of register Command.
1594 @param[in] Command Points to the content of register Command.
1596 @retval EFI_SUCCESS The command completed successfully.
1604 Explain each meaningful bit of register Bridge Control.
1606 @param[in] BridgeControl Points to the content of register Bridge Control.
1607 @param[in] HeaderType The headertype.
1609 @retval EFI_SUCCESS The command completed successfully.
1612 PciExplainBridgeControl (
1613 IN UINT16
*BridgeControl
,
1614 IN PCI_HEADER_TYPE HeaderType
1618 Print each capability structure.
1620 @param[in] IoDev The pointer to the deivce.
1621 @param[in] Address The address to start at.
1622 @param[in] CapPtr The offset from the address.
1624 @retval EFI_SUCCESS The operation was successful.
1627 PciExplainCapabilityStruct (
1628 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1634 Display Pcie device structure.
1636 @param[in] IoDev The pointer to the root pci protocol.
1637 @param[in] Address The Address to start at.
1638 @param[in] CapabilityPtr The offset from the address to start.
1641 PciExplainPciExpress (
1642 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1644 IN UINT8 CapabilityPtr
1648 Print out information of the capability information.
1650 @param[in] PciExpressCap The pointer to the structure about the device.
1652 @retval EFI_SUCCESS The operation was successful.
1656 IN PCIE_CAP_STURCTURE
*PciExpressCap
1660 Print out information of the device capability information.
1662 @param[in] PciExpressCap The pointer to the structure about the device.
1664 @retval EFI_SUCCESS The operation was successful.
1667 ExplainPcieDeviceCap (
1668 IN PCIE_CAP_STURCTURE
*PciExpressCap
1672 Print out information of the device control information.
1674 @param[in] PciExpressCap The pointer to the structure about the device.
1676 @retval EFI_SUCCESS The operation was successful.
1679 ExplainPcieDeviceControl (
1680 IN PCIE_CAP_STURCTURE
*PciExpressCap
1684 Print out information of the device status information.
1686 @param[in] PciExpressCap The pointer to the structure about the device.
1688 @retval EFI_SUCCESS The operation was successful.
1691 ExplainPcieDeviceStatus (
1692 IN PCIE_CAP_STURCTURE
*PciExpressCap
1696 Print out information of the device link information.
1698 @param[in] PciExpressCap The pointer to the structure about the device.
1700 @retval EFI_SUCCESS The operation was successful.
1703 ExplainPcieLinkCap (
1704 IN PCIE_CAP_STURCTURE
*PciExpressCap
1708 Print out information of the device link control information.
1710 @param[in] PciExpressCap The pointer to the structure about the device.
1712 @retval EFI_SUCCESS The operation was successful.
1715 ExplainPcieLinkControl (
1716 IN PCIE_CAP_STURCTURE
*PciExpressCap
1720 Print out information of the device link status information.
1722 @param[in] PciExpressCap The pointer to the structure about the device.
1724 @retval EFI_SUCCESS The operation was successful.
1727 ExplainPcieLinkStatus (
1728 IN PCIE_CAP_STURCTURE
*PciExpressCap
1732 Print out information of the device slot information.
1734 @param[in] PciExpressCap The pointer to the structure about the device.
1736 @retval EFI_SUCCESS The operation was successful.
1739 ExplainPcieSlotCap (
1740 IN PCIE_CAP_STURCTURE
*PciExpressCap
1744 Print out information of the device slot control information.
1746 @param[in] PciExpressCap The pointer to the structure about the device.
1748 @retval EFI_SUCCESS The operation was successful.
1751 ExplainPcieSlotControl (
1752 IN PCIE_CAP_STURCTURE
*PciExpressCap
1756 Print out information of the device slot status information.
1758 @param[in] PciExpressCap The pointer to the structure about the device.
1760 @retval EFI_SUCCESS The operation was successful.
1763 ExplainPcieSlotStatus (
1764 IN PCIE_CAP_STURCTURE
*PciExpressCap
1768 Print out information of the device root information.
1770 @param[in] PciExpressCap The pointer to the structure about the device.
1772 @retval EFI_SUCCESS The operation was successful.
1775 ExplainPcieRootControl (
1776 IN PCIE_CAP_STURCTURE
*PciExpressCap
1780 Print out information of the device root capability information.
1782 @param[in] PciExpressCap The pointer to the structure about the device.
1784 @retval EFI_SUCCESS The operation was successful.
1787 ExplainPcieRootCap (
1788 IN PCIE_CAP_STURCTURE
*PciExpressCap
1792 Print out information of the device root status information.
1794 @param[in] PciExpressCap The pointer to the structure about the device.
1796 @retval EFI_SUCCESS The operation was successful.
1799 ExplainPcieRootStatus (
1800 IN PCIE_CAP_STURCTURE
*PciExpressCap
1803 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCIE_CAP_STURCTURE
*PciExpressCap
);
1809 } PCIE_CAPREG_FIELD_WIDTH
;
1812 PcieExplainTypeCommon
,
1813 PcieExplainTypeDevice
,
1814 PcieExplainTypeLink
,
1815 PcieExplainTypeSlot
,
1816 PcieExplainTypeRoot
,
1818 } PCIE_EXPLAIN_TYPE
;
1824 PCIE_CAPREG_FIELD_WIDTH Width
;
1825 PCIE_EXPLAIN_FUNCTION Func
;
1826 PCIE_EXPLAIN_TYPE Type
;
1827 } PCIE_EXPLAIN_STRUCT
;
1829 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
1831 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
1835 PcieExplainTypeCommon
1838 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
1842 PcieExplainTypeCommon
1845 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
1849 PcieExplainTypeCommon
1852 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
1855 ExplainPcieDeviceCap
,
1856 PcieExplainTypeDevice
1859 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
1862 ExplainPcieDeviceControl
,
1863 PcieExplainTypeDevice
1866 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
1869 ExplainPcieDeviceStatus
,
1870 PcieExplainTypeDevice
1873 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
1880 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
1883 ExplainPcieLinkControl
,
1887 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
1890 ExplainPcieLinkStatus
,
1894 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
1901 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
1904 ExplainPcieSlotControl
,
1908 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
1911 ExplainPcieSlotStatus
,
1915 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
1918 ExplainPcieRootControl
,
1922 STRING_TOKEN (STR_PCIEX_RSVDP
),
1929 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
1932 ExplainPcieRootStatus
,
1938 (PCIE_CAPREG_FIELD_WIDTH
)0,
1947 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
1948 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
1954 CHAR16
*DevicePortTypeTable
[] = {
1955 L
"PCI Express Endpoint",
1956 L
"Legacy PCI Express Endpoint",
1959 L
"Root Port of PCI Express Root Complex",
1960 L
"Upstream Port of PCI Express Switch",
1961 L
"Downstream Port of PCI Express Switch",
1962 L
"PCI Express to PCI/PCI-X Bridge",
1963 L
"PCI/PCI-X to PCI Express Bridge",
1964 L
"Root Complex Integrated Endpoint",
1965 L
"Root Complex Event Collector"
1968 CHAR16
*L0sLatencyStrTable
[] = {
1970 L
"64ns to less than 128ns",
1971 L
"128ns to less than 256ns",
1972 L
"256ns to less than 512ns",
1973 L
"512ns to less than 1us",
1974 L
"1us to less than 2us",
1979 CHAR16
*L1LatencyStrTable
[] = {
1981 L
"1us to less than 2us",
1982 L
"2us to less than 4us",
1983 L
"4us to less than 8us",
1984 L
"8us to less than 16us",
1985 L
"16us to less than 32us",
1990 CHAR16
*ASPMCtrlStrTable
[] = {
1992 L
"L0s Entry Enabled",
1993 L
"L1 Entry Enabled",
1994 L
"L0s and L1 Entry Enabled"
1997 CHAR16
*SlotPwrLmtScaleTable
[] = {
2004 CHAR16
*IndicatorTable
[] = {
2013 Function for 'pci' command.
2015 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2016 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2020 ShellCommandRunPci (
2021 IN EFI_HANDLE ImageHandle
,
2022 IN EFI_SYSTEM_TABLE
*SystemTable
2030 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2032 PCI_COMMON_HEADER PciHeader
;
2033 PCI_CONFIG_SPACE ConfigSpace
;
2037 BOOLEAN ExplainData
;
2041 UINTN HandleBufSize
;
2042 EFI_HANDLE
*HandleBuf
;
2044 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2048 LIST_ENTRY
*Package
;
2049 CHAR16
*ProblemParam
;
2050 SHELL_STATUS ShellStatus
;
2054 ShellStatus
= SHELL_SUCCESS
;
2055 Status
= EFI_SUCCESS
;
2062 // initialize the shell lib (we must be in non-auto-init...)
2064 Status
= ShellInitialize();
2065 ASSERT_EFI_ERROR(Status
);
2067 Status
= CommandInit();
2068 ASSERT_EFI_ERROR(Status
);
2071 // parse the command line
2073 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2074 if (EFI_ERROR(Status
)) {
2075 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2076 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, ProblemParam
);
2077 FreePool(ProblemParam
);
2078 ShellStatus
= SHELL_INVALID_PARAMETER
;
2084 if (ShellCommandLineGetCount(Package
) == 2) {
2085 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
);
2086 ShellStatus
= SHELL_INVALID_PARAMETER
;
2090 if (ShellCommandLineGetCount(Package
) > 4) {
2091 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
);
2092 ShellStatus
= SHELL_INVALID_PARAMETER
;
2095 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2096 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"-s");
2097 ShellStatus
= SHELL_INVALID_PARAMETER
;
2101 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2102 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2103 // space for handles and call it again.
2105 HandleBufSize
= sizeof (EFI_HANDLE
);
2106 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2107 if (HandleBuf
== NULL
) {
2108 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2109 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2113 Status
= gBS
->LocateHandle (
2115 &gEfiPciRootBridgeIoProtocolGuid
,
2121 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2122 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2123 if (HandleBuf
== NULL
) {
2124 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2125 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2129 Status
= gBS
->LocateHandle (
2131 &gEfiPciRootBridgeIoProtocolGuid
,
2138 if (EFI_ERROR (Status
)) {
2139 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
);
2140 ShellStatus
= SHELL_NOT_FOUND
;
2144 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2146 // Argument Count == 1(no other argument): enumerate all pci functions
2148 if (ShellCommandLineGetCount(Package
) == 1) {
2149 gST
->ConOut
->QueryMode (
2151 gST
->ConOut
->Mode
->Mode
,
2158 if ((ScreenSize
& 1) == 1) {
2165 // For each handle, which decides a segment and a bus number range,
2166 // enumerate all devices on it.
2168 for (Index
= 0; Index
< HandleCount
; Index
++) {
2169 Status
= PciGetProtocolAndResource (
2174 if (EFI_ERROR (Status
)) {
2175 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, Status
);
2176 ShellStatus
= SHELL_NOT_FOUND
;
2180 // No document say it's impossible for a RootBridgeIo protocol handle
2181 // to have more than one address space descriptors, so find out every
2182 // bus range and for each of them do device enumeration.
2185 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2187 if (EFI_ERROR (Status
)) {
2188 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, Status
);
2189 ShellStatus
= SHELL_NOT_FOUND
;
2197 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2199 // For each devices, enumerate all functions it contains
2201 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2203 // For each function, read its configuration space and print summary
2205 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2206 if (ShellGetExecutionBreakFlag ()) {
2207 ShellStatus
= SHELL_ABORTED
;
2210 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2220 // If VendorId = 0xffff, there does not exist a device at this
2221 // location. For each device, if there is any function on it,
2222 // there must be 1 function at Function 0. So if Func = 0, there
2223 // will be no more functions in the same device, so we can break
2224 // loop to deal with the next device.
2226 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2230 if (PciHeader
.VendorId
!= 0xffff) {
2233 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2241 sizeof (PciHeader
) / sizeof (UINT32
),
2246 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2247 IoDev
->SegmentNumber
,
2253 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2255 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2258 PciHeader
.ClassCode
[0]
2262 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2264 // If ScreenSize == 0 we have the console redirected so don't
2270 // If this is not a multi-function device, we can leave the loop
2271 // to deal with the next device.
2273 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2281 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2282 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2283 // devices on all bus, we can leave loop.
2285 if (Descriptors
== NULL
) {
2291 Status
= EFI_SUCCESS
;
2295 ExplainData
= FALSE
;
2300 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2304 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2307 // Input converted to hexadecimal number.
2309 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2310 Segment
= (UINT16
) RetVal
;
2312 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2313 ShellStatus
= SHELL_INVALID_PARAMETER
;
2319 // The first Argument(except "-i") is assumed to be Bus number, second
2320 // to be Device number, and third to be Func number.
2322 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2325 // Input converted to hexadecimal number.
2327 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2328 Bus
= (UINT16
) RetVal
;
2330 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2331 ShellStatus
= SHELL_INVALID_PARAMETER
;
2335 if (Bus
> MAX_BUS_NUMBER
) {
2336 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2337 ShellStatus
= SHELL_INVALID_PARAMETER
;
2341 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2344 // Input converted to hexadecimal number.
2346 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2347 Device
= (UINT16
) RetVal
;
2349 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2350 ShellStatus
= SHELL_INVALID_PARAMETER
;
2354 if (Device
> MAX_DEVICE_NUMBER
){
2355 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2356 ShellStatus
= SHELL_INVALID_PARAMETER
;
2361 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2364 // Input converted to hexadecimal number.
2366 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2367 Func
= (UINT16
) RetVal
;
2369 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2370 ShellStatus
= SHELL_INVALID_PARAMETER
;
2374 if (Func
> MAX_FUNCTION_NUMBER
){
2375 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2376 ShellStatus
= SHELL_INVALID_PARAMETER
;
2382 // Find the protocol interface who's in charge of current segment, and its
2383 // bus range covers the current bus
2385 Status
= PciFindProtocolInterface (
2393 if (EFI_ERROR (Status
)) {
2395 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
,
2399 ShellStatus
= SHELL_NOT_FOUND
;
2403 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2404 Status
= IoDev
->Pci
.Read (
2408 sizeof (ConfigSpace
),
2412 if (EFI_ERROR (Status
)) {
2413 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, Status
);
2414 ShellStatus
= SHELL_ACCESS_DENIED
;
2418 mConfigSpace
= &ConfigSpace
;
2423 STRING_TOKEN (STR_PCI_INFO
),
2424 gShellDebug1HiiHandle
,
2436 // Dump standard header of configuration space
2438 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2440 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2441 ShellPrintEx(-1,-1, L
"\r\n");
2444 // Dump device dependent Part of configuration space
2449 sizeof (ConfigSpace
) - SizeOfHeader
,
2454 // If "-i" appears in command line, interpret data in configuration space
2457 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
);
2461 if (HandleBuf
!= NULL
) {
2462 FreePool (HandleBuf
);
2464 if (Package
!= NULL
) {
2465 ShellCommandLineFreeVarList (Package
);
2467 mConfigSpace
= NULL
;
2472 This function finds out the protocol which is in charge of the given
2473 segment, and its bus range covers the current bus number. It lookes
2474 each instances of RootBridgeIoProtocol handle, until the one meets the
2477 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2478 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2479 @param[in] Segment Segment number of device we are dealing with.
2480 @param[in] Bus Bus number of device we are dealing with.
2481 @param[out] IoDev Handle used to access configuration space of PCI device.
2483 @retval EFI_SUCCESS The command completed successfully.
2484 @retval EFI_INVALID_PARAMETER Invalid parameter.
2488 PciFindProtocolInterface (
2489 IN EFI_HANDLE
*HandleBuf
,
2490 IN UINTN HandleCount
,
2493 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2498 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2504 // Go through all handles, until the one meets the criteria is found
2506 for (Index
= 0; Index
< HandleCount
; Index
++) {
2507 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2508 if (EFI_ERROR (Status
)) {
2512 // When Descriptors == NULL, the Configuration() is not implemented,
2513 // so we only check the Segment number
2515 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2519 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2524 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2525 if (EFI_ERROR (Status
)) {
2533 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2539 return EFI_NOT_FOUND
;
2543 This function gets the protocol interface from the given handle, and
2544 obtains its address space descriptors.
2546 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2547 @param[out] IoDev Handle used to access configuration space of PCI device.
2548 @param[out] Descriptors Points to the address space descriptors.
2550 @retval EFI_SUCCESS The command completed successfully
2553 PciGetProtocolAndResource (
2554 IN EFI_HANDLE Handle
,
2555 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
2556 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
2562 // Get inferface from protocol
2564 Status
= gBS
->HandleProtocol (
2566 &gEfiPciRootBridgeIoProtocolGuid
,
2570 if (EFI_ERROR (Status
)) {
2574 // Call Configuration() to get address space descriptors
2576 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
2577 if (Status
== EFI_UNSUPPORTED
) {
2578 *Descriptors
= NULL
;
2587 This function get the next bus range of given address space descriptors.
2588 It also moves the pointer backward a node, to get prepared to be called
2591 @param[in, out] Descriptors Points to current position of a serial of address space
2593 @param[out] MinBus The lower range of bus number.
2594 @param[out] MaxBus The upper range of bus number.
2595 @param[out] IsEnd Meet end of the serial of descriptors.
2597 @retval EFI_SUCCESS The command completed successfully.
2600 PciGetNextBusRange (
2601 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2610 // When *Descriptors is NULL, Configuration() is not implemented, so assume
2611 // range is 0~PCI_MAX_BUS
2613 if ((*Descriptors
) == NULL
) {
2615 *MaxBus
= PCI_MAX_BUS
;
2619 // *Descriptors points to one or more address space descriptors, which
2620 // ends with a end tagged descriptor. Examine each of the descriptors,
2621 // if a bus typed one is found and its bus range covers bus, this handle
2622 // is the handle we are looking for.
2625 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2626 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2627 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2628 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2630 return (EFI_SUCCESS
);
2636 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
2644 Explain the data in PCI configuration space. The part which is common for
2645 PCI device and bridge is interpreted in this function. It calls other
2646 functions to interpret data unique for device or bridge.
2648 @param[in] ConfigSpace Data in PCI configuration space.
2649 @param[in] Address Address used to access configuration space of this PCI device.
2650 @param[in] IoDev Handle used to access configuration space of PCI device.
2652 @retval EFI_SUCCESS The command completed successfully.
2656 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2658 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2661 PCI_COMMON_HEADER
*Common
;
2662 PCI_HEADER_TYPE HeaderType
;
2666 Common
= &(ConfigSpace
->Common
);
2668 ShellPrintEx (-1, -1, L
"\r\n");
2671 // Print Vendor Id and Device Id
2673 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
2674 INDEX_OF (&(Common
->VendorId
)),
2676 INDEX_OF (&(Common
->DeviceId
)),
2681 // Print register Command
2683 PciExplainCommand (&(Common
->Command
));
2686 // Print register Status
2688 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
2691 // Print register Revision ID
2693 ShellPrintEx(-1, -1, L
"\r\n");
2694 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
2695 INDEX_OF (&(Common
->RevisionId
)),
2700 // Print register BIST
2702 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->Bist
)));
2703 if ((Common
->Bist
& PCI_BIT_7
) != 0) {
2704 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->Bist
);
2706 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
2709 // Print register Cache Line Size
2711 ShellPrintHiiEx(-1, -1, NULL
,
2712 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
2713 gShellDebug1HiiHandle
,
2714 INDEX_OF (&(Common
->CacheLineSize
)),
2715 Common
->CacheLineSize
2719 // Print register Latency Timer
2721 ShellPrintHiiEx(-1, -1, NULL
,
2722 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
2723 gShellDebug1HiiHandle
,
2724 INDEX_OF (&(Common
->PrimaryLatencyTimer
)),
2725 Common
->PrimaryLatencyTimer
2729 // Print register Header Type
2731 ShellPrintHiiEx(-1, -1, NULL
,
2732 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
2733 gShellDebug1HiiHandle
,
2734 INDEX_OF (&(Common
->HeaderType
)),
2738 if ((Common
->HeaderType
& PCI_BIT_7
) != 0) {
2739 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
2742 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
2745 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
2746 switch (HeaderType
) {
2748 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
2752 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
2755 case PciCardBusBridge
:
2756 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
2760 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
2761 HeaderType
= PciUndefined
;
2765 // Print register Class Code
2767 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
2768 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
2769 ShellPrintEx (-1, -1, L
"\r\n");
2771 if (ShellGetExecutionBreakFlag()) {
2776 // Interpret remaining part of PCI configuration header depending on
2780 Status
= EFI_SUCCESS
;
2781 switch (HeaderType
) {
2783 Status
= PciExplainDeviceData (
2784 &(ConfigSpace
->NonCommon
.Device
),
2788 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilitiesPtr
;
2792 Status
= PciExplainBridgeData (
2793 &(ConfigSpace
->NonCommon
.Bridge
),
2797 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilitiesPtr
;
2800 case PciCardBusBridge
:
2801 Status
= PciExplainCardBusData (
2802 &(ConfigSpace
->NonCommon
.CardBus
),
2806 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.CapabilitiesPtr
;
2813 // If Status bit4 is 1, dump or explain capability structure
2815 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
2816 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
);
2823 Explain the device specific part of data in PCI configuration space.
2825 @param[in] Device Data in PCI configuration space.
2826 @param[in] Address Address used to access configuration space of this PCI device.
2827 @param[in] IoDev Handle used to access configuration space of PCI device.
2829 @retval EFI_SUCCESS The command completed successfully.
2832 PciExplainDeviceData (
2833 IN PCI_DEVICE_HEADER
*Device
,
2835 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2844 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
2845 // exist. If these no Bar for this function, print "none", otherwise
2846 // list detail information about this Bar.
2848 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
2851 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
2852 for (Index
= 0; Index
< BarCount
; Index
++) {
2853 if (Device
->Bar
[Index
] == 0) {
2859 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
2860 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
2863 Status
= PciExplainBar (
2864 &(Device
->Bar
[Index
]),
2865 &(mConfigSpace
->Common
.Command
),
2871 if (EFI_ERROR (Status
)) {
2877 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
2880 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
2884 // Print register Expansion ROM Base Address
2886 if ((Device
->ROMBar
& PCI_BIT_0
) == 0) {
2887 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ROMBar
)));
2890 ShellPrintHiiEx(-1, -1, NULL
,
2891 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
2892 gShellDebug1HiiHandle
,
2893 INDEX_OF (&(Device
->ROMBar
)),
2898 // Print register Cardbus CIS ptr
2900 ShellPrintHiiEx(-1, -1, NULL
,
2901 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
2902 gShellDebug1HiiHandle
,
2903 INDEX_OF (&(Device
->CardBusCISPtr
)),
2904 Device
->CardBusCISPtr
2908 // Print register Sub-vendor ID and subsystem ID
2910 ShellPrintHiiEx(-1, -1, NULL
,
2911 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
2912 gShellDebug1HiiHandle
,
2913 INDEX_OF (&(Device
->SubVendorId
)),
2917 ShellPrintHiiEx(-1, -1, NULL
,
2918 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
2919 gShellDebug1HiiHandle
,
2920 INDEX_OF (&(Device
->SubSystemId
)),
2925 // Print register Capabilities Ptr
2927 ShellPrintHiiEx(-1, -1, NULL
,
2928 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
2929 gShellDebug1HiiHandle
,
2930 INDEX_OF (&(Device
->CapabilitiesPtr
)),
2931 Device
->CapabilitiesPtr
2935 // Print register Interrupt Line and interrupt pin
2937 ShellPrintHiiEx(-1, -1, NULL
,
2938 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
2939 gShellDebug1HiiHandle
,
2940 INDEX_OF (&(Device
->InterruptLine
)),
2941 Device
->InterruptLine
2944 ShellPrintHiiEx(-1, -1, NULL
,
2945 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
2946 gShellDebug1HiiHandle
,
2947 INDEX_OF (&(Device
->InterruptPin
)),
2948 Device
->InterruptPin
2952 // Print register Min_Gnt and Max_Lat
2954 ShellPrintHiiEx(-1, -1, NULL
,
2955 STRING_TOKEN (STR_PCI2_MIN_GNT
),
2956 gShellDebug1HiiHandle
,
2957 INDEX_OF (&(Device
->MinGnt
)),
2961 ShellPrintHiiEx(-1, -1, NULL
,
2962 STRING_TOKEN (STR_PCI2_MAX_LAT
),
2963 gShellDebug1HiiHandle
,
2964 INDEX_OF (&(Device
->MaxLat
)),
2972 Explain the bridge specific part of data in PCI configuration space.
2974 @param[in] Bridge Bridge specific data region in PCI configuration space.
2975 @param[in] Address Address used to access configuration space of this PCI device.
2976 @param[in] IoDev Handle used to access configuration space of PCI device.
2978 @retval EFI_SUCCESS The command completed successfully.
2981 PciExplainBridgeData (
2982 IN PCI_BRIDGE_HEADER
*Bridge
,
2984 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2994 // Print Base Address Registers. When Bar = 0, this Bar does not
2995 // exist. If these no Bar for this function, print "none", otherwise
2996 // list detail information about this Bar.
2998 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3001 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3003 for (Index
= 0; Index
< BarCount
; Index
++) {
3004 if (Bridge
->Bar
[Index
] == 0) {
3010 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3011 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3014 Status
= PciExplainBar (
3015 &(Bridge
->Bar
[Index
]),
3016 &(mConfigSpace
->Common
.Command
),
3022 if (EFI_ERROR (Status
)) {
3028 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3030 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3034 // Expansion register ROM Base Address
3036 if ((Bridge
->ROMBar
& PCI_BIT_0
) == 0) {
3037 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ROMBar
)));
3040 ShellPrintHiiEx(-1, -1, NULL
,
3041 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3042 gShellDebug1HiiHandle
,
3043 INDEX_OF (&(Bridge
->ROMBar
)),
3048 // Print Bus Numbers(Primary, Secondary, and Subordinate
3050 ShellPrintHiiEx(-1, -1, NULL
,
3051 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3052 gShellDebug1HiiHandle
,
3053 INDEX_OF (&(Bridge
->PrimaryBus
)),
3054 INDEX_OF (&(Bridge
->SecondaryBus
)),
3055 INDEX_OF (&(Bridge
->SubordinateBus
))
3058 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3060 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3061 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3062 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3065 // Print register Secondary Latency Timer
3067 ShellPrintHiiEx(-1, -1, NULL
,
3068 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3069 gShellDebug1HiiHandle
,
3070 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3071 Bridge
->SecondaryLatencyTimer
3075 // Print register Secondary Status
3077 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3080 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3081 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3082 // base and limit address are listed.
3084 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3085 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3090 IoAddress32
= (Bridge
->IoBaseUpper
<< 16 | Bridge
->IoBase
<< 8);
3091 IoAddress32
&= 0xfffff000;
3092 ShellPrintHiiEx(-1, -1, NULL
,
3093 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3094 gShellDebug1HiiHandle
,
3095 INDEX_OF (&(Bridge
->IoBase
)),
3099 IoAddress32
= (Bridge
->IoLimitUpper
<< 16 | Bridge
->IoLimit
<< 8);
3100 IoAddress32
|= 0x00000fff;
3101 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3104 // Memory Base & Limit
3106 ShellPrintHiiEx(-1, -1, NULL
,
3107 STRING_TOKEN (STR_PCI2_MEMORY
),
3108 gShellDebug1HiiHandle
,
3109 INDEX_OF (&(Bridge
->MemoryBase
)),
3110 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3113 ShellPrintHiiEx(-1, -1, NULL
,
3114 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3115 gShellDebug1HiiHandle
,
3116 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3120 // Pre-fetch-able Memory Base & Limit
3122 ShellPrintHiiEx(-1, -1, NULL
,
3123 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3124 gShellDebug1HiiHandle
,
3125 INDEX_OF (&(Bridge
->PrefetchableMemBase
)),
3126 Bridge
->PrefetchableBaseUpper
,
3127 (Bridge
->PrefetchableMemBase
<< 16) & 0xfff00000
3130 ShellPrintHiiEx(-1, -1, NULL
,
3131 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3132 gShellDebug1HiiHandle
,
3133 Bridge
->PrefetchableLimitUpper
,
3134 (Bridge
->PrefetchableMemLimit
<< 16) | 0x000fffff
3138 // Print register Capabilities Pointer
3140 ShellPrintHiiEx(-1, -1, NULL
,
3141 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3142 gShellDebug1HiiHandle
,
3143 INDEX_OF (&(Bridge
->CapabilitiesPtr
)),
3144 Bridge
->CapabilitiesPtr
3148 // Print register Bridge Control
3150 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3153 // Print register Interrupt Line & PIN
3155 ShellPrintHiiEx(-1, -1, NULL
,
3156 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3157 gShellDebug1HiiHandle
,
3158 INDEX_OF (&(Bridge
->InterruptLine
)),
3159 Bridge
->InterruptLine
3162 ShellPrintHiiEx(-1, -1, NULL
,
3163 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3164 gShellDebug1HiiHandle
,
3165 INDEX_OF (&(Bridge
->InterruptPin
)),
3166 Bridge
->InterruptPin
3173 Explain the Base Address Register(Bar) in PCI configuration space.
3175 @param[in] Bar Points to the Base Address Register intended to interpret.
3176 @param[in] Command Points to the register Command.
3177 @param[in] Address Address used to access configuration space of this PCI device.
3178 @param[in] IoDev Handle used to access configuration space of PCI device.
3179 @param[in, out] Index The Index.
3181 @retval EFI_SUCCESS The command completed successfully.
3188 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3209 // According the bar type, list detail about this bar, for example: 32 or
3210 // 64 bits; pre-fetchable or not.
3212 if ((*Bar
& PCI_BIT_0
) == 0) {
3214 // This bar is of memory type
3218 if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) == 0) {
3219 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3220 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3221 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3223 } else if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) != 0) {
3225 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3226 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3227 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3228 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3229 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3237 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3238 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3241 if ((*Bar
& PCI_BIT_3
) == 0) {
3242 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3245 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3250 // This bar is of io type
3253 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3254 ShellPrintEx (-1, -1, L
"I/O ");
3258 // Get BAR length(or the amount of resource this bar demands for). To get
3259 // Bar length, first we should temporarily disable I/O and memory access
3260 // of this function(by set bits in the register Command), then write all
3261 // "1"s to this bar. The bar value read back is the amount of resource
3262 // this bar demands for.
3265 // Disable io & mem access
3267 OldCommand
= *Command
;
3268 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3269 RegAddress
= Address
| INDEX_OF (Command
);
3270 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3272 RegAddress
= Address
| INDEX_OF (Bar
);
3275 // Read after write the BAR to get the size
3279 NewBar32
= 0xffffffff;
3281 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3282 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3283 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3286 NewBar32
= NewBar32
& 0xfffffff0;
3287 NewBar32
= (~NewBar32
) + 1;
3290 NewBar32
= NewBar32
& 0xfffffffc;
3291 NewBar32
= (~NewBar32
) + 1;
3292 NewBar32
= NewBar32
& 0x0000ffff;
3297 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3298 NewBar64
= 0xffffffffffffffffULL
;
3300 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3301 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3302 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3305 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3306 NewBar64
= (~NewBar64
) + 1;
3309 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3310 NewBar64
= (~NewBar64
) + 1;
3311 NewBar64
= NewBar64
& 0x000000000000ffff;
3315 // Enable io & mem access
3317 RegAddress
= Address
| INDEX_OF (Command
);
3318 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3322 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3323 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3326 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3327 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3328 ShellPrintEx (-1, -1, L
" ");
3329 ShellPrintHiiEx(-1, -1, NULL
,
3330 STRING_TOKEN (STR_PCI2_RSHIFT
),
3331 gShellDebug1HiiHandle
,
3332 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3334 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3338 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3339 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3346 Explain the cardbus specific part of data in PCI configuration space.
3348 @param[in] CardBus CardBus specific region of PCI configuration space.
3349 @param[in] Address Address used to access configuration space of this PCI device.
3350 @param[in] IoDev Handle used to access configuration space of PCI device.
3352 @retval EFI_SUCCESS The command completed successfully.
3355 PciExplainCardBusData (
3356 IN PCI_CARDBUS_HEADER
*CardBus
,
3358 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3362 PCI_CARDBUS_DATA
*CardBusData
;
3364 ShellPrintHiiEx(-1, -1, NULL
,
3365 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3366 gShellDebug1HiiHandle
,
3367 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3368 CardBus
->CardBusSocketReg
3372 // Print Secondary Status
3374 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3377 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3378 // Subordinate bus number
3380 ShellPrintHiiEx(-1, -1, NULL
,
3381 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3382 gShellDebug1HiiHandle
,
3383 INDEX_OF (&(CardBus
->PciBusNumber
)),
3384 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3385 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3388 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3390 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3391 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3392 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3395 // Print CardBus Latency Timer
3397 ShellPrintHiiEx(-1, -1, NULL
,
3398 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3399 gShellDebug1HiiHandle
,
3400 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3401 CardBus
->CardBusLatencyTimer
3405 // Print Memory/Io ranges this cardbus bridge forwards
3407 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3408 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3410 ShellPrintHiiEx(-1, -1, NULL
,
3411 STRING_TOKEN (STR_PCI2_MEM_3
),
3412 gShellDebug1HiiHandle
,
3413 INDEX_OF (&(CardBus
->MemoryBase0
)),
3414 CardBus
->BridgeControl
& PCI_BIT_8
? L
" Prefetchable" : L
"Non-Prefetchable",
3415 CardBus
->MemoryBase0
& 0xfffff000,
3416 CardBus
->MemoryLimit0
| 0x00000fff
3419 ShellPrintHiiEx(-1, -1, NULL
,
3420 STRING_TOKEN (STR_PCI2_MEM_3
),
3421 gShellDebug1HiiHandle
,
3422 INDEX_OF (&(CardBus
->MemoryBase1
)),
3423 CardBus
->BridgeControl
& PCI_BIT_9
? L
" Prefetchable" : L
"Non-Prefetchable",
3424 CardBus
->MemoryBase1
& 0xfffff000,
3425 CardBus
->MemoryLimit1
| 0x00000fff
3428 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& PCI_BIT_0
);
3429 ShellPrintHiiEx(-1, -1, NULL
,
3430 STRING_TOKEN (STR_PCI2_IO_2
),
3431 gShellDebug1HiiHandle
,
3432 INDEX_OF (&(CardBus
->IoBase0
)),
3433 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3434 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3435 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3438 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& PCI_BIT_0
);
3439 ShellPrintHiiEx(-1, -1, NULL
,
3440 STRING_TOKEN (STR_PCI2_IO_2
),
3441 gShellDebug1HiiHandle
,
3442 INDEX_OF (&(CardBus
->IoBase1
)),
3443 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3444 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3445 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3449 // Print register Interrupt Line & PIN
3451 ShellPrintHiiEx(-1, -1, NULL
,
3452 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3453 gShellDebug1HiiHandle
,
3454 INDEX_OF (&(CardBus
->InterruptLine
)),
3455 CardBus
->InterruptLine
,
3456 INDEX_OF (&(CardBus
->InterruptPin
)),
3457 CardBus
->InterruptPin
3461 // Print register Bridge Control
3463 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3466 // Print some registers in data region of PCI configuration space for cardbus
3467 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3470 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_HEADER
));
3472 ShellPrintHiiEx(-1, -1, NULL
,
3473 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3474 gShellDebug1HiiHandle
,
3475 INDEX_OF (&(CardBusData
->SubVendorId
)),
3476 CardBusData
->SubVendorId
,
3477 INDEX_OF (&(CardBusData
->SubSystemId
)),
3478 CardBusData
->SubSystemId
3481 ShellPrintHiiEx(-1, -1, NULL
,
3482 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3483 gShellDebug1HiiHandle
,
3484 INDEX_OF (&(CardBusData
->LegacyBase
)),
3485 CardBusData
->LegacyBase
3492 Explain each meaningful bit of register Status. The definition of Status is
3493 slightly different depending on the PCI header type.
3495 @param[in] Status Points to the content of register Status.
3496 @param[in] MainStatus Indicates if this register is main status(not secondary
3498 @param[in] HeaderType Header type of this PCI device.
3500 @retval EFI_SUCCESS The command completed successfully.
3505 IN BOOLEAN MainStatus
,
3506 IN PCI_HEADER_TYPE HeaderType
3510 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3513 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3516 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_4
) != 0);
3519 // Bit 5 is meaningless for CardBus Bridge
3521 if (HeaderType
== PciCardBusBridge
) {
3522 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3525 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3528 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_7
) != 0);
3530 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_8
) != 0);
3532 // Bit 9 and bit 10 together decides the DEVSEL timing
3534 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3535 if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) == 0) {
3536 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3538 } else if ((*Status
& PCI_BIT_9
) != 0 && (*Status
& PCI_BIT_10
) == 0) {
3539 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3541 } else if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) != 0) {
3542 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3545 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3548 ShellPrintHiiEx(-1, -1, NULL
,
3549 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3550 gShellDebug1HiiHandle
,
3551 (*Status
& PCI_BIT_11
) != 0
3554 ShellPrintHiiEx(-1, -1, NULL
,
3555 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3556 gShellDebug1HiiHandle
,
3557 (*Status
& PCI_BIT_12
) != 0
3560 ShellPrintHiiEx(-1, -1, NULL
,
3561 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3562 gShellDebug1HiiHandle
,
3563 (*Status
& PCI_BIT_13
) != 0
3567 ShellPrintHiiEx(-1, -1, NULL
,
3568 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
3569 gShellDebug1HiiHandle
,
3570 (*Status
& PCI_BIT_14
) != 0
3574 ShellPrintHiiEx(-1, -1, NULL
,
3575 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
3576 gShellDebug1HiiHandle
,
3577 (*Status
& PCI_BIT_14
) != 0
3581 ShellPrintHiiEx(-1, -1, NULL
,
3582 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
3583 gShellDebug1HiiHandle
,
3584 (*Status
& PCI_BIT_15
) != 0
3591 Explain each meaningful bit of register Command.
3593 @param[in] Command Points to the content of register Command.
3595 @retval EFI_SUCCESS The command completed successfully.
3603 // Print the binary value of register Command
3605 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
3608 // Explain register Command bit by bit
3610 ShellPrintHiiEx(-1, -1, NULL
,
3611 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
3612 gShellDebug1HiiHandle
,
3613 (*Command
& PCI_BIT_0
) != 0
3616 ShellPrintHiiEx(-1, -1, NULL
,
3617 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
3618 gShellDebug1HiiHandle
,
3619 (*Command
& PCI_BIT_1
) != 0
3622 ShellPrintHiiEx(-1, -1, NULL
,
3623 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
3624 gShellDebug1HiiHandle
,
3625 (*Command
& PCI_BIT_2
) != 0
3628 ShellPrintHiiEx(-1, -1, NULL
,
3629 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
3630 gShellDebug1HiiHandle
,
3631 (*Command
& PCI_BIT_3
) != 0
3634 ShellPrintHiiEx(-1, -1, NULL
,
3635 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
3636 gShellDebug1HiiHandle
,
3637 (*Command
& PCI_BIT_4
) != 0
3640 ShellPrintHiiEx(-1, -1, NULL
,
3641 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
3642 gShellDebug1HiiHandle
,
3643 (*Command
& PCI_BIT_5
) != 0
3646 ShellPrintHiiEx(-1, -1, NULL
,
3647 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
3648 gShellDebug1HiiHandle
,
3649 (*Command
& PCI_BIT_6
) != 0
3652 ShellPrintHiiEx(-1, -1, NULL
,
3653 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
3654 gShellDebug1HiiHandle
,
3655 (*Command
& PCI_BIT_7
) != 0
3658 ShellPrintHiiEx(-1, -1, NULL
,
3659 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
3660 gShellDebug1HiiHandle
,
3661 (*Command
& PCI_BIT_8
) != 0
3664 ShellPrintHiiEx(-1, -1, NULL
,
3665 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
3666 gShellDebug1HiiHandle
,
3667 (*Command
& PCI_BIT_9
) != 0
3674 Explain each meaningful bit of register Bridge Control.
3676 @param[in] BridgeControl Points to the content of register Bridge Control.
3677 @param[in] HeaderType The headertype.
3679 @retval EFI_SUCCESS The command completed successfully.
3682 PciExplainBridgeControl (
3683 IN UINT16
*BridgeControl
,
3684 IN PCI_HEADER_TYPE HeaderType
3687 ShellPrintHiiEx(-1, -1, NULL
,
3688 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
3689 gShellDebug1HiiHandle
,
3690 INDEX_OF (BridgeControl
),
3694 ShellPrintHiiEx(-1, -1, NULL
,
3695 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
3696 gShellDebug1HiiHandle
,
3697 (*BridgeControl
& PCI_BIT_0
) != 0
3699 ShellPrintHiiEx(-1, -1, NULL
,
3700 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
3701 gShellDebug1HiiHandle
,
3702 (*BridgeControl
& PCI_BIT_1
) != 0
3704 ShellPrintHiiEx(-1, -1, NULL
,
3705 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
3706 gShellDebug1HiiHandle
,
3707 (*BridgeControl
& PCI_BIT_2
) != 0
3709 ShellPrintHiiEx(-1, -1, NULL
,
3710 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
3711 gShellDebug1HiiHandle
,
3712 (*BridgeControl
& PCI_BIT_3
) != 0
3714 ShellPrintHiiEx(-1, -1, NULL
,
3715 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
3716 gShellDebug1HiiHandle
,
3717 (*BridgeControl
& PCI_BIT_5
) != 0
3721 // Register Bridge Control has some slight differences between P2P bridge
3722 // and Cardbus bridge from bit 6 to bit 11.
3724 if (HeaderType
== PciP2pBridge
) {
3725 ShellPrintHiiEx(-1, -1, NULL
,
3726 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
3727 gShellDebug1HiiHandle
,
3728 (*BridgeControl
& PCI_BIT_6
) != 0
3730 ShellPrintHiiEx(-1, -1, NULL
,
3731 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
3732 gShellDebug1HiiHandle
,
3733 (*BridgeControl
& PCI_BIT_7
) != 0
3735 ShellPrintHiiEx(-1, -1, NULL
,
3736 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
3737 gShellDebug1HiiHandle
,
3738 (*BridgeControl
& PCI_BIT_8
)!=0 ? L
"2^10" : L
"2^15"
3740 ShellPrintHiiEx(-1, -1, NULL
,
3741 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
3742 gShellDebug1HiiHandle
,
3743 (*BridgeControl
& PCI_BIT_9
)!=0 ? L
"2^10" : L
"2^15"
3745 ShellPrintHiiEx(-1, -1, NULL
,
3746 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
3747 gShellDebug1HiiHandle
,
3748 (*BridgeControl
& PCI_BIT_10
) != 0
3750 ShellPrintHiiEx(-1, -1, NULL
,
3751 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
3752 gShellDebug1HiiHandle
,
3753 (*BridgeControl
& PCI_BIT_11
) != 0
3757 ShellPrintHiiEx(-1, -1, NULL
,
3758 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
3759 gShellDebug1HiiHandle
,
3760 (*BridgeControl
& PCI_BIT_6
) != 0
3762 ShellPrintHiiEx(-1, -1, NULL
,
3763 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
3764 gShellDebug1HiiHandle
,
3765 (*BridgeControl
& PCI_BIT_7
) != 0
3767 ShellPrintHiiEx(-1, -1, NULL
,
3768 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
3769 gShellDebug1HiiHandle
,
3770 (*BridgeControl
& PCI_BIT_10
) != 0
3778 Print each capability structure.
3780 @param[in] IoDev The pointer to the deivce.
3781 @param[in] Address The address to start at.
3782 @param[in] CapPtr The offset from the address.
3784 @retval EFI_SUCCESS The operation was successful.
3787 PciExplainCapabilityStruct (
3788 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3793 UINT8 CapabilityPtr
;
3794 UINT16 CapabilityEntry
;
3798 CapabilityPtr
= CapPtr
;
3801 // Go through the Capability list
3803 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
3804 RegAddress
= Address
+ CapabilityPtr
;
3805 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
3807 CapabilityID
= (UINT8
) CapabilityEntry
;
3810 // Explain PciExpress data
3812 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
3813 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
);
3817 // Explain other capabilities here
3819 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
3826 Print out information of the capability information.
3828 @param[in] PciExpressCap The pointer to the structure about the device.
3830 @retval EFI_SUCCESS The operation was successful.
3834 IN PCIE_CAP_STURCTURE
*PciExpressCap
3838 CHAR16
*DevicePortType
;
3840 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3841 ShellPrintEx (-1, -1,
3842 L
" Capability Version(3:0): %E0x%04x%N\r\n",
3843 PCIE_CAP_VERSION (PcieCapReg
)
3845 if ((UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) < PCIE_DEVICE_PORT_TYPE_MAX
) {
3846 DevicePortType
= DevicePortTypeTable
[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
)];
3848 DevicePortType
= L
"Unknown Type";
3850 ShellPrintEx (-1, -1,
3851 L
" Device/PortType(7:4): %E%s%N\r\n",
3855 // 'Slot Implemented' is only valid for:
3856 // a) Root Port of PCI Express Root Complex, or
3857 // b) Downstream Port of PCI Express Switch
3859 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_ROOT_COMPLEX_ROOT_PORT
||
3860 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_SWITCH_DOWNSTREAM_PORT
) {
3861 ShellPrintEx (-1, -1,
3862 L
" Slot Implemented(8): %E%d%N\r\n",
3863 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg
)
3866 ShellPrintEx (-1, -1,
3867 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
3868 PCIE_CAP_INT_MSG_NUM (PcieCapReg
)
3874 Print out information of the device capability information.
3876 @param[in] PciExpressCap The pointer to the structure about the device.
3878 @retval EFI_SUCCESS The operation was successful.
3881 ExplainPcieDeviceCap (
3882 IN PCIE_CAP_STURCTURE
*PciExpressCap
3886 UINT32 PcieDeviceCap
;
3887 UINT8 DevicePortType
;
3891 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3892 PcieDeviceCap
= PciExpressCap
->PcieDeviceCap
;
3893 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
);
3894 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
3895 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) < 6) {
3896 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) + 7));
3898 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
3900 ShellPrintEx (-1, -1,
3901 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
3902 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap
)
3904 ShellPrintEx (-1, -1,
3905 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
3906 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap
) ? 8 : 5
3909 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
3911 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3912 L0sLatency
= (UINT8
) PCIE_CAP_L0SLATENCY (PcieDeviceCap
);
3913 L1Latency
= (UINT8
) PCIE_CAP_L1LATENCY (PcieDeviceCap
);
3914 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
3915 if (L0sLatency
< 4) {
3916 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
3918 if (L0sLatency
< 7) {
3919 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
3921 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
3924 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
3925 if (L1Latency
< 7) {
3926 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
3928 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
3931 ShellPrintEx (-1, -1,
3932 L
" Role-based Error Reporting(15): %E%d%N\r\n",
3933 PCIE_CAP_ERR_REPORTING (PcieDeviceCap
)
3936 // Only valid for Upstream Port:
3937 // a) Captured Slot Power Limit Value
3938 // b) Captured Slot Power Scale
3940 if (DevicePortType
== PCIE_SWITCH_UPSTREAM_PORT
) {
3941 ShellPrintEx (-1, -1,
3942 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
3943 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap
)
3945 ShellPrintEx (-1, -1,
3946 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
3947 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap
)]
3951 // Function Level Reset Capability is only valid for Endpoint
3953 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3954 ShellPrintEx (-1, -1,
3955 L
" Function Level Reset Capability(28): %E%d%N\r\n",
3956 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap
)
3963 Print out information of the device control information.
3965 @param[in] PciExpressCap The pointer to the structure about the device.
3967 @retval EFI_SUCCESS The operation was successful.
3970 ExplainPcieDeviceControl (
3971 IN PCIE_CAP_STURCTURE
*PciExpressCap
3975 UINT16 PcieDeviceControl
;
3977 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3978 PcieDeviceControl
= PciExpressCap
->DeviceControl
;
3979 ShellPrintEx (-1, -1,
3980 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
3981 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3983 ShellPrintEx (-1, -1,
3984 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
3985 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3987 ShellPrintEx (-1, -1,
3988 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
3989 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3991 ShellPrintEx (-1, -1,
3992 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
3993 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl
)
3995 ShellPrintEx (-1, -1,
3996 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
3997 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl
)
3999 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4000 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) < 6) {
4001 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) + 7));
4003 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4005 ShellPrintEx (-1, -1,
4006 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4007 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl
)
4009 ShellPrintEx (-1, -1,
4010 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4011 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl
)
4013 ShellPrintEx (-1, -1,
4014 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4015 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl
)
4017 ShellPrintEx (-1, -1,
4018 L
" Enable No Snoop(11): %E%d%N\r\n",
4019 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl
)
4021 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4022 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) < 6) {
4023 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) + 7));
4025 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4028 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4030 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_PCIE_TO_PCIX_BRIDGE
) {
4031 ShellPrintEx (-1, -1,
4032 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4033 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl
)
4040 Print out information of the device status information.
4042 @param[in] PciExpressCap The pointer to the structure about the device.
4044 @retval EFI_SUCCESS The operation was successful.
4047 ExplainPcieDeviceStatus (
4048 IN PCIE_CAP_STURCTURE
*PciExpressCap
4051 UINT16 PcieDeviceStatus
;
4053 PcieDeviceStatus
= PciExpressCap
->DeviceStatus
;
4054 ShellPrintEx (-1, -1,
4055 L
" Correctable Error Detected(0): %E%d%N\r\n",
4056 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus
)
4058 ShellPrintEx (-1, -1,
4059 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4060 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus
)
4062 ShellPrintEx (-1, -1,
4063 L
" Fatal Error Detected(2): %E%d%N\r\n",
4064 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus
)
4066 ShellPrintEx (-1, -1,
4067 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4068 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus
)
4070 ShellPrintEx (-1, -1,
4071 L
" AUX Power Detected(4): %E%d%N\r\n",
4072 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus
)
4074 ShellPrintEx (-1, -1,
4075 L
" Transactions Pending(5): %E%d%N\r\n",
4076 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus
)
4082 Print out information of the device link information.
4084 @param[in] PciExpressCap The pointer to the structure about the device.
4086 @retval EFI_SUCCESS The operation was successful.
4089 ExplainPcieLinkCap (
4090 IN PCIE_CAP_STURCTURE
*PciExpressCap
4094 CHAR16
*MaxLinkSpeed
;
4097 PcieLinkCap
= PciExpressCap
->LinkCap
;
4098 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap
)) {
4100 MaxLinkSpeed
= L
"2.5 GT/s";
4103 MaxLinkSpeed
= L
"5.0 GT/s";
4106 MaxLinkSpeed
= L
"8.0 GT/s";
4109 MaxLinkSpeed
= L
"Unknown";
4112 ShellPrintEx (-1, -1,
4113 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4116 ShellPrintEx (-1, -1,
4117 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4118 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap
)
4120 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap
)) {
4131 AspmValue
= L
"L0s and L1";
4134 AspmValue
= L
"Reserved";
4137 ShellPrintEx (-1, -1,
4138 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4141 ShellPrintEx (-1, -1,
4142 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4143 L0sLatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4145 ShellPrintEx (-1, -1,
4146 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4147 L1LatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4149 ShellPrintEx (-1, -1,
4150 L
" Clock Power Management(18): %E%d%N\r\n",
4151 PCIE_CAP_CLOCK_PM (PcieLinkCap
)
4153 ShellPrintEx (-1, -1,
4154 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4155 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap
)
4157 ShellPrintEx (-1, -1,
4158 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4159 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap
)
4161 ShellPrintEx (-1, -1,
4162 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4163 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap
)
4165 ShellPrintEx (-1, -1,
4166 L
" Port Number(31:24): %E0x%02x%N\r\n",
4167 PCIE_CAP_PORT_NUMBER (PcieLinkCap
)
4173 Print out information of the device link control information.
4175 @param[in] PciExpressCap The pointer to the structure about the device.
4177 @retval EFI_SUCCESS The operation was successful.
4180 ExplainPcieLinkControl (
4181 IN PCIE_CAP_STURCTURE
*PciExpressCap
4184 UINT16 PcieLinkControl
;
4185 UINT8 DevicePortType
;
4187 PcieLinkControl
= PciExpressCap
->LinkControl
;
4188 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
->PcieCapReg
);
4189 ShellPrintEx (-1, -1,
4190 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4191 ASPMCtrlStrTable
[PCIE_CAP_ASPM_CONTROL (PcieLinkControl
)]
4194 // RCB is not applicable to switches
4196 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4197 ShellPrintEx (-1, -1,
4198 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4199 1 << (PCIE_CAP_RCB (PcieLinkControl
) + 6)
4203 // Link Disable is reserved on
4205 // b) PCI Express to PCI/PCI-X bridges
4206 // c) Upstream Ports of Switches
4208 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4209 DevicePortType
!= PCIE_SWITCH_UPSTREAM_PORT
&&
4210 DevicePortType
!= PCIE_PCIE_TO_PCIX_BRIDGE
) {
4211 ShellPrintEx (-1, -1,
4212 L
" Link Disable(4): %E%d%N\r\n",
4213 PCIE_CAP_LINK_DISABLE (PcieLinkControl
)
4216 ShellPrintEx (-1, -1,
4217 L
" Common Clock Configuration(6): %E%d%N\r\n",
4218 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl
)
4220 ShellPrintEx (-1, -1,
4221 L
" Extended Synch(7): %E%d%N\r\n",
4222 PCIE_CAP_EXT_SYNC (PcieLinkControl
)
4224 ShellPrintEx (-1, -1,
4225 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4226 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl
)
4228 ShellPrintEx (-1, -1,
4229 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4230 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl
)
4232 ShellPrintEx (-1, -1,
4233 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4234 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl
)
4236 ShellPrintEx (-1, -1,
4237 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4238 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl
)
4244 Print out information of the device link status information.
4246 @param[in] PciExpressCap The pointer to the structure about the device.
4248 @retval EFI_SUCCESS The operation was successful.
4251 ExplainPcieLinkStatus (
4252 IN PCIE_CAP_STURCTURE
*PciExpressCap
4255 UINT16 PcieLinkStatus
;
4256 CHAR16
*CurLinkSpeed
;
4258 PcieLinkStatus
= PciExpressCap
->LinkStatus
;
4259 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus
)) {
4261 CurLinkSpeed
= L
"2.5 GT/s";
4264 CurLinkSpeed
= L
"5.0 GT/s";
4267 CurLinkSpeed
= L
"8.0 GT/s";
4270 CurLinkSpeed
= L
"Reserved";
4273 ShellPrintEx (-1, -1,
4274 L
" Current Link Speed(3:0): %E%s%N\r\n",
4277 ShellPrintEx (-1, -1,
4278 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
4279 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus
)
4281 ShellPrintEx (-1, -1,
4282 L
" Link Training(11): %E%d%N\r\n",
4283 PCIE_CAP_LINK_TRAINING (PcieLinkStatus
)
4285 ShellPrintEx (-1, -1,
4286 L
" Slot Clock Configuration(12): %E%d%N\r\n",
4287 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus
)
4289 ShellPrintEx (-1, -1,
4290 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
4291 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus
)
4293 ShellPrintEx (-1, -1,
4294 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
4295 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus
)
4297 ShellPrintEx (-1, -1,
4298 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
4299 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus
)
4305 Print out information of the device slot information.
4307 @param[in] PciExpressCap The pointer to the structure about the device.
4309 @retval EFI_SUCCESS The operation was successful.
4312 ExplainPcieSlotCap (
4313 IN PCIE_CAP_STURCTURE
*PciExpressCap
4318 PcieSlotCap
= PciExpressCap
->SlotCap
;
4320 ShellPrintEx (-1, -1,
4321 L
" Attention Button Present(0): %E%d%N\r\n",
4322 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap
)
4324 ShellPrintEx (-1, -1,
4325 L
" Power Controller Present(1): %E%d%N\r\n",
4326 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap
)
4328 ShellPrintEx (-1, -1,
4329 L
" MRL Sensor Present(2): %E%d%N\r\n",
4330 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap
)
4332 ShellPrintEx (-1, -1,
4333 L
" Attention Indicator Present(3): %E%d%N\r\n",
4334 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap
)
4336 ShellPrintEx (-1, -1,
4337 L
" Power Indicator Present(4): %E%d%N\r\n",
4338 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap
)
4340 ShellPrintEx (-1, -1,
4341 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
4342 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap
)
4344 ShellPrintEx (-1, -1,
4345 L
" Hot-Plug Capable(6): %E%d%N\r\n",
4346 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap
)
4348 ShellPrintEx (-1, -1,
4349 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
4350 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap
)
4352 ShellPrintEx (-1, -1,
4353 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
4354 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap
)]
4356 ShellPrintEx (-1, -1,
4357 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
4358 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap
)
4360 ShellPrintEx (-1, -1,
4361 L
" No Command Completed Support(18): %E%d%N\r\n",
4362 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap
)
4364 ShellPrintEx (-1, -1,
4365 L
" Physical Slot Number(31:19): %E%d%N\r\n",
4366 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap
)
4373 Print out information of the device slot control information.
4375 @param[in] PciExpressCap The pointer to the structure about the device.
4377 @retval EFI_SUCCESS The operation was successful.
4380 ExplainPcieSlotControl (
4381 IN PCIE_CAP_STURCTURE
*PciExpressCap
4384 UINT16 PcieSlotControl
;
4386 PcieSlotControl
= PciExpressCap
->SlotControl
;
4387 ShellPrintEx (-1, -1,
4388 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
4389 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl
)
4391 ShellPrintEx (-1, -1,
4392 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
4393 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl
)
4395 ShellPrintEx (-1, -1,
4396 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
4397 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl
)
4399 ShellPrintEx (-1, -1,
4400 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
4401 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl
)
4403 ShellPrintEx (-1, -1,
4404 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
4405 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl
)
4407 ShellPrintEx (-1, -1,
4408 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
4409 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl
)
4411 ShellPrintEx (-1, -1,
4412 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
4413 IndicatorTable
[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl
)]
4415 ShellPrintEx (-1, -1,
4416 L
" Power Indicator Control(9:8): %E%s%N\r\n",
4417 IndicatorTable
[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl
)]
4419 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
4420 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl
)) {
4421 ShellPrintEx (-1, -1, L
"Off%N\r\n");
4423 ShellPrintEx (-1, -1, L
"On%N\r\n");
4425 ShellPrintEx (-1, -1,
4426 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
4427 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl
)
4429 ShellPrintEx (-1, -1,
4430 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
4431 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl
)
4437 Print out information of the device slot status information.
4439 @param[in] PciExpressCap The pointer to the structure about the device.
4441 @retval EFI_SUCCESS The operation was successful.
4444 ExplainPcieSlotStatus (
4445 IN PCIE_CAP_STURCTURE
*PciExpressCap
4448 UINT16 PcieSlotStatus
;
4450 PcieSlotStatus
= PciExpressCap
->SlotStatus
;
4452 ShellPrintEx (-1, -1,
4453 L
" Attention Button Pressed(0): %E%d%N\r\n",
4454 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus
)
4456 ShellPrintEx (-1, -1,
4457 L
" Power Fault Detected(1): %E%d%N\r\n",
4458 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus
)
4460 ShellPrintEx (-1, -1,
4461 L
" MRL Sensor Changed(2): %E%d%N\r\n",
4462 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus
)
4464 ShellPrintEx (-1, -1,
4465 L
" Presence Detect Changed(3): %E%d%N\r\n",
4466 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus
)
4468 ShellPrintEx (-1, -1,
4469 L
" Command Completed(4): %E%d%N\r\n",
4470 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus
)
4472 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
4473 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus
)) {
4474 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
4476 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
4478 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
4479 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus
)) {
4480 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
4482 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
4484 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4485 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus
)) {
4486 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
4488 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
4490 ShellPrintEx (-1, -1,
4491 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
4492 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus
)
4498 Print out information of the device root information.
4500 @param[in] PciExpressCap The pointer to the structure about the device.
4502 @retval EFI_SUCCESS The operation was successful.
4505 ExplainPcieRootControl (
4506 IN PCIE_CAP_STURCTURE
*PciExpressCap
4509 UINT16 PcieRootControl
;
4511 PcieRootControl
= PciExpressCap
->RootControl
;
4513 ShellPrintEx (-1, -1,
4514 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
4515 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl
)
4517 ShellPrintEx (-1, -1,
4518 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
4519 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl
)
4521 ShellPrintEx (-1, -1,
4522 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
4523 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl
)
4525 ShellPrintEx (-1, -1,
4526 L
" PME Interrupt Enable(3): %E%d%N\r\n",
4527 PCIE_CAP_PME_INT_ENABLE (PcieRootControl
)
4529 ShellPrintEx (-1, -1,
4530 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
4531 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl
)
4538 Print out information of the device root capability information.
4540 @param[in] PciExpressCap The pointer to the structure about the device.
4542 @retval EFI_SUCCESS The operation was successful.
4545 ExplainPcieRootCap (
4546 IN PCIE_CAP_STURCTURE
*PciExpressCap
4551 PcieRootCap
= PciExpressCap
->RsvdP
;
4553 ShellPrintEx (-1, -1,
4554 L
" CRS Software Visibility(0): %E%d%N\r\n",
4555 PCIE_CAP_CRS_SW_VIS (PcieRootCap
)
4562 Print out information of the device root status information.
4564 @param[in] PciExpressCap The pointer to the structure about the device.
4566 @retval EFI_SUCCESS The operation was successful.
4569 ExplainPcieRootStatus (
4570 IN PCIE_CAP_STURCTURE
*PciExpressCap
4573 UINT32 PcieRootStatus
;
4575 PcieRootStatus
= PciExpressCap
->RootStatus
;
4577 ShellPrintEx (-1, -1,
4578 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
4579 PCIE_CAP_PME_REQ_ID (PcieRootStatus
)
4581 ShellPrintEx (-1, -1,
4582 L
" PME Status(16): %E%d%N\r\n",
4583 PCIE_CAP_PME_STATUS (PcieRootStatus
)
4585 ShellPrintEx (-1, -1,
4586 L
" PME Pending(17): %E%d%N\r\n",
4587 PCIE_CAP_PME_PENDING (PcieRootStatus
)
4593 Display Pcie device structure.
4595 @param[in] IoDev The pointer to the root pci protocol.
4596 @param[in] Address The Address to start at.
4597 @param[in] CapabilityPtr The offset from the address to start.
4600 PciExplainPciExpress (
4601 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
4603 IN UINT8 CapabilityPtr
4607 PCIE_CAP_STURCTURE PciExpressCap
;
4609 UINT64 CapRegAddress
;
4614 UINTN ExtendRegSize
;
4615 UINT64 Pciex_Address
;
4616 UINT8 DevicePortType
;
4621 CapRegAddress
= Address
+ CapabilityPtr
;
4626 sizeof (PciExpressCap
) / sizeof (UINT32
),
4630 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
.PcieCapReg
);
4632 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
4634 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
4635 if (ShellGetExecutionBreakFlag()) {
4638 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
4639 switch (PcieExplainList
[Index
].Width
) {
4640 case FieldWidthUINT8
:
4641 RegValue
= *(UINT8
*) RegAddr
;
4643 case FieldWidthUINT16
:
4644 RegValue
= *(UINT16
*) RegAddr
;
4646 case FieldWidthUINT32
:
4647 RegValue
= *(UINT32
*) RegAddr
;
4653 ShellPrintHiiEx(-1, -1, NULL
,
4654 PcieExplainList
[Index
].Token
,
4655 gShellDebug1HiiHandle
,
4656 PcieExplainList
[Index
].Offset
,
4659 if (PcieExplainList
[Index
].Func
== NULL
) {
4662 switch (PcieExplainList
[Index
].Type
) {
4663 case PcieExplainTypeLink
:
4665 // Link registers should not be used by
4666 // a) Root Complex Integrated Endpoint
4667 // b) Root Complex Event Collector
4669 if (DevicePortType
== PCIE_ROOT_COMPLEX_INTEGRATED_PORT
||
4670 DevicePortType
== PCIE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
4674 case PcieExplainTypeSlot
:
4676 // Slot registers are only valid for
4677 // a) Root Port of PCI Express Root Complex
4678 // b) Downstream Port of PCI Express Switch
4679 // and when SlotImplemented bit is set in PCIE cap register.
4681 if ((DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
&&
4682 DevicePortType
!= PCIE_SWITCH_DOWNSTREAM_PORT
) ||
4683 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap
.PcieCapReg
)) {
4687 case PcieExplainTypeRoot
:
4689 // Root registers are only valid for
4690 // Root Port of PCI Express Root Complex
4692 if (DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
) {
4699 PcieExplainList
[Index
].Func (&PciExpressCap
);
4702 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
4703 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
4704 Func
= (UINT8
) (RShiftU64 (Address
, 8));
4706 Pciex_Address
= CALC_EFI_PCIEX_ADDRESS (Bus
, Dev
, Func
, 0x100);
4708 ExtendRegSize
= 0x1000 - 0x100;
4710 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
4713 // PciRootBridgeIo protocol should support pci express extend space IO
4714 // (Begins at offset 0x100)
4716 Status
= IoDev
->Pci
.Read (
4720 (ExtendRegSize
) / sizeof (UINT32
),
4721 (VOID
*) (ExRegBuffer
)
4723 if (EFI_ERROR (Status
)) {
4724 FreePool ((VOID
*) ExRegBuffer
);
4725 return EFI_UNSUPPORTED
;
4728 // Start outputing PciEx extend space( 0xFF-0xFFF)
4730 ShellPrintEx (-1, -1, L
"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
4732 if (ExRegBuffer
!= NULL
) {
4737 (VOID
*) (ExRegBuffer
)
4740 FreePool ((VOID
*) ExRegBuffer
);