2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "UefiShellDebug1CommandsLib.h"
16 #include <Protocol/PciRootBridgeIo.h>
17 #include <Library/ShellLib.h>
18 #include <IndustryStandard/Pci.h>
19 #include <IndustryStandard/Acpi.h>
22 #define PCI_CLASS_STRING_LIMIT 54
24 // Printable strings for Pci class code
27 CHAR16
*BaseClass
; // Pointer to the PCI base class string
28 CHAR16
*SubClass
; // Pointer to the PCI sub class string
29 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
33 // a structure holding a single entry, which also points to its lower level
36 typedef struct PCI_CLASS_ENTRY_TAG
{
37 UINT8 Code
; // Class, subclass or I/F code
38 CHAR16
*DescText
; // Description string
39 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
43 // Declarations of entries which contain printable strings for class codes
44 // in PCI configuration space
46 PCI_CLASS_ENTRY PCIBlankEntry
[];
47 PCI_CLASS_ENTRY PCISubClass_00
[];
48 PCI_CLASS_ENTRY PCISubClass_01
[];
49 PCI_CLASS_ENTRY PCISubClass_02
[];
50 PCI_CLASS_ENTRY PCISubClass_03
[];
51 PCI_CLASS_ENTRY PCISubClass_04
[];
52 PCI_CLASS_ENTRY PCISubClass_05
[];
53 PCI_CLASS_ENTRY PCISubClass_06
[];
54 PCI_CLASS_ENTRY PCISubClass_07
[];
55 PCI_CLASS_ENTRY PCISubClass_08
[];
56 PCI_CLASS_ENTRY PCISubClass_09
[];
57 PCI_CLASS_ENTRY PCISubClass_0a
[];
58 PCI_CLASS_ENTRY PCISubClass_0b
[];
59 PCI_CLASS_ENTRY PCISubClass_0c
[];
60 PCI_CLASS_ENTRY PCISubClass_0d
[];
61 PCI_CLASS_ENTRY PCISubClass_0e
[];
62 PCI_CLASS_ENTRY PCISubClass_0f
[];
63 PCI_CLASS_ENTRY PCISubClass_10
[];
64 PCI_CLASS_ENTRY PCISubClass_11
[];
65 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
66 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
81 // Base class strings entries
83 PCI_CLASS_ENTRY gClassStringList
[] = {
91 L
"Mass Storage Controller",
96 L
"Network Controller",
101 L
"Display Controller",
106 L
"Multimedia Device",
111 L
"Memory Controller",
121 L
"Simple Communications Controllers",
126 L
"Base System Peripherals",
146 L
"Serial Bus Controllers",
151 L
"Wireless Controllers",
156 L
"Intelligent IO Controllers",
161 L
"Satellite Communications Controllers",
166 L
"Encryption/Decryption Controllers",
171 L
"Data Acquisition & Signal Processing Controllers",
176 L
"Device does not fit in any defined classes",
182 /* null string ends the list */NULL
187 // Subclass strings entries
189 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
198 /* null string ends the list */NULL
202 PCI_CLASS_ENTRY PCISubClass_00
[] = {
205 L
"All devices other than VGA",
210 L
"VGA-compatible devices",
216 /* null string ends the list */NULL
220 PCI_CLASS_ENTRY PCISubClass_01
[] = {
233 L
"Floppy disk controller",
248 L
"Other mass storage controller",
254 /* null string ends the list */NULL
258 PCI_CLASS_ENTRY PCISubClass_02
[] = {
261 L
"Ethernet controller",
266 L
"Token ring controller",
286 L
"Other network controller",
292 /* null string ends the list */NULL
296 PCI_CLASS_ENTRY PCISubClass_03
[] = {
299 L
"VGA/8514 controller",
314 L
"Other display controller",
320 /* null string ends the list */PCIBlankEntry
324 PCI_CLASS_ENTRY PCISubClass_04
[] = {
337 L
"Computer Telephony device",
342 L
"Other multimedia device",
348 /* null string ends the list */NULL
352 PCI_CLASS_ENTRY PCISubClass_05
[] = {
355 L
"RAM memory controller",
360 L
"Flash memory controller",
365 L
"Other memory controller",
371 /* null string ends the list */NULL
375 PCI_CLASS_ENTRY PCISubClass_06
[] = {
393 L
"PCI/Micro Channel bridge",
403 L
"PCI/PCMCIA bridge",
423 L
"Other bridge type",
429 /* null string ends the list */NULL
433 PCI_CLASS_ENTRY PCISubClass_07
[] = {
436 L
"Serial controller",
446 L
"Multiport serial controller",
456 L
"Other communication device",
462 /* null string ends the list */NULL
466 PCI_CLASS_ENTRY PCISubClass_08
[] = {
489 L
"Generic PCI Hot-Plug controller",
494 L
"Other system peripheral",
500 /* null string ends the list */NULL
504 PCI_CLASS_ENTRY PCISubClass_09
[] = {
507 L
"Keyboard controller",
522 L
"Scanner controller",
527 L
"Gameport controller",
532 L
"Other input controller",
538 /* null string ends the list */NULL
542 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
545 L
"Generic docking station",
550 L
"Other type of docking station",
556 /* null string ends the list */NULL
560 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
604 /* null string ends the list */NULL
608 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
611 L
"Firewire(IEEE 1394)",
636 L
"System Management Bus",
647 /* null string ends the list */NULL
651 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
654 L
"iRDA compatible controller",
659 L
"Consumer IR controller",
669 L
"Other type of wireless controller",
675 /* null string ends the list */NULL
679 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
688 /* null string ends the list */NULL
692 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
716 /* null string ends the list */NULL
720 PCI_CLASS_ENTRY PCISubClass_10
[] = {
723 L
"Network & computing Encrypt/Decrypt",
728 L
"Entertainment Encrypt/Decrypt",
733 L
"Other Encrypt/Decrypt",
739 /* null string ends the list */NULL
743 PCI_CLASS_ENTRY PCISubClass_11
[] = {
751 L
"Other DAQ & SP controllers",
757 /* null string ends the list */NULL
762 // Programming Interface entries
764 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
792 L
"OM-primary, OM-secondary",
797 L
"PI-primary, OM-secondary",
802 L
"OM/PI-primary, OM-secondary",
812 L
"OM-primary, PI-secondary",
817 L
"PI-primary, PI-secondary",
822 L
"OM/PI-primary, PI-secondary",
832 L
"OM-primary, OM/PI-secondary",
837 L
"PI-primary, OM/PI-secondary",
842 L
"OM/PI-primary, OM/PI-secondary",
852 L
"Master, OM-primary",
857 L
"Master, PI-primary",
862 L
"Master, OM/PI-primary",
867 L
"Master, OM-secondary",
872 L
"Master, OM-primary, OM-secondary",
877 L
"Master, PI-primary, OM-secondary",
882 L
"Master, OM/PI-primary, OM-secondary",
887 L
"Master, OM-secondary",
892 L
"Master, OM-primary, PI-secondary",
897 L
"Master, PI-primary, PI-secondary",
902 L
"Master, OM/PI-primary, PI-secondary",
907 L
"Master, OM-secondary",
912 L
"Master, OM-primary, OM/PI-secondary",
917 L
"Master, PI-primary, OM/PI-secondary",
922 L
"Master, OM/PI-primary, OM/PI-secondary",
928 /* null string ends the list */NULL
932 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
946 /* null string ends the list */NULL
950 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
958 L
"Subtractive decode",
964 /* null string ends the list */NULL
968 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
971 L
"Generic XT-compatible",
1001 L
"16950-compatible",
1007 /* null string ends the list */NULL
1011 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1024 L
"ECP 1.X-compliant",
1034 L
"IEEE 1284 target (not a controller)",
1040 /* null string ends the list */NULL
1044 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1052 L
"Hayes-compatible 16450",
1057 L
"Hayes-compatible 16550",
1062 L
"Hayes-compatible 16650",
1067 L
"Hayes-compatible 16750",
1073 /* null string ends the list */NULL
1077 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1100 L
"IO(x) APIC interrupt controller",
1106 /* null string ends the list */NULL
1110 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1129 /* null string ends the list */NULL
1133 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1152 /* null string ends the list */NULL
1156 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1175 /* null string ends the list */NULL
1179 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1193 /* null string ends the list */NULL
1197 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1200 L
"Universal Host Controller spec",
1205 L
"Open Host Controller spec",
1210 L
"No specific programming interface",
1215 L
"(Not Host Controller)",
1221 /* null string ends the list */NULL
1225 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1233 L
"Using 1394 OpenHCI spec",
1239 /* null string ends the list */NULL
1243 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1246 L
"Message FIFO at offset 40h",
1257 /* null string ends the list */NULL
1261 #define EFI_HEX_DISP_SIZE 32
1271 Routine Description:
1273 Add page break feature to the DumpHex
1276 Indent - The indent space
1280 DataSize - The data size
1286 TRUE - The dump is broke
1287 FALSE - The dump is completed
1294 DispSize
= EFI_HEX_DISP_SIZE
;
1295 DispData
= (UINT8
*) UserData
;
1297 while (DataSize
!=0) {
1298 if (ShellGetExecutionBreakFlag ()) {
1302 if (DataSize
> EFI_HEX_DISP_SIZE
) {
1303 DataSize
-= EFI_HEX_DISP_SIZE
;
1305 DispSize
= DataSize
;
1309 DumpHex (Indent
, Offset
+ DispData
- (UINT8
*) UserData
, DispSize
, DispData
);
1310 DispData
+= DispSize
;
1320 PciGetClassStrings (
1321 IN UINT32 ClassCode
,
1322 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1325 Routine Description:
1327 Generates printable Unicode strings that represent PCI device class,
1328 subclass and programmed I/F based on a value passed to the function.
1332 ClassCode Value representing the PCI "Class Code" register read from a
1333 PCI device. The encodings are:
1334 bits 23:16 - Base Class Code
1335 bits 15:8 - Sub-Class Code
1336 bits 7:0 - Programming Interface
1337 ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1338 printable class strings corresponding to ClassCode. The
1339 caller must not modify the strings that are pointed by
1340 the fields in ClassStrings.
1348 PCI_CLASS_ENTRY
*CurrentClass
;
1351 // Assume no strings found
1353 ClassStrings
->BaseClass
= L
"UNDEFINED";
1354 ClassStrings
->SubClass
= L
"UNDEFINED";
1355 ClassStrings
->PIFClass
= L
"UNDEFINED";
1357 CurrentClass
= gClassStringList
;
1358 Code
= (UINT8
) (ClassCode
>> 16);
1362 // Go through all entries of the base class, until the entry with a matching
1363 // base class code is found. If reaches an entry with a null description
1364 // text, the last entry is met, which means no text for the base class was
1365 // found, so no more action is needed.
1367 while (Code
!= CurrentClass
[Index
].Code
) {
1368 if (NULL
== CurrentClass
[Index
].DescText
) {
1375 // A base class was found. Assign description, and check if this class has
1376 // sub-class defined. If sub-class defined, no more action is needed,
1377 // otherwise, continue to find description for the sub-class code.
1379 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1380 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1384 // find Subclass entry
1386 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1387 Code
= (UINT8
) (ClassCode
>> 8);
1391 // Go through all entries of the sub-class, until the entry with a matching
1392 // sub-class code is found. If reaches an entry with a null description
1393 // text, the last entry is met, which means no text for the sub-class was
1394 // found, so no more action is needed.
1396 while (Code
!= CurrentClass
[Index
].Code
) {
1397 if (NULL
== CurrentClass
[Index
].DescText
) {
1404 // A class was found for the sub-class code. Assign description, and check if
1405 // this sub-class has programming interface defined. If no, no more action is
1406 // needed, otherwise, continue to find description for the programming
1409 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1410 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1414 // Find programming interface entry
1416 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1417 Code
= (UINT8
) ClassCode
;
1421 // Go through all entries of the I/F entries, until the entry with a
1422 // matching I/F code is found. If reaches an entry with a null description
1423 // text, the last entry is met, which means no text was found, so no more
1424 // action is needed.
1426 while (Code
!= CurrentClass
[Index
].Code
) {
1427 if (NULL
== CurrentClass
[Index
].DescText
) {
1434 // A class was found for the I/F code. Assign description, done!
1436 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1442 IN UINT8
*ClassCodePtr
,
1443 IN BOOLEAN IncludePIF
1446 Routine Description:
1448 Print strings that represent PCI device class, subclass and programmed I/F
1452 ClassCodePtr Points to the memory which stores register Class Code in PCI
1454 IncludePIF If the printed string should include the programming I/F part
1461 PCI_CLASS_STRINGS ClassStrings
;
1462 CHAR16 OutputString
[PCI_CLASS_STRING_LIMIT
+ 1];
1465 ClassCode
|= ClassCodePtr
[0];
1466 ClassCode
|= (ClassCodePtr
[1] << 8);
1467 ClassCode
|= (ClassCodePtr
[2] << 16);
1470 // Get name from class code
1472 PciGetClassStrings (ClassCode
, &ClassStrings
);
1476 // Only print base class and sub class name
1478 ShellPrintEx(-1,-1, L
"%s - %s - %s",
1479 ClassStrings
.BaseClass
,
1480 ClassStrings
.SubClass
,
1481 ClassStrings
.PIFClass
1486 // Print base class, sub class, and programming inferface name
1490 PCI_CLASS_STRING_LIMIT
* sizeof (CHAR16
),
1492 ClassStrings
.BaseClass
,
1493 ClassStrings
.SubClass
1496 OutputString
[PCI_CLASS_STRING_LIMIT
] = 0;
1497 ShellPrintEx(-1,-1, L
"%s", OutputString
);
1503 IN EFI_HANDLE ImageHandle
,
1504 IN EFI_SYSTEM_TABLE
*SystemTable
1508 PciFindProtocolInterface (
1509 IN EFI_HANDLE
*HandleBuf
,
1510 IN UINTN HandleCount
,
1513 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1517 PciGetProtocolAndResource (
1518 IN EFI_HANDLE Handle
,
1519 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1520 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1524 PciGetNextBusRange (
1525 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1533 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1535 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1539 PciExplainDeviceData (
1540 IN PCI_DEVICE_HEADER
*Device
,
1542 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1546 PciExplainBridgeData (
1547 IN PCI_BRIDGE_HEADER
*Bridge
,
1549 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1557 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1562 PciExplainCardBusData (
1563 IN PCI_CARDBUS_HEADER
*CardBus
,
1565 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1571 IN BOOLEAN MainStatus
,
1572 IN PCI_HEADER_TYPE HeaderType
1581 PciExplainBridgeControl (
1582 IN UINT16
*BridgeControl
,
1583 IN PCI_HEADER_TYPE HeaderType
1587 PciExplainCapabilityStruct (
1588 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1594 PciExplainPciExpress (
1595 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1597 IN UINT8 CapabilityPtr
1602 IN PCIE_CAP_STURCTURE
*PciExpressCap
1606 ExplainPcieDeviceCap (
1607 IN PCIE_CAP_STURCTURE
*PciExpressCap
1611 ExplainPcieDeviceControl (
1612 IN PCIE_CAP_STURCTURE
*PciExpressCap
1616 ExplainPcieDeviceStatus (
1617 IN PCIE_CAP_STURCTURE
*PciExpressCap
1621 ExplainPcieLinkCap (
1622 IN PCIE_CAP_STURCTURE
*PciExpressCap
1626 ExplainPcieLinkControl (
1627 IN PCIE_CAP_STURCTURE
*PciExpressCap
1631 ExplainPcieLinkStatus (
1632 IN PCIE_CAP_STURCTURE
*PciExpressCap
1636 ExplainPcieSlotCap (
1637 IN PCIE_CAP_STURCTURE
*PciExpressCap
1641 ExplainPcieSlotControl (
1642 IN PCIE_CAP_STURCTURE
*PciExpressCap
1646 ExplainPcieSlotStatus (
1647 IN PCIE_CAP_STURCTURE
*PciExpressCap
1651 ExplainPcieRootControl (
1652 IN PCIE_CAP_STURCTURE
*PciExpressCap
1656 ExplainPcieRootCap (
1657 IN PCIE_CAP_STURCTURE
*PciExpressCap
1661 ExplainPcieRootStatus (
1662 IN PCIE_CAP_STURCTURE
*PciExpressCap
1665 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCIE_CAP_STURCTURE
*PciExpressCap
);
1671 } PCIE_CAPREG_FIELD_WIDTH
;
1674 PcieExplainTypeCommon
,
1675 PcieExplainTypeDevice
,
1676 PcieExplainTypeLink
,
1677 PcieExplainTypeSlot
,
1678 PcieExplainTypeRoot
,
1680 } PCIE_EXPLAIN_TYPE
;
1686 PCIE_CAPREG_FIELD_WIDTH Width
;
1687 PCIE_EXPLAIN_FUNCTION Func
;
1688 PCIE_EXPLAIN_TYPE Type
;
1689 } PCIE_EXPLAIN_STRUCT
;
1691 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
1693 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
1697 PcieExplainTypeCommon
1700 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
1704 PcieExplainTypeCommon
1707 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
1711 PcieExplainTypeCommon
1714 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
1717 ExplainPcieDeviceCap
,
1718 PcieExplainTypeDevice
1721 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
1724 ExplainPcieDeviceControl
,
1725 PcieExplainTypeDevice
1728 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
1731 ExplainPcieDeviceStatus
,
1732 PcieExplainTypeDevice
1735 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
1742 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
1745 ExplainPcieLinkControl
,
1749 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
1752 ExplainPcieLinkStatus
,
1756 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
1763 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
1766 ExplainPcieSlotControl
,
1770 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
1773 ExplainPcieSlotStatus
,
1777 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
1780 ExplainPcieRootControl
,
1784 STRING_TOKEN (STR_PCIEX_RSVDP
),
1791 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
1794 ExplainPcieRootStatus
,
1800 (PCIE_CAPREG_FIELD_WIDTH
)0,
1809 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
1810 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
1816 CHAR16
*DevicePortTypeTable
[] = {
1817 L
"PCI Express Endpoint",
1818 L
"Legacy PCI Express Endpoint",
1821 L
"Root Port of PCI Express Root Complex",
1822 L
"Upstream Port of PCI Express Switch",
1823 L
"Downstream Port of PCI Express Switch",
1824 L
"PCI Express to PCI/PCI-X Bridge",
1825 L
"PCI/PCI-X to PCI Express Bridge",
1826 L
"Root Complex Integrated Endpoint",
1827 L
"Root Complex Event Collector"
1830 CHAR16
*L0sLatencyStrTable
[] = {
1832 L
"64ns to less than 128ns",
1833 L
"128ns to less than 256ns",
1834 L
"256ns to less than 512ns",
1835 L
"512ns to less than 1us",
1836 L
"1us to less than 2us",
1841 CHAR16
*L1LatencyStrTable
[] = {
1843 L
"1us to less than 2us",
1844 L
"2us to less than 4us",
1845 L
"4us to less than 8us",
1846 L
"8us to less than 16us",
1847 L
"16us to less than 32us",
1852 CHAR16
*ASPMCtrlStrTable
[] = {
1854 L
"L0s Entry Enabled",
1855 L
"L1 Entry Enabled",
1856 L
"L0s and L1 Entry Enabled"
1859 CHAR16
*SlotPwrLmtScaleTable
[] = {
1866 CHAR16
*IndicatorTable
[] = {
1876 ShellCommandRunPci (
1877 IN EFI_HANDLE ImageHandle
,
1878 IN EFI_SYSTEM_TABLE
*SystemTable
1886 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
1888 PCI_COMMON_HEADER PciHeader
;
1889 PCI_CONFIG_SPACE ConfigSpace
;
1893 BOOLEAN ExplainData
;
1897 UINTN HandleBufSize
;
1898 EFI_HANDLE
*HandleBuf
;
1900 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
1904 LIST_ENTRY
*Package
;
1905 CHAR16
*ProblemParam
;
1906 SHELL_STATUS ShellStatus
;
1910 ShellStatus
= SHELL_SUCCESS
;
1911 Status
= EFI_SUCCESS
;
1919 // initialize the shell lib (we must be in non-auto-init...)
1921 Status
= ShellInitialize();
1922 ASSERT_EFI_ERROR(Status
);
1924 Status
= CommandInit();
1925 ASSERT_EFI_ERROR(Status
);
1928 // parse the command line
1930 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
1931 if (EFI_ERROR(Status
)) {
1932 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
1933 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, ProblemParam
);
1934 FreePool(ProblemParam
);
1935 ShellStatus
= SHELL_INVALID_PARAMETER
;
1941 if (ShellCommandLineGetCount(Package
) == 2) {
1942 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
);
1943 ShellStatus
= SHELL_INVALID_PARAMETER
;
1947 if (ShellCommandLineGetCount(Package
) > 4) {
1948 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
);
1949 ShellStatus
= SHELL_INVALID_PARAMETER
;
1952 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
1953 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"-s");
1954 ShellStatus
= SHELL_INVALID_PARAMETER
;
1958 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
1959 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
1960 // space for handles and call it again.
1962 HandleBufSize
= sizeof (EFI_HANDLE
);
1963 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
1964 if (HandleBuf
== NULL
) {
1965 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
1966 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
1970 Status
= gBS
->LocateHandle (
1972 &gEfiPciRootBridgeIoProtocolGuid
,
1978 if (Status
== EFI_BUFFER_TOO_SMALL
) {
1979 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
1980 if (HandleBuf
== NULL
) {
1981 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
1982 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
1986 Status
= gBS
->LocateHandle (
1988 &gEfiPciRootBridgeIoProtocolGuid
,
1995 if (EFI_ERROR (Status
)) {
1996 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
);
1997 ShellStatus
= SHELL_NOT_FOUND
;
2001 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2003 // Argument Count == 1(no other argument): enumerate all pci functions
2005 if (ShellCommandLineGetCount(Package
) == 1) {
2006 gST
->ConOut
->QueryMode (
2008 gST
->ConOut
->Mode
->Mode
,
2015 if ((ScreenSize
& 1) == 1) {
2022 // For each handle, which decides a segment and a bus number range,
2023 // enumerate all devices on it.
2025 for (Index
= 0; Index
< HandleCount
; Index
++) {
2026 Status
= PciGetProtocolAndResource (
2031 if (EFI_ERROR (Status
)) {
2032 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, Status
);
2033 ShellStatus
= SHELL_NOT_FOUND
;
2037 // No document say it's impossible for a RootBridgeIo protocol handle
2038 // to have more than one address space descriptors, so find out every
2039 // bus range and for each of them do device enumeration.
2042 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2044 if (EFI_ERROR (Status
)) {
2045 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, Status
);
2046 ShellStatus
= SHELL_NOT_FOUND
;
2054 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2056 // For each devices, enumerate all functions it contains
2058 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2060 // For each function, read its configuration space and print summary
2062 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2063 if (ShellGetExecutionBreakFlag ()) {
2064 ShellStatus
= SHELL_ABORTED
;
2067 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2077 // If VendorId = 0xffff, there does not exist a device at this
2078 // location. For each device, if there is any function on it,
2079 // there must be 1 function at Function 0. So if Func = 0, there
2080 // will be no more functions in the same device, so we can break
2081 // loop to deal with the next device.
2083 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2087 if (PciHeader
.VendorId
!= 0xffff) {
2090 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2098 sizeof (PciHeader
) / sizeof (UINT32
),
2103 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2104 IoDev
->SegmentNumber
,
2110 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2112 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2115 PciHeader
.ClassCode
[0]
2119 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2121 // If ScreenSize == 0 we have the console redirected so don't
2127 // If this is not a multi-function device, we can leave the loop
2128 // to deal with the next device.
2130 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2138 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2139 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2140 // devices on all bus, we can leave loop.
2142 if (Descriptors
== NULL
) {
2148 Status
= EFI_SUCCESS
;
2152 ExplainData
= FALSE
;
2157 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2161 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2163 Segment
= (UINT16
) ShellStrToUintn (Temp
);
2167 // The first Argument(except "-i") is assumed to be Bus number, second
2168 // to be Device number, and third to be Func number.
2170 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2172 Bus
= (UINT16
)ShellStrToUintn(Temp
);
2173 if (Bus
> MAX_BUS_NUMBER
) {
2174 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2175 ShellStatus
= SHELL_INVALID_PARAMETER
;
2179 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2181 Device
= (UINT16
) ShellStrToUintn(Temp
);
2182 if (Device
> MAX_DEVICE_NUMBER
){
2183 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2184 ShellStatus
= SHELL_INVALID_PARAMETER
;
2189 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2191 Func
= (UINT16
) ShellStrToUintn(Temp
);
2192 if (Func
> MAX_FUNCTION_NUMBER
){
2193 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2194 ShellStatus
= SHELL_INVALID_PARAMETER
;
2200 // Find the protocol interface who's in charge of current segment, and its
2201 // bus range covers the current bus
2203 Status
= PciFindProtocolInterface (
2211 if (EFI_ERROR (Status
)) {
2213 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
,
2214 gShellDebug1HiiHandle
,
2218 ShellStatus
= SHELL_NOT_FOUND
;
2222 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2223 Status
= IoDev
->Pci
.Read (
2227 sizeof (ConfigSpace
),
2231 if (EFI_ERROR (Status
)) {
2232 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, Status
);
2233 ShellStatus
= SHELL_ACCESS_DENIED
;
2237 mConfigSpace
= &ConfigSpace
;
2242 STRING_TOKEN (STR_PCI_INFO
),
2243 gShellDebug1HiiHandle
,
2255 // Dump standard header of configuration space
2257 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2259 PrivateDumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2260 ShellPrintEx(-1,-1, L
"\r\n");
2263 // Dump device dependent Part of configuration space
2268 sizeof (ConfigSpace
) - SizeOfHeader
,
2273 // If "-i" appears in command line, interpret data in configuration space
2276 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
);
2280 if (HandleBuf
!= NULL
) {
2281 FreePool (HandleBuf
);
2283 if (Package
!= NULL
) {
2284 ShellCommandLineFreeVarList (Package
);
2286 mConfigSpace
= NULL
;
2291 PciFindProtocolInterface (
2292 IN EFI_HANDLE
*HandleBuf
,
2293 IN UINTN HandleCount
,
2296 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2300 Routine Description:
2302 This function finds out the protocol which is in charge of the given
2303 segment, and its bus range covers the current bus number. It lookes
2304 each instances of RootBridgeIoProtocol handle, until the one meets the
2309 HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles
2310 HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles
2311 Segment Segment number of device we are dealing with
2312 Bus Bus number of device we are dealing with
2313 IoDev Handle used to access configuration space of PCI device
2317 EFI_SUCCESS - The command completed successfully
2318 EFI_INVALID_PARAMETER - Invalid parameter
2324 BOOLEAN FoundInterface
;
2325 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2330 FoundInterface
= FALSE
;
2332 // Go through all handles, until the one meets the criteria is found
2334 for (Index
= 0; Index
< HandleCount
; Index
++) {
2335 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2336 if (EFI_ERROR (Status
)) {
2340 // When Descriptors == NULL, the Configuration() is not implemented,
2341 // so we only check the Segment number
2343 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2347 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2352 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2353 if (EFI_ERROR (Status
)) {
2361 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2362 FoundInterface
= TRUE
;
2368 if (FoundInterface
) {
2371 return EFI_INVALID_PARAMETER
;
2376 PciGetProtocolAndResource (
2377 IN EFI_HANDLE Handle
,
2378 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
2379 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
2383 Routine Description:
2385 This function gets the protocol interface from the given handle, and
2386 obtains its address space descriptors.
2390 Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle
2391 IoDev Handle used to access configuration space of PCI device
2392 Descriptors Points to the address space descriptors
2396 EFI_SUCCESS The command completed successfully
2403 // Get inferface from protocol
2405 Status
= gBS
->HandleProtocol (
2407 &gEfiPciRootBridgeIoProtocolGuid
,
2411 if (EFI_ERROR (Status
)) {
2415 // Call Configuration() to get address space descriptors
2417 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
2418 if (Status
== EFI_UNSUPPORTED
) {
2419 *Descriptors
= NULL
;
2428 PciGetNextBusRange (
2429 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2436 Routine Description:
2438 This function get the next bus range of given address space descriptors.
2439 It also moves the pointer backward a node, to get prepared to be called
2444 Descriptors points to current position of a serial of address space
2446 MinBus The lower range of bus number
2447 ManBus The upper range of bus number
2448 IsEnd Meet end of the serial of descriptors
2452 EFI_SUCCESS The command completed successfully
2459 // When *Descriptors is NULL, Configuration() is not implemented, so assume
2460 // range is 0~PCI_MAX_BUS
2462 if ((*Descriptors
) == NULL
) {
2464 *MaxBus
= PCI_MAX_BUS
;
2468 // *Descriptors points to one or more address space descriptors, which
2469 // ends with a end tagged descriptor. Examine each of the descriptors,
2470 // if a bus typed one is found and its bus range covers bus, this handle
2471 // is the handle we are looking for.
2474 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2475 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2476 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2477 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2479 return (EFI_SUCCESS
);
2485 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
2494 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2496 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2500 Routine Description:
2502 Explain the data in PCI configuration space. The part which is common for
2503 PCI device and bridge is interpreted in this function. It calls other
2504 functions to interpret data unique for device or bridge.
2508 ConfigSpace Data in PCI configuration space
2509 Address Address used to access configuration space of this PCI device
2510 IoDev Handle used to access configuration space of PCI device
2514 EFI_SUCCESS The command completed successfully
2518 PCI_COMMON_HEADER
*Common
;
2519 PCI_HEADER_TYPE HeaderType
;
2523 Common
= &(ConfigSpace
->Common
);
2528 // Print Vendor Id and Device Id
2530 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
2531 INDEX_OF (&(Common
->VendorId
)),
2533 INDEX_OF (&(Common
->DeviceId
)),
2538 // Print register Command
2540 PciExplainCommand (&(Common
->Command
));
2543 // Print register Status
2545 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
2548 // Print register Revision ID
2550 ShellPrintEx(-1, -1, L
"/r/n");
2551 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
2552 INDEX_OF (&(Common
->RevisionId
)),
2557 // Print register BIST
2559 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->BIST
)));
2560 if ((Common
->BIST
& PCI_BIT_7
) != 0) {
2561 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->BIST
);
2563 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
2566 // Print register Cache Line Size
2568 ShellPrintHiiEx(-1, -1, NULL
,
2569 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
2570 gShellDebug1HiiHandle
,
2571 INDEX_OF (&(Common
->CacheLineSize
)),
2572 Common
->CacheLineSize
2576 // Print register Latency Timer
2578 ShellPrintHiiEx(-1, -1, NULL
,
2579 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
2580 gShellDebug1HiiHandle
,
2581 INDEX_OF (&(Common
->PrimaryLatencyTimer
)),
2582 Common
->PrimaryLatencyTimer
2586 // Print register Header Type
2588 ShellPrintHiiEx(-1, -1, NULL
,
2589 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
2590 gShellDebug1HiiHandle
,
2591 INDEX_OF (&(Common
->HeaderType
)),
2595 if ((Common
->HeaderType
& PCI_BIT_7
) != 0) {
2596 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
2599 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
2602 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
2603 switch (HeaderType
) {
2605 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
2609 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
2612 case PciCardBusBridge
:
2613 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
2617 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
2618 HeaderType
= PciUndefined
;
2622 // Print register Class Code
2624 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
2625 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
2628 if (ShellGetExecutionBreakFlag()) {
2633 // Interpret remaining part of PCI configuration header depending on
2637 Status
= EFI_SUCCESS
;
2638 switch (HeaderType
) {
2640 Status
= PciExplainDeviceData (
2641 &(ConfigSpace
->NonCommon
.Device
),
2645 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilitiesPtr
;
2649 Status
= PciExplainBridgeData (
2650 &(ConfigSpace
->NonCommon
.Bridge
),
2654 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilitiesPtr
;
2657 case PciCardBusBridge
:
2658 Status
= PciExplainCardBusData (
2659 &(ConfigSpace
->NonCommon
.CardBus
),
2663 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.CapabilitiesPtr
;
2667 // If Status bit4 is 1, dump or explain capability structure
2669 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
2670 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
);
2677 PciExplainDeviceData (
2678 IN PCI_DEVICE_HEADER
*Device
,
2680 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2684 Routine Description:
2686 Explain the device specific part of data in PCI configuration space.
2690 Device Data in PCI configuration space
2691 Address Address used to access configuration space of this PCI device
2692 IoDev Handle used to access configuration space of PCI device
2696 EFI_SUCCESS The command completed successfully
2706 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
2707 // exist. If these no Bar for this function, print "none", otherwise
2708 // list detail information about this Bar.
2710 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
2713 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
2714 for (Index
= 0; Index
< BarCount
; Index
++) {
2715 if (Device
->Bar
[Index
] == 0) {
2721 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
2722 Print (L
" --------------------------------------------------------------------------");
2725 Status
= PciExplainBar (
2726 &(Device
->Bar
[Index
]),
2727 &(mConfigSpace
->Common
.Command
),
2733 if (EFI_ERROR (Status
)) {
2739 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
2742 Print (L
"\n --------------------------------------------------------------------------");
2746 // Print register Expansion ROM Base Address
2748 if ((Device
->ROMBar
& PCI_BIT_0
) == 0) {
2749 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ROMBar
)));
2752 ShellPrintHiiEx(-1, -1, NULL
,
2753 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
2754 gShellDebug1HiiHandle
,
2755 INDEX_OF (&(Device
->ROMBar
)),
2760 // Print register Cardbus CIS ptr
2762 ShellPrintHiiEx(-1, -1, NULL
,
2763 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
2764 gShellDebug1HiiHandle
,
2765 INDEX_OF (&(Device
->CardBusCISPtr
)),
2766 Device
->CardBusCISPtr
2770 // Print register Sub-vendor ID and subsystem ID
2772 ShellPrintHiiEx(-1, -1, NULL
,
2773 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
2774 gShellDebug1HiiHandle
,
2775 INDEX_OF (&(Device
->SubVendorId
)),
2779 ShellPrintHiiEx(-1, -1, NULL
,
2780 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
2781 gShellDebug1HiiHandle
,
2782 INDEX_OF (&(Device
->SubSystemId
)),
2787 // Print register Capabilities Ptr
2789 ShellPrintHiiEx(-1, -1, NULL
,
2790 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
2791 gShellDebug1HiiHandle
,
2792 INDEX_OF (&(Device
->CapabilitiesPtr
)),
2793 Device
->CapabilitiesPtr
2797 // Print register Interrupt Line and interrupt pin
2799 ShellPrintHiiEx(-1, -1, NULL
,
2800 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
2801 gShellDebug1HiiHandle
,
2802 INDEX_OF (&(Device
->InterruptLine
)),
2803 Device
->InterruptLine
2806 ShellPrintHiiEx(-1, -1, NULL
,
2807 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
2808 gShellDebug1HiiHandle
,
2809 INDEX_OF (&(Device
->InterruptPin
)),
2810 Device
->InterruptPin
2814 // Print register Min_Gnt and Max_Lat
2816 ShellPrintHiiEx(-1, -1, NULL
,
2817 STRING_TOKEN (STR_PCI2_MIN_GNT
),
2818 gShellDebug1HiiHandle
,
2819 INDEX_OF (&(Device
->MinGnt
)),
2823 ShellPrintHiiEx(-1, -1, NULL
,
2824 STRING_TOKEN (STR_PCI2_MAX_LAT
),
2825 gShellDebug1HiiHandle
,
2826 INDEX_OF (&(Device
->MaxLat
)),
2834 PciExplainBridgeData (
2835 IN PCI_BRIDGE_HEADER
*Bridge
,
2837 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2841 Routine Description:
2843 Explain the bridge specific part of data in PCI configuration space.
2847 Bridge Bridge specific data region in PCI configuration space
2848 Address Address used to access configuration space of this PCI device
2849 IoDev Handle used to access configuration space of PCI device
2853 EFI_SUCCESS The command completed successfully
2864 // Print Base Address Registers. When Bar = 0, this Bar does not
2865 // exist. If these no Bar for this function, print "none", otherwise
2866 // list detail information about this Bar.
2868 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
2871 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
2873 for (Index
= 0; Index
< BarCount
; Index
++) {
2874 if (Bridge
->Bar
[Index
] == 0) {
2880 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
2881 Print (L
" --------------------------------------------------------------------------");
2884 Status
= PciExplainBar (
2885 &(Bridge
->Bar
[Index
]),
2886 &(mConfigSpace
->Common
.Command
),
2892 if (EFI_ERROR (Status
)) {
2898 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
2900 Print (L
"\n --------------------------------------------------------------------------");
2904 // Expansion register ROM Base Address
2906 if ((Bridge
->ROMBar
& PCI_BIT_0
) == 0) {
2907 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ROMBar
)));
2910 ShellPrintHiiEx(-1, -1, NULL
,
2911 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
2912 gShellDebug1HiiHandle
,
2913 INDEX_OF (&(Bridge
->ROMBar
)),
2918 // Print Bus Numbers(Primary, Secondary, and Subordinate
2920 ShellPrintHiiEx(-1, -1, NULL
,
2921 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
2922 gShellDebug1HiiHandle
,
2923 INDEX_OF (&(Bridge
->PrimaryBus
)),
2924 INDEX_OF (&(Bridge
->SecondaryBus
)),
2925 INDEX_OF (&(Bridge
->SubordinateBus
))
2928 Print (L
" ------------------------------------------------------\n");
2930 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
2931 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
2932 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
2935 // Print register Secondary Latency Timer
2937 ShellPrintHiiEx(-1, -1, NULL
,
2938 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
2939 gShellDebug1HiiHandle
,
2940 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
2941 Bridge
->SecondaryLatencyTimer
2945 // Print register Secondary Status
2947 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
2950 // Print I/O and memory ranges this bridge forwards. There are 3 resource
2951 // types: I/O, memory, and pre-fetchable memory. For each resource type,
2952 // base and limit address are listed.
2954 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
2955 Print (L
"----------------------------------------------------------------------\n");
2960 IoAddress32
= (Bridge
->IoBaseUpper
<< 16 | Bridge
->IoBase
<< 8);
2961 IoAddress32
&= 0xfffff000;
2962 ShellPrintHiiEx(-1, -1, NULL
,
2963 STRING_TOKEN (STR_PCI2_TWO_VARS
),
2964 gShellDebug1HiiHandle
,
2965 INDEX_OF (&(Bridge
->IoBase
)),
2969 IoAddress32
= (Bridge
->IoLimitUpper
<< 16 | Bridge
->IoLimit
<< 8);
2970 IoAddress32
|= 0x00000fff;
2971 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
2974 // Memory Base & Limit
2976 ShellPrintHiiEx(-1, -1, NULL
,
2977 STRING_TOKEN (STR_PCI2_MEMORY
),
2978 gShellDebug1HiiHandle
,
2979 INDEX_OF (&(Bridge
->MemoryBase
)),
2980 (Bridge
->MemoryBase
<< 16) & 0xfff00000
2983 ShellPrintHiiEx(-1, -1, NULL
,
2984 STRING_TOKEN (STR_PCI2_ONE_VAR
),
2985 gShellDebug1HiiHandle
,
2986 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
2990 // Pre-fetch-able Memory Base & Limit
2992 ShellPrintHiiEx(-1, -1, NULL
,
2993 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
2994 gShellDebug1HiiHandle
,
2995 INDEX_OF (&(Bridge
->PrefetchableMemBase
)),
2996 Bridge
->PrefetchableBaseUpper
,
2997 (Bridge
->PrefetchableMemBase
<< 16) & 0xfff00000
3000 ShellPrintHiiEx(-1, -1, NULL
,
3001 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3002 gShellDebug1HiiHandle
,
3003 Bridge
->PrefetchableLimitUpper
,
3004 (Bridge
->PrefetchableMemLimit
<< 16) | 0x000fffff
3008 // Print register Capabilities Pointer
3010 ShellPrintHiiEx(-1, -1, NULL
,
3011 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3012 gShellDebug1HiiHandle
,
3013 INDEX_OF (&(Bridge
->CapabilitiesPtr
)),
3014 Bridge
->CapabilitiesPtr
3018 // Print register Bridge Control
3020 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3023 // Print register Interrupt Line & PIN
3025 ShellPrintHiiEx(-1, -1, NULL
,
3026 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3027 gShellDebug1HiiHandle
,
3028 INDEX_OF (&(Bridge
->InterruptLine
)),
3029 Bridge
->InterruptLine
3032 ShellPrintHiiEx(-1, -1, NULL
,
3033 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3034 gShellDebug1HiiHandle
,
3035 INDEX_OF (&(Bridge
->InterruptPin
)),
3036 Bridge
->InterruptPin
3047 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3052 Routine Description:
3054 Explain the Base Address Register(Bar) in PCI configuration space.
3058 Bar Points to the Base Address Register intended to interpret
3059 Command Points to the register Command
3060 Address Address used to access configuration space of this PCI device
3061 IoDev Handle used to access configuration space of PCI device
3066 EFI_SUCCESS The command completed successfully
3087 // According the bar type, list detail about this bar, for example: 32 or
3088 // 64 bits; pre-fetchable or not.
3090 if ((*Bar
& PCI_BIT_0
) == 0) {
3092 // This bar is of memory type
3096 if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) == 0) {
3097 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3098 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3099 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3101 } else if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) != 0) {
3103 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3104 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, RShiftU64 ((Bar64
& 0xfffffffffffffff0), 32));
3105 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0));
3106 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3107 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3115 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3116 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3119 if ((*Bar
& PCI_BIT_3
) == 0) {
3120 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3123 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3128 // This bar is of io type
3131 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3136 // Get BAR length(or the amount of resource this bar demands for). To get
3137 // Bar length, first we should temporarily disable I/O and memory access
3138 // of this function(by set bits in the register Command), then write all
3139 // "1"s to this bar. The bar value read back is the amount of resource
3140 // this bar demands for.
3143 // Disable io & mem access
3145 OldCommand
= *Command
;
3146 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3147 RegAddress
= Address
| INDEX_OF (Command
);
3148 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3150 RegAddress
= Address
| INDEX_OF (Bar
);
3153 // Read after write the BAR to get the size
3157 NewBar32
= 0xffffffff;
3159 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3160 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3161 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3164 NewBar32
= NewBar32
& 0xfffffff0;
3165 NewBar32
= (~NewBar32
) + 1;
3168 NewBar32
= NewBar32
& 0xfffffffc;
3169 NewBar32
= (~NewBar32
) + 1;
3170 NewBar32
= NewBar32
& 0x0000ffff;
3175 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3176 NewBar64
= 0xffffffffffffffff;
3178 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3179 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3180 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3183 NewBar64
= NewBar64
& 0xfffffffffffffff0;
3184 NewBar64
= (~NewBar64
) + 1;
3187 NewBar64
= NewBar64
& 0xfffffffffffffffc;
3188 NewBar64
= (~NewBar64
) + 1;
3189 NewBar64
= NewBar64
& 0x000000000000ffff;
3193 // Enable io & mem access
3195 RegAddress
= Address
| INDEX_OF (Command
);
3196 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3200 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3201 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3204 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, RShiftU64 (NewBar64
, 32));
3205 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3207 ShellPrintHiiEx(-1, -1, NULL
,
3208 STRING_TOKEN (STR_PCI2_RSHIFT
),
3209 gShellDebug1HiiHandle
,
3210 RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0) - 1), 32)
3212 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0) - 1));
3216 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3217 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3224 PciExplainCardBusData (
3225 IN PCI_CARDBUS_HEADER
*CardBus
,
3227 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3231 Routine Description:
3233 Explain the cardbus specific part of data in PCI configuration space.
3237 CardBus CardBus specific region of PCI configuration space
3238 Address Address used to access configuration space of this PCI device
3239 IoDev Handle used to access configuration space of PCI device
3243 EFI_SUCCESS The command completed successfully
3248 PCI_CARDBUS_DATA
*CardBusData
;
3250 ShellPrintHiiEx(-1, -1, NULL
,
3251 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3252 gShellDebug1HiiHandle
,
3253 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3254 CardBus
->CardBusSocketReg
3258 // Print Secondary Status
3260 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3263 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3264 // Subordinate bus number
3266 ShellPrintHiiEx(-1, -1, NULL
,
3267 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3268 gShellDebug1HiiHandle
,
3269 INDEX_OF (&(CardBus
->PciBusNumber
)),
3270 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3271 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3274 Print (L
" ------------------------------------------------------\n");
3276 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3277 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3278 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3281 // Print CardBus Latency Timer
3283 ShellPrintHiiEx(-1, -1, NULL
,
3284 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3285 gShellDebug1HiiHandle
,
3286 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3287 CardBus
->CardBusLatencyTimer
3291 // Print Memory/Io ranges this cardbus bridge forwards
3293 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3294 Print (L
"----------------------------------------------------------------------\n");
3296 ShellPrintHiiEx(-1, -1, NULL
,
3297 STRING_TOKEN (STR_PCI2_MEM_3
),
3298 gShellDebug1HiiHandle
,
3299 INDEX_OF (&(CardBus
->MemoryBase0
)),
3300 CardBus
->BridgeControl
& PCI_BIT_8
? L
" Prefetchable" : L
"Non-Prefetchable",
3301 CardBus
->MemoryBase0
& 0xfffff000,
3302 CardBus
->MemoryLimit0
| 0x00000fff
3305 ShellPrintHiiEx(-1, -1, NULL
,
3306 STRING_TOKEN (STR_PCI2_MEM_3
),
3307 gShellDebug1HiiHandle
,
3308 INDEX_OF (&(CardBus
->MemoryBase1
)),
3309 CardBus
->BridgeControl
& PCI_BIT_9
? L
" Prefetchable" : L
"Non-Prefetchable",
3310 CardBus
->MemoryBase1
& 0xfffff000,
3311 CardBus
->MemoryLimit1
| 0x00000fff
3314 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& PCI_BIT_0
);
3315 ShellPrintHiiEx(-1, -1, NULL
,
3316 STRING_TOKEN (STR_PCI2_IO_2
),
3317 gShellDebug1HiiHandle
,
3318 INDEX_OF (&(CardBus
->IoBase0
)),
3319 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3320 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3321 CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff) | 0x00000003
3324 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& PCI_BIT_0
);
3325 ShellPrintHiiEx(-1, -1, NULL
,
3326 STRING_TOKEN (STR_PCI2_IO_2
),
3327 gShellDebug1HiiHandle
,
3328 INDEX_OF (&(CardBus
->IoBase1
)),
3329 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3330 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3331 CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff) | 0x00000003
3335 // Print register Interrupt Line & PIN
3337 ShellPrintHiiEx(-1, -1, NULL
,
3338 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3339 gShellDebug1HiiHandle
,
3340 INDEX_OF (&(CardBus
->InterruptLine
)),
3341 CardBus
->InterruptLine
,
3342 INDEX_OF (&(CardBus
->InterruptPin
)),
3343 CardBus
->InterruptPin
3347 // Print register Bridge Control
3349 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3352 // Print some registers in data region of PCI configuration space for cardbus
3353 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3356 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_HEADER
));
3358 ShellPrintHiiEx(-1, -1, NULL
,
3359 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3360 gShellDebug1HiiHandle
,
3361 INDEX_OF (&(CardBusData
->SubVendorId
)),
3362 CardBusData
->SubVendorId
,
3363 INDEX_OF (&(CardBusData
->SubSystemId
)),
3364 CardBusData
->SubSystemId
3367 ShellPrintHiiEx(-1, -1, NULL
,
3368 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3369 gShellDebug1HiiHandle
,
3370 INDEX_OF (&(CardBusData
->LegacyBase
)),
3371 CardBusData
->LegacyBase
3380 IN BOOLEAN MainStatus
,
3381 IN PCI_HEADER_TYPE HeaderType
3385 Routine Description:
3387 Explain each meaningful bit of register Status. The definition of Status is
3388 slightly different depending on the PCI header type.
3392 Status Points to the content of register Status
3393 MainStatus Indicates if this register is main status(not secondary
3395 HeaderType Header type of this PCI device
3399 EFI_SUCCESS The command completed successfully
3404 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3407 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3410 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_4
) != 0);
3413 // Bit 5 is meaningless for CardBus Bridge
3415 if (HeaderType
== PciCardBusBridge
) {
3416 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3419 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3422 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_7
) != 0);
3424 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_8
) != 0);
3426 // Bit 9 and bit 10 together decides the DEVSEL timing
3428 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3429 if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) == 0) {
3430 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3432 } else if ((*Status
& PCI_BIT_9
) != 0 && (*Status
& PCI_BIT_10
) == 0) {
3433 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3435 } else if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) != 0) {
3436 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3439 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3442 ShellPrintHiiEx(-1, -1, NULL
,
3443 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3444 gShellDebug1HiiHandle
,
3445 (*Status
& PCI_BIT_11
) != 0
3448 ShellPrintHiiEx(-1, -1, NULL
,
3449 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3450 gShellDebug1HiiHandle
,
3451 (*Status
& PCI_BIT_12
) != 0
3454 ShellPrintHiiEx(-1, -1, NULL
,
3455 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3456 gShellDebug1HiiHandle
,
3457 (*Status
& PCI_BIT_13
) != 0
3461 ShellPrintHiiEx(-1, -1, NULL
,
3462 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
3463 gShellDebug1HiiHandle
,
3464 (*Status
& PCI_BIT_14
) != 0
3468 ShellPrintHiiEx(-1, -1, NULL
,
3469 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
3470 gShellDebug1HiiHandle
,
3471 (*Status
& PCI_BIT_14
) != 0
3475 ShellPrintHiiEx(-1, -1, NULL
,
3476 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
3477 gShellDebug1HiiHandle
,
3478 (*Status
& PCI_BIT_15
) != 0
3490 Routine Description:
3492 Explain each meaningful bit of register Command.
3496 Command Points to the content of register Command
3500 EFI_SUCCESS The command completed successfully
3505 // Print the binary value of register Command
3507 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
3510 // Explain register Command bit by bit
3512 ShellPrintHiiEx(-1, -1, NULL
,
3513 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
3514 gShellDebug1HiiHandle
,
3515 (*Command
& PCI_BIT_0
) != 0
3518 ShellPrintHiiEx(-1, -1, NULL
,
3519 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
3520 gShellDebug1HiiHandle
,
3521 (*Command
& PCI_BIT_1
) != 0
3524 ShellPrintHiiEx(-1, -1, NULL
,
3525 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
3526 gShellDebug1HiiHandle
,
3527 (*Command
& PCI_BIT_2
) != 0
3530 ShellPrintHiiEx(-1, -1, NULL
,
3531 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
3532 gShellDebug1HiiHandle
,
3533 (*Command
& PCI_BIT_3
) != 0
3536 ShellPrintHiiEx(-1, -1, NULL
,
3537 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
3538 gShellDebug1HiiHandle
,
3539 (*Command
& PCI_BIT_4
) != 0
3542 ShellPrintHiiEx(-1, -1, NULL
,
3543 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
3544 gShellDebug1HiiHandle
,
3545 (*Command
& PCI_BIT_5
) != 0
3548 ShellPrintHiiEx(-1, -1, NULL
,
3549 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
3550 gShellDebug1HiiHandle
,
3551 (*Command
& PCI_BIT_6
) != 0
3554 ShellPrintHiiEx(-1, -1, NULL
,
3555 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
3556 gShellDebug1HiiHandle
,
3557 (*Command
& PCI_BIT_7
) != 0
3560 ShellPrintHiiEx(-1, -1, NULL
,
3561 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
3562 gShellDebug1HiiHandle
,
3563 (*Command
& PCI_BIT_8
) != 0
3566 ShellPrintHiiEx(-1, -1, NULL
,
3567 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
3568 gShellDebug1HiiHandle
,
3569 (*Command
& PCI_BIT_9
) != 0
3576 PciExplainBridgeControl (
3577 IN UINT16
*BridgeControl
,
3578 IN PCI_HEADER_TYPE HeaderType
3582 Routine Description:
3584 Explain each meaningful bit of register Bridge Control.
3588 BridgeControl Points to the content of register Bridge Control
3589 HeaderType The headertype
3593 EFI_SUCCESS The command completed successfully
3597 ShellPrintHiiEx(-1, -1, NULL
,
3598 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
3599 gShellDebug1HiiHandle
,
3600 INDEX_OF (BridgeControl
),
3604 ShellPrintHiiEx(-1, -1, NULL
,
3605 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
3606 gShellDebug1HiiHandle
,
3607 (*BridgeControl
& PCI_BIT_0
) != 0
3609 ShellPrintHiiEx(-1, -1, NULL
,
3610 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
3611 gShellDebug1HiiHandle
,
3612 (*BridgeControl
& PCI_BIT_1
) != 0
3614 ShellPrintHiiEx(-1, -1, NULL
,
3615 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
3616 gShellDebug1HiiHandle
,
3617 (*BridgeControl
& PCI_BIT_2
) != 0
3619 ShellPrintHiiEx(-1, -1, NULL
,
3620 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
3621 gShellDebug1HiiHandle
,
3622 (*BridgeControl
& PCI_BIT_3
) != 0
3624 ShellPrintHiiEx(-1, -1, NULL
,
3625 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
3626 gShellDebug1HiiHandle
,
3627 (*BridgeControl
& PCI_BIT_5
) != 0
3631 // Register Bridge Control has some slight differences between P2P bridge
3632 // and Cardbus bridge from bit 6 to bit 11.
3634 if (HeaderType
== PciP2pBridge
) {
3635 ShellPrintHiiEx(-1, -1, NULL
,
3636 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
3637 gShellDebug1HiiHandle
,
3638 (*BridgeControl
& PCI_BIT_6
) != 0
3640 ShellPrintHiiEx(-1, -1, NULL
,
3641 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
3642 gShellDebug1HiiHandle
,
3643 (*BridgeControl
& PCI_BIT_7
) != 0
3645 ShellPrintHiiEx(-1, -1, NULL
,
3646 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
3647 gShellDebug1HiiHandle
,
3648 (*BridgeControl
& PCI_BIT_8
)!=0 ? L
"2^10" : L
"2^15"
3650 ShellPrintHiiEx(-1, -1, NULL
,
3651 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
3652 gShellDebug1HiiHandle
,
3653 (*BridgeControl
& PCI_BIT_9
)!=0 ? L
"2^10" : L
"2^15"
3655 ShellPrintHiiEx(-1, -1, NULL
,
3656 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
3657 gShellDebug1HiiHandle
,
3658 (*BridgeControl
& PCI_BIT_10
) != 0
3660 ShellPrintHiiEx(-1, -1, NULL
,
3661 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
3662 gShellDebug1HiiHandle
,
3663 (*BridgeControl
& PCI_BIT_11
) != 0
3667 ShellPrintHiiEx(-1, -1, NULL
,
3668 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
3669 gShellDebug1HiiHandle
,
3670 (*BridgeControl
& PCI_BIT_6
) != 0
3672 ShellPrintHiiEx(-1, -1, NULL
,
3673 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
3674 gShellDebug1HiiHandle
,
3675 (*BridgeControl
& PCI_BIT_7
) != 0
3677 ShellPrintHiiEx(-1, -1, NULL
,
3678 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
3679 gShellDebug1HiiHandle
,
3680 (*BridgeControl
& PCI_BIT_10
) != 0
3688 PciExplainCapabilityStruct (
3689 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3694 UINT8 CapabilityPtr
;
3695 UINT16 CapabilityEntry
;
3699 CapabilityPtr
= CapPtr
;
3702 // Go through the Capability list
3704 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
3705 RegAddress
= Address
+ CapabilityPtr
;
3706 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
3708 CapabilityID
= (UINT8
) CapabilityEntry
;
3711 // Explain PciExpress data
3713 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
3714 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
);
3718 // Explain other capabilities here
3720 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
3728 IN PCIE_CAP_STURCTURE
*PciExpressCap
3732 CHAR16
*DevicePortType
;
3734 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3736 L
" Capability Version(3:0): %E0x%04x%N\n",
3737 PCIE_CAP_VERSION (PcieCapReg
)
3739 if ((UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) < PCIE_DEVICE_PORT_TYPE_MAX
) {
3740 DevicePortType
= DevicePortTypeTable
[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
)];
3742 DevicePortType
= L
"Unknown Type";
3745 L
" Device/PortType(7:4): %E%s%N\n",
3749 // 'Slot Implemented' is only valid for:
3750 // a) Root Port of PCI Express Root Complex, or
3751 // b) Downstream Port of PCI Express Switch
3753 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_ROOT_COMPLEX_ROOT_PORT
||
3754 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_SWITCH_DOWNSTREAM_PORT
) {
3756 L
" Slot Implemented(8): %E%d%N\n",
3757 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg
)
3761 L
" Interrupt Message Number(13:9): %E0x%05x%N\n",
3762 PCIE_CAP_INT_MSG_NUM (PcieCapReg
)
3768 ExplainPcieDeviceCap (
3769 IN PCIE_CAP_STURCTURE
*PciExpressCap
3773 UINT32 PcieDeviceCap
;
3774 UINT8 DevicePortType
;
3778 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3779 PcieDeviceCap
= PciExpressCap
->PcieDeviceCap
;
3780 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
);
3781 Print (L
" Max_Payload_Size Supported(2:0): ");
3782 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) < 6) {
3783 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) + 7));
3785 Print (L
"%EUnknown%N\n");
3788 L
" Phantom Functions Supported(4:3): %E%d%N\n",
3789 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap
)
3792 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",
3793 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap
) ? 8 : 5
3796 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
3798 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3799 L0sLatency
= (UINT8
) PCIE_CAP_L0sLatency (PcieDeviceCap
);
3800 L1Latency
= (UINT8
) PCIE_CAP_L1Latency (PcieDeviceCap
);
3801 Print (L
" Endpoint L0s Acceptable Latency(8:6): ");
3802 if (L0sLatency
< 4) {
3803 Print (L
"%EMaximum of %d ns%N\n", 1 << (L0sLatency
+ 6));
3805 if (L0sLatency
< 7) {
3806 Print (L
"%EMaximum of %d us%N\n", 1 << (L0sLatency
- 3));
3808 Print (L
"%ENo limit%N\n");
3811 Print (L
" Endpoint L1 Acceptable Latency(11:9): ");
3812 if (L1Latency
< 7) {
3813 Print (L
"%EMaximum of %d us%N\n", 1 << (L1Latency
+ 1));
3815 Print (L
"%ENo limit%N\n");
3819 L
" Role-based Error Reporting(15): %E%d%N\n",
3820 PCIE_CAP_ERR_REPORTING (PcieDeviceCap
)
3823 // Only valid for Upstream Port:
3824 // a) Captured Slot Power Limit Value
3825 // b) Captured Slot Power Scale
3827 if (DevicePortType
== PCIE_SWITCH_UPSTREAM_PORT
) {
3829 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",
3830 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap
)
3833 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\n",
3834 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap
)]
3838 // Function Level Reset Capability is only valid for Endpoint
3840 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3842 L
" Function Level Reset Capability(28): %E%d%N\n",
3843 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap
)
3850 ExplainPcieDeviceControl (
3851 IN PCIE_CAP_STURCTURE
*PciExpressCap
3855 UINT16 PcieDeviceControl
;
3857 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3858 PcieDeviceControl
= PciExpressCap
->DeviceControl
;
3860 L
" Correctable Error Reporting Enable(0): %E%d%N\n",
3861 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3864 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\n",
3865 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3868 L
" Fatal Error Reporting Enable(2): %E%d%N\n",
3869 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3872 L
" Unsupported Request Reporting Enable(3): %E%d%N\n",
3873 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl
)
3876 L
" Enable Relaxed Ordering(4): %E%d%N\n",
3877 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl
)
3879 Print (L
" Max_Payload_Size(7:5): ");
3880 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) < 6) {
3881 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) + 7));
3883 Print (L
"%EUnknown%N\n");
3886 L
" Extended Tag Field Enable(8): %E%d%N\n",
3887 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl
)
3890 L
" Phantom Functions Enable(9): %E%d%N\n",
3891 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl
)
3894 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",
3895 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl
)
3898 L
" Enable No Snoop(11): %E%d%N\n",
3899 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl
)
3901 Print (L
" Max_Read_Request_Size(14:12): ");
3902 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) < 6) {
3903 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) + 7));
3905 Print (L
"%EUnknown%N\n");
3908 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
3910 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_PCIE_TO_PCIX_BRIDGE
) {
3912 L
" Bridge Configuration Retry Enable(15): %E%d%N\n",
3913 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl
)
3920 ExplainPcieDeviceStatus (
3921 IN PCIE_CAP_STURCTURE
*PciExpressCap
3924 UINT16 PcieDeviceStatus
;
3926 PcieDeviceStatus
= PciExpressCap
->DeviceStatus
;
3928 L
" Correctable Error Detected(0): %E%d%N\n",
3929 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus
)
3932 L
" Non-Fatal Error Detected(1): %E%d%N\n",
3933 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus
)
3936 L
" Fatal Error Detected(2): %E%d%N\n",
3937 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus
)
3940 L
" Unsupported Request Detected(3): %E%d%N\n",
3941 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus
)
3944 L
" AUX Power Detected(4): %E%d%N\n",
3945 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus
)
3948 L
" Transactions Pending(5): %E%d%N\n",
3949 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus
)
3955 ExplainPcieLinkCap (
3956 IN PCIE_CAP_STURCTURE
*PciExpressCap
3960 CHAR16
*SupLinkSpeeds
;
3963 PcieLinkCap
= PciExpressCap
->LinkCap
;
3964 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap
)) {
3966 SupLinkSpeeds
= L
"2.5 GT/s";
3969 SupLinkSpeeds
= L
"5.0 GT/s and 2.5 GT/s";
3972 SupLinkSpeeds
= L
"Unknown";
3976 L
" Supported Link Speeds(3:0): %E%s supported%N\n",
3980 L
" Maximum Link Width(9:4): %Ex%d%N\n",
3981 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap
)
3983 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap
)) {
3985 ASPM
= L
"L0s Entry";
3988 ASPM
= L
"L0s and L1";
3995 L
" Active State Power Management Support(11:10): %E%s Supported%N\n",
3999 L
" L0s Exit Latency(14:12): %E%s%N\n",
4000 L0sLatencyStrTable
[PCIE_CAP_L0s_LATENCY (PcieLinkCap
)]
4003 L
" L1 Exit Latency(17:15): %E%s%N\n",
4004 L1LatencyStrTable
[PCIE_CAP_L0s_LATENCY (PcieLinkCap
)]
4007 L
" Clock Power Management(18): %E%d%N\n",
4008 PCIE_CAP_CLOCK_PM (PcieLinkCap
)
4011 L
" Surprise Down Error Reporting Capable(19): %E%d%N\n",
4012 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap
)
4015 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",
4016 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap
)
4019 L
" Link Bandwidth Notification Capability(21): %E%d%N\n",
4020 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap
)
4023 L
" Port Number(31:24): %E0x%02x%N\n",
4024 PCIE_CAP_PORT_NUMBER (PcieLinkCap
)
4030 ExplainPcieLinkControl (
4031 IN PCIE_CAP_STURCTURE
*PciExpressCap
4034 UINT16 PcieLinkControl
;
4035 UINT8 DevicePortType
;
4037 PcieLinkControl
= PciExpressCap
->LinkControl
;
4038 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
->PcieCapReg
);
4040 L
" Active State Power Management Control(1:0): %E%s%N\n",
4041 ASPMCtrlStrTable
[PCIE_CAP_ASPM_CONTROL (PcieLinkControl
)]
4044 // RCB is not applicable to switches
4046 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4048 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\n",
4049 1 << (PCIE_CAP_RCB (PcieLinkControl
) + 6)
4053 // Link Disable is reserved on
4055 // b) PCI Express to PCI/PCI-X bridges
4056 // c) Upstream Ports of Switches
4058 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4059 DevicePortType
!= PCIE_SWITCH_UPSTREAM_PORT
&&
4060 DevicePortType
!= PCIE_PCIE_TO_PCIX_BRIDGE
) {
4062 L
" Link Disable(4): %E%d%N\n",
4063 PCIE_CAP_LINK_DISABLE (PcieLinkControl
)
4067 L
" Common Clock Configuration(6): %E%d%N\n",
4068 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl
)
4071 L
" Extended Synch(7): %E%d%N\n",
4072 PCIE_CAP_EXT_SYNC (PcieLinkControl
)
4075 L
" Enable Clock Power Management(8): %E%d%N\n",
4076 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl
)
4079 L
" Hardware Autonomous Width Disable(9): %E%d%N\n",
4080 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl
)
4083 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",
4084 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl
)
4087 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",
4088 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl
)
4094 ExplainPcieLinkStatus (
4095 IN PCIE_CAP_STURCTURE
*PciExpressCap
4098 UINT16 PcieLinkStatus
;
4099 CHAR16
*SupLinkSpeeds
;
4101 PcieLinkStatus
= PciExpressCap
->LinkStatus
;
4102 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus
)) {
4104 SupLinkSpeeds
= L
"2.5 GT/s";
4107 SupLinkSpeeds
= L
"5.0 GT/s";
4110 SupLinkSpeeds
= L
"Reserved";
4114 L
" Current Link Speed(3:0): %E%s%N\n",
4118 L
" Negotiated Link Width(9:4): %Ex%d%N\n",
4119 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus
)
4122 L
" Link Training(11): %E%d%N\n",
4123 PCIE_CAP_LINK_TRAINING (PcieLinkStatus
)
4126 L
" Slot Clock Configuration(12): %E%d%N\n",
4127 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus
)
4130 L
" Data Link Layer Link Active(13): %E%d%N\n",
4131 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus
)
4134 L
" Link Bandwidth Management Status(14): %E%d%N\n",
4135 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus
)
4138 L
" Link Autonomous Bandwidth Status(15): %E%d%N\n",
4139 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus
)
4145 ExplainPcieSlotCap (
4146 IN PCIE_CAP_STURCTURE
*PciExpressCap
4151 PcieSlotCap
= PciExpressCap
->SlotCap
;
4154 L
" Attention Button Present(0): %E%d%N\n",
4155 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap
)
4158 L
" Power Controller Present(1): %E%d%N\n",
4159 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap
)
4162 L
" MRL Sensor Present(2): %E%d%N\n",
4163 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap
)
4166 L
" Attention Indicator Present(3): %E%d%N\n",
4167 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap
)
4170 L
" Power Indicator Present(4): %E%d%N\n",
4171 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap
)
4174 L
" Hot-Plug Surprise(5): %E%d%N\n",
4175 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap
)
4178 L
" Hot-Plug Capable(6): %E%d%N\n",
4179 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap
)
4182 L
" Slot Power Limit Value(14:7): %E0x%02x%N\n",
4183 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap
)
4186 L
" Slot Power Limit Scale(16:15): %E%s%N\n",
4187 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap
)]
4190 L
" Electromechanical Interlock Present(17): %E%d%N\n",
4191 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap
)
4194 L
" No Command Completed Support(18): %E%d%N\n",
4195 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap
)
4198 L
" Physical Slot Number(31:19): %E%d%N\n",
4199 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap
)
4206 ExplainPcieSlotControl (
4207 IN PCIE_CAP_STURCTURE
*PciExpressCap
4210 UINT16 PcieSlotControl
;
4212 PcieSlotControl
= PciExpressCap
->SlotControl
;
4214 L
" Attention Button Pressed Enable(0): %E%d%N\n",
4215 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl
)
4218 L
" Power Fault Detected Enable(1): %E%d%N\n",
4219 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl
)
4222 L
" MRL Sensor Changed Enable(2): %E%d%N\n",
4223 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl
)
4226 L
" Presence Detect Changed Enable(3): %E%d%N\n",
4227 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl
)
4230 L
" Command Completed Interrupt Enable(4): %E%d%N\n",
4231 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl
)
4234 L
" Hot-Plug Interrupt Enable(5): %E%d%N\n",
4235 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl
)
4238 L
" Attention Indicator Control(7:6): %E%s%N\n",
4239 IndicatorTable
[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl
)]
4242 L
" Power Indicator Control(9:8): %E%s%N\n",
4243 IndicatorTable
[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl
)]
4245 Print (L
" Power Controller Control(10): %EPower ");
4246 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl
)) {
4252 L
" Electromechanical Interlock Control(11): %E%d%N\n",
4253 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl
)
4256 L
" Data Link Layer State Changed Enable(12): %E%d%N\n",
4257 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl
)
4263 ExplainPcieSlotStatus (
4264 IN PCIE_CAP_STURCTURE
*PciExpressCap
4267 UINT16 PcieSlotStatus
;
4269 PcieSlotStatus
= PciExpressCap
->SlotStatus
;
4272 L
" Attention Button Pressed(0): %E%d%N\n",
4273 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus
)
4276 L
" Power Fault Detected(1): %E%d%N\n",
4277 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus
)
4280 L
" MRL Sensor Changed(2): %E%d%N\n",
4281 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus
)
4284 L
" Presence Detect Changed(3): %E%d%N\n",
4285 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus
)
4288 L
" Command Completed(4): %E%d%N\n",
4289 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus
)
4291 Print (L
" MRL Sensor State(5): %EMRL ");
4292 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus
)) {
4293 Print (L
" Opened%N\n");
4295 Print (L
" Closed%N\n");
4297 Print (L
" Presence Detect State(6): ");
4298 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus
)) {
4299 Print (L
"%ECard Present in slot%N\n");
4301 Print (L
"%ESlot Empty%N\n");
4303 Print (L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4304 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus
)) {
4305 Print (L
"Engaged%N\n");
4307 Print (L
"Disengaged%N\n");
4310 L
" Data Link Layer State Changed(8): %E%d%N\n",
4311 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus
)
4317 ExplainPcieRootControl (
4318 IN PCIE_CAP_STURCTURE
*PciExpressCap
4321 UINT16 PcieRootControl
;
4323 PcieRootControl
= PciExpressCap
->RootControl
;
4326 L
" System Error on Correctable Error Enable(0): %E%d%N\n",
4327 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl
)
4330 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\n",
4331 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl
)
4334 L
" System Error on Fatal Error Enable(2): %E%d%N\n",
4335 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl
)
4338 L
" PME Interrupt Enable(3): %E%d%N\n",
4339 PCIE_CAP_PME_INT_ENABLE (PcieRootControl
)
4342 L
" CRS Software Visibility Enable(4): %E%d%N\n",
4343 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl
)
4350 ExplainPcieRootCap (
4351 IN PCIE_CAP_STURCTURE
*PciExpressCap
4356 PcieRootCap
= PciExpressCap
->RsvdP
;
4359 L
" CRS Software Visibility(0): %E%d%N\n",
4360 PCIE_CAP_CRS_SW_VIS (PcieRootCap
)
4367 ExplainPcieRootStatus (
4368 IN PCIE_CAP_STURCTURE
*PciExpressCap
4371 UINT32 PcieRootStatus
;
4373 PcieRootStatus
= PciExpressCap
->RootStatus
;
4376 L
" PME Requester ID(15:0): %E0x%04x%N\n",
4377 PCIE_CAP_PME_REQ_ID (PcieRootStatus
)
4380 L
" PME Status(16): %E%d%N\n",
4381 PCIE_CAP_PME_STATUS (PcieRootStatus
)
4384 L
" PME Pending(17): %E%d%N\n",
4385 PCIE_CAP_PME_PENDING (PcieRootStatus
)
4391 PciExplainPciExpress (
4392 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
4394 IN UINT8 CapabilityPtr
4398 PCIE_CAP_STURCTURE PciExpressCap
;
4400 UINT64 CapRegAddress
;
4405 UINTN ExtendRegSize
;
4406 UINT64 Pciex_Address
;
4407 UINT8 DevicePortType
;
4412 CapRegAddress
= Address
+ CapabilityPtr
;
4417 sizeof (PciExpressCap
) / sizeof (UINT32
),
4421 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
.PcieCapReg
);
4423 Print (L
"\nPci Express device capability structure:\n");
4425 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
4426 if (ShellGetExecutionBreakFlag()) {
4429 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
4430 switch (PcieExplainList
[Index
].Width
) {
4431 case FieldWidthUINT8
:
4432 RegValue
= *(UINT8
*) RegAddr
;
4434 case FieldWidthUINT16
:
4435 RegValue
= *(UINT16
*) RegAddr
;
4437 case FieldWidthUINT32
:
4438 RegValue
= *(UINT32
*) RegAddr
;
4444 ShellPrintHiiEx(-1, -1, NULL
,
4445 PcieExplainList
[Index
].Token
,
4446 gShellDebug1HiiHandle
,
4447 PcieExplainList
[Index
].Offset
,
4450 if (PcieExplainList
[Index
].Func
== NULL
) {
4453 switch (PcieExplainList
[Index
].Type
) {
4454 case PcieExplainTypeLink
:
4456 // Link registers should not be used by
4457 // a) Root Complex Integrated Endpoint
4458 // b) Root Complex Event Collector
4460 if (DevicePortType
== PCIE_ROOT_COMPLEX_INTEGRATED_PORT
||
4461 DevicePortType
== PCIE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
4465 case PcieExplainTypeSlot
:
4467 // Slot registers are only valid for
4468 // a) Root Port of PCI Express Root Complex
4469 // b) Downstream Port of PCI Express Switch
4470 // and when SlotImplemented bit is set in PCIE cap register.
4472 if ((DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
&&
4473 DevicePortType
!= PCIE_SWITCH_DOWNSTREAM_PORT
) ||
4474 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap
.PcieCapReg
)) {
4478 case PcieExplainTypeRoot
:
4480 // Root registers are only valid for
4481 // Root Port of PCI Express Root Complex
4483 if (DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
) {
4490 PcieExplainList
[Index
].Func (&PciExpressCap
);
4493 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
4494 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
4495 Func
= (UINT8
) (RShiftU64 (Address
, 8));
4497 Pciex_Address
= CALC_EFI_PCIEX_ADDRESS (Bus
, Dev
, Func
, 0x100);
4499 ExtendRegSize
= 0x1000 - 0x100;
4501 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
4504 // PciRootBridgeIo protocol should support pci express extend space IO
4505 // (Begins at offset 0x100)
4507 Status
= IoDev
->Pci
.Read (
4511 (ExtendRegSize
) / sizeof (UINT32
),
4512 (VOID
*) (ExRegBuffer
)
4514 if (EFI_ERROR (Status
)) {
4515 FreePool ((VOID
*) ExRegBuffer
);
4516 return EFI_UNSUPPORTED
;
4519 // Start outputing PciEx extend space( 0xFF-0xFFF)
4521 Print (L
"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");
4527 (VOID
*) (ExRegBuffer
)
4530 FreePool ((VOID
*) ExRegBuffer
);