2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "UefiShellDebug1CommandsLib.h"
16 #include <Protocol/PciRootBridgeIo.h>
17 #include <Library/ShellLib.h>
18 #include <IndustryStandard/Pci.h>
19 #include <IndustryStandard/Acpi.h>
22 #define PCI_CLASS_STRING_LIMIT 54
24 // Printable strings for Pci class code
27 CHAR16
*BaseClass
; // Pointer to the PCI base class string
28 CHAR16
*SubClass
; // Pointer to the PCI sub class string
29 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
33 // a structure holding a single entry, which also points to its lower level
36 typedef struct PCI_CLASS_ENTRY_TAG
{
37 UINT8 Code
; // Class, subclass or I/F code
38 CHAR16
*DescText
; // Description string
39 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
43 // Declarations of entries which contain printable strings for class codes
44 // in PCI configuration space
46 PCI_CLASS_ENTRY PCIBlankEntry
[];
47 PCI_CLASS_ENTRY PCISubClass_00
[];
48 PCI_CLASS_ENTRY PCISubClass_01
[];
49 PCI_CLASS_ENTRY PCISubClass_02
[];
50 PCI_CLASS_ENTRY PCISubClass_03
[];
51 PCI_CLASS_ENTRY PCISubClass_04
[];
52 PCI_CLASS_ENTRY PCISubClass_05
[];
53 PCI_CLASS_ENTRY PCISubClass_06
[];
54 PCI_CLASS_ENTRY PCISubClass_07
[];
55 PCI_CLASS_ENTRY PCISubClass_08
[];
56 PCI_CLASS_ENTRY PCISubClass_09
[];
57 PCI_CLASS_ENTRY PCISubClass_0a
[];
58 PCI_CLASS_ENTRY PCISubClass_0b
[];
59 PCI_CLASS_ENTRY PCISubClass_0c
[];
60 PCI_CLASS_ENTRY PCISubClass_0d
[];
61 PCI_CLASS_ENTRY PCISubClass_0e
[];
62 PCI_CLASS_ENTRY PCISubClass_0f
[];
63 PCI_CLASS_ENTRY PCISubClass_10
[];
64 PCI_CLASS_ENTRY PCISubClass_11
[];
65 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
66 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
81 // Base class strings entries
83 PCI_CLASS_ENTRY gClassStringList
[] = {
91 L
"Mass Storage Controller",
96 L
"Network Controller",
101 L
"Display Controller",
106 L
"Multimedia Device",
111 L
"Memory Controller",
121 L
"Simple Communications Controllers",
126 L
"Base System Peripherals",
146 L
"Serial Bus Controllers",
151 L
"Wireless Controllers",
156 L
"Intelligent IO Controllers",
161 L
"Satellite Communications Controllers",
166 L
"Encryption/Decryption Controllers",
171 L
"Data Acquisition & Signal Processing Controllers",
176 L
"Device does not fit in any defined classes",
182 /* null string ends the list */NULL
187 // Subclass strings entries
189 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
198 /* null string ends the list */NULL
202 PCI_CLASS_ENTRY PCISubClass_00
[] = {
205 L
"All devices other than VGA",
210 L
"VGA-compatible devices",
216 /* null string ends the list */NULL
220 PCI_CLASS_ENTRY PCISubClass_01
[] = {
233 L
"Floppy disk controller",
248 L
"Other mass storage controller",
254 /* null string ends the list */NULL
258 PCI_CLASS_ENTRY PCISubClass_02
[] = {
261 L
"Ethernet controller",
266 L
"Token ring controller",
286 L
"Other network controller",
292 /* null string ends the list */NULL
296 PCI_CLASS_ENTRY PCISubClass_03
[] = {
299 L
"VGA/8514 controller",
314 L
"Other display controller",
320 /* null string ends the list */PCIBlankEntry
324 PCI_CLASS_ENTRY PCISubClass_04
[] = {
337 L
"Computer Telephony device",
342 L
"Other multimedia device",
348 /* null string ends the list */NULL
352 PCI_CLASS_ENTRY PCISubClass_05
[] = {
355 L
"RAM memory controller",
360 L
"Flash memory controller",
365 L
"Other memory controller",
371 /* null string ends the list */NULL
375 PCI_CLASS_ENTRY PCISubClass_06
[] = {
393 L
"PCI/Micro Channel bridge",
403 L
"PCI/PCMCIA bridge",
423 L
"Other bridge type",
429 /* null string ends the list */NULL
433 PCI_CLASS_ENTRY PCISubClass_07
[] = {
436 L
"Serial controller",
446 L
"Multiport serial controller",
456 L
"Other communication device",
462 /* null string ends the list */NULL
466 PCI_CLASS_ENTRY PCISubClass_08
[] = {
489 L
"Generic PCI Hot-Plug controller",
494 L
"Other system peripheral",
500 /* null string ends the list */NULL
504 PCI_CLASS_ENTRY PCISubClass_09
[] = {
507 L
"Keyboard controller",
522 L
"Scanner controller",
527 L
"Gameport controller",
532 L
"Other input controller",
538 /* null string ends the list */NULL
542 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
545 L
"Generic docking station",
550 L
"Other type of docking station",
556 /* null string ends the list */NULL
560 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
604 /* null string ends the list */NULL
608 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
611 L
"Firewire(IEEE 1394)",
636 L
"System Management Bus",
647 /* null string ends the list */NULL
651 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
654 L
"iRDA compatible controller",
659 L
"Consumer IR controller",
669 L
"Other type of wireless controller",
675 /* null string ends the list */NULL
679 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
688 /* null string ends the list */NULL
692 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
716 /* null string ends the list */NULL
720 PCI_CLASS_ENTRY PCISubClass_10
[] = {
723 L
"Network & computing Encrypt/Decrypt",
728 L
"Entertainment Encrypt/Decrypt",
733 L
"Other Encrypt/Decrypt",
739 /* null string ends the list */NULL
743 PCI_CLASS_ENTRY PCISubClass_11
[] = {
751 L
"Other DAQ & SP controllers",
757 /* null string ends the list */NULL
762 // Programming Interface entries
764 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
792 L
"OM-primary, OM-secondary",
797 L
"PI-primary, OM-secondary",
802 L
"OM/PI-primary, OM-secondary",
812 L
"OM-primary, PI-secondary",
817 L
"PI-primary, PI-secondary",
822 L
"OM/PI-primary, PI-secondary",
832 L
"OM-primary, OM/PI-secondary",
837 L
"PI-primary, OM/PI-secondary",
842 L
"OM/PI-primary, OM/PI-secondary",
852 L
"Master, OM-primary",
857 L
"Master, PI-primary",
862 L
"Master, OM/PI-primary",
867 L
"Master, OM-secondary",
872 L
"Master, OM-primary, OM-secondary",
877 L
"Master, PI-primary, OM-secondary",
882 L
"Master, OM/PI-primary, OM-secondary",
887 L
"Master, OM-secondary",
892 L
"Master, OM-primary, PI-secondary",
897 L
"Master, PI-primary, PI-secondary",
902 L
"Master, OM/PI-primary, PI-secondary",
907 L
"Master, OM-secondary",
912 L
"Master, OM-primary, OM/PI-secondary",
917 L
"Master, PI-primary, OM/PI-secondary",
922 L
"Master, OM/PI-primary, OM/PI-secondary",
928 /* null string ends the list */NULL
932 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
946 /* null string ends the list */NULL
950 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
958 L
"Subtractive decode",
964 /* null string ends the list */NULL
968 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
971 L
"Generic XT-compatible",
1001 L
"16950-compatible",
1007 /* null string ends the list */NULL
1011 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1024 L
"ECP 1.X-compliant",
1034 L
"IEEE 1284 target (not a controller)",
1040 /* null string ends the list */NULL
1044 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1052 L
"Hayes-compatible 16450",
1057 L
"Hayes-compatible 16550",
1062 L
"Hayes-compatible 16650",
1067 L
"Hayes-compatible 16750",
1073 /* null string ends the list */NULL
1077 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1100 L
"IO(x) APIC interrupt controller",
1106 /* null string ends the list */NULL
1110 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1129 /* null string ends the list */NULL
1133 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1152 /* null string ends the list */NULL
1156 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1175 /* null string ends the list */NULL
1179 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1193 /* null string ends the list */NULL
1197 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1200 L
"Universal Host Controller spec",
1205 L
"Open Host Controller spec",
1210 L
"No specific programming interface",
1215 L
"(Not Host Controller)",
1221 /* null string ends the list */NULL
1225 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1233 L
"Using 1394 OpenHCI spec",
1239 /* null string ends the list */NULL
1243 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1246 L
"Message FIFO at offset 40h",
1257 /* null string ends the list */NULL
1263 Generates printable Unicode strings that represent PCI device class,
1264 subclass and programmed I/F based on a value passed to the function.
1266 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1267 PCI device. The encodings are:
1268 bits 23:16 - Base Class Code
1269 bits 15:8 - Sub-Class Code
1270 bits 7:0 - Programming Interface
1271 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1272 printable class strings corresponding to ClassCode. The
1273 caller must not modify the strings that are pointed by
1274 the fields in ClassStrings.
1277 PciGetClassStrings (
1278 IN UINT32 ClassCode
,
1279 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1284 PCI_CLASS_ENTRY
*CurrentClass
;
1287 // Assume no strings found
1289 ClassStrings
->BaseClass
= L
"UNDEFINED";
1290 ClassStrings
->SubClass
= L
"UNDEFINED";
1291 ClassStrings
->PIFClass
= L
"UNDEFINED";
1293 CurrentClass
= gClassStringList
;
1294 Code
= (UINT8
) (ClassCode
>> 16);
1298 // Go through all entries of the base class, until the entry with a matching
1299 // base class code is found. If reaches an entry with a null description
1300 // text, the last entry is met, which means no text for the base class was
1301 // found, so no more action is needed.
1303 while (Code
!= CurrentClass
[Index
].Code
) {
1304 if (NULL
== CurrentClass
[Index
].DescText
) {
1311 // A base class was found. Assign description, and check if this class has
1312 // sub-class defined. If sub-class defined, no more action is needed,
1313 // otherwise, continue to find description for the sub-class code.
1315 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1316 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1320 // find Subclass entry
1322 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1323 Code
= (UINT8
) (ClassCode
>> 8);
1327 // Go through all entries of the sub-class, until the entry with a matching
1328 // sub-class code is found. If reaches an entry with a null description
1329 // text, the last entry is met, which means no text for the sub-class was
1330 // found, so no more action is needed.
1332 while (Code
!= CurrentClass
[Index
].Code
) {
1333 if (NULL
== CurrentClass
[Index
].DescText
) {
1340 // A class was found for the sub-class code. Assign description, and check if
1341 // this sub-class has programming interface defined. If no, no more action is
1342 // needed, otherwise, continue to find description for the programming
1345 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1346 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1350 // Find programming interface entry
1352 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1353 Code
= (UINT8
) ClassCode
;
1357 // Go through all entries of the I/F entries, until the entry with a
1358 // matching I/F code is found. If reaches an entry with a null description
1359 // text, the last entry is met, which means no text was found, so no more
1360 // action is needed.
1362 while (Code
!= CurrentClass
[Index
].Code
) {
1363 if (NULL
== CurrentClass
[Index
].DescText
) {
1370 // A class was found for the I/F code. Assign description, done!
1372 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1377 Print strings that represent PCI device class, subclass and programmed I/F.
1379 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1381 @param[in] IncludePIF If the printed string should include the programming I/F part
1385 IN UINT8
*ClassCodePtr
,
1386 IN BOOLEAN IncludePIF
1390 PCI_CLASS_STRINGS ClassStrings
;
1391 CHAR16 OutputString
[PCI_CLASS_STRING_LIMIT
+ 1];
1394 ClassCode
|= ClassCodePtr
[0];
1395 ClassCode
|= (ClassCodePtr
[1] << 8);
1396 ClassCode
|= (ClassCodePtr
[2] << 16);
1399 // Get name from class code
1401 PciGetClassStrings (ClassCode
, &ClassStrings
);
1405 // Only print base class and sub class name
1407 ShellPrintEx(-1,-1, L
"%s - %s - %s",
1408 ClassStrings
.BaseClass
,
1409 ClassStrings
.SubClass
,
1410 ClassStrings
.PIFClass
1415 // Print base class, sub class, and programming inferface name
1419 PCI_CLASS_STRING_LIMIT
* sizeof (CHAR16
),
1421 ClassStrings
.BaseClass
,
1422 ClassStrings
.SubClass
1425 OutputString
[PCI_CLASS_STRING_LIMIT
] = 0;
1426 ShellPrintEx(-1,-1, L
"%s", OutputString
);
1431 This function finds out the protocol which is in charge of the given
1432 segment, and its bus range covers the current bus number. It lookes
1433 each instances of RootBridgeIoProtocol handle, until the one meets the
1436 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1437 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1438 @param[in] Segment Segment number of device we are dealing with.
1439 @param[in] Bus Bus number of device we are dealing with.
1440 @param[out] IoDev Handle used to access configuration space of PCI device.
1442 @retval EFI_SUCCESS The command completed successfully.
1443 @retval EFI_INVALID_PARAMETER Invalid parameter.
1447 PciFindProtocolInterface (
1448 IN EFI_HANDLE
*HandleBuf
,
1449 IN UINTN HandleCount
,
1452 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1456 This function gets the protocol interface from the given handle, and
1457 obtains its address space descriptors.
1459 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1460 @param[out] IoDev Handle used to access configuration space of PCI device.
1461 @param[out] Descriptors Points to the address space descriptors.
1463 @retval EFI_SUCCESS The command completed successfully
1466 PciGetProtocolAndResource (
1467 IN EFI_HANDLE Handle
,
1468 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1469 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1473 This function get the next bus range of given address space descriptors.
1474 It also moves the pointer backward a node, to get prepared to be called
1477 @param[in, out] Descriptors Points to current position of a serial of address space
1479 @param[out] MinBus The lower range of bus number.
1480 @param[out] MaxBus The upper range of bus number.
1481 @param[out] IsEnd Meet end of the serial of descriptors.
1483 @retval EFI_SUCCESS The command completed successfully.
1486 PciGetNextBusRange (
1487 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1494 Explain the data in PCI configuration space. The part which is common for
1495 PCI device and bridge is interpreted in this function. It calls other
1496 functions to interpret data unique for device or bridge.
1498 @param[in] ConfigSpace Data in PCI configuration space.
1499 @param[in] Address Address used to access configuration space of this PCI device.
1500 @param[in] IoDev Handle used to access configuration space of PCI device.
1502 @retval EFI_SUCCESS The command completed successfully.
1506 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1508 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1512 Explain the device specific part of data in PCI configuration space.
1514 @param[in] Device Data in PCI configuration space.
1515 @param[in] Address Address used to access configuration space of this PCI device.
1516 @param[in] IoDev Handle used to access configuration space of PCI device.
1518 @retval EFI_SUCCESS The command completed successfully.
1521 PciExplainDeviceData (
1522 IN PCI_DEVICE_HEADER
*Device
,
1524 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1528 Explain the bridge specific part of data in PCI configuration space.
1530 @param[in] Bridge Bridge specific data region in PCI configuration space.
1531 @param[in] Address Address used to access configuration space of this PCI device.
1532 @param[in] IoDev Handle used to access configuration space of PCI device.
1534 @retval EFI_SUCCESS The command completed successfully.
1537 PciExplainBridgeData (
1538 IN PCI_BRIDGE_HEADER
*Bridge
,
1540 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1544 Explain the Base Address Register(Bar) in PCI configuration space.
1546 @param[in] Bar Points to the Base Address Register intended to interpret.
1547 @param[in] Command Points to the register Command.
1548 @param[in] Address Address used to access configuration space of this PCI device.
1549 @param[in] IoDev Handle used to access configuration space of PCI device.
1550 @param[in, out] Index The Index.
1552 @retval EFI_SUCCESS The command completed successfully.
1559 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1564 Explain the cardbus specific part of data in PCI configuration space.
1566 @param[in] CardBus CardBus specific region of PCI configuration space.
1567 @param[in] Address Address used to access configuration space of this PCI device.
1568 @param[in] IoDev Handle used to access configuration space of PCI device.
1570 @retval EFI_SUCCESS The command completed successfully.
1573 PciExplainCardBusData (
1574 IN PCI_CARDBUS_HEADER
*CardBus
,
1576 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1580 Explain each meaningful bit of register Status. The definition of Status is
1581 slightly different depending on the PCI header type.
1583 @param[in] Status Points to the content of register Status.
1584 @param[in] MainStatus Indicates if this register is main status(not secondary
1586 @param[in] HeaderType Header type of this PCI device.
1588 @retval EFI_SUCCESS The command completed successfully.
1593 IN BOOLEAN MainStatus
,
1594 IN PCI_HEADER_TYPE HeaderType
1598 Explain each meaningful bit of register Command.
1600 @param[in] Command Points to the content of register Command.
1602 @retval EFI_SUCCESS The command completed successfully.
1610 Explain each meaningful bit of register Bridge Control.
1612 @param[in] BridgeControl Points to the content of register Bridge Control.
1613 @param[in] HeaderType The headertype.
1615 @retval EFI_SUCCESS The command completed successfully.
1618 PciExplainBridgeControl (
1619 IN UINT16
*BridgeControl
,
1620 IN PCI_HEADER_TYPE HeaderType
1624 Print each capability structure.
1626 @param[in] IoDev The pointer to the deivce.
1627 @param[in] Address The address to start at.
1628 @param[in] CapPtr The offset from the address.
1630 @retval EFI_SUCCESS The operation was successful.
1633 PciExplainCapabilityStruct (
1634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1640 Display Pcie device structure.
1642 @param[in] IoDev The pointer to the root pci protocol.
1643 @param[in] Address The Address to start at.
1644 @param[in] CapabilityPtr The offset from the address to start.
1647 PciExplainPciExpress (
1648 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1650 IN UINT8 CapabilityPtr
1654 Print out information of the capability information.
1656 @param[in] PciExpressCap The pointer to the structure about the device.
1658 @retval EFI_SUCCESS The operation was successful.
1662 IN PCIE_CAP_STURCTURE
*PciExpressCap
1666 Print out information of the device capability information.
1668 @param[in] PciExpressCap The pointer to the structure about the device.
1670 @retval EFI_SUCCESS The operation was successful.
1673 ExplainPcieDeviceCap (
1674 IN PCIE_CAP_STURCTURE
*PciExpressCap
1678 Print out information of the device control information.
1680 @param[in] PciExpressCap The pointer to the structure about the device.
1682 @retval EFI_SUCCESS The operation was successful.
1685 ExplainPcieDeviceControl (
1686 IN PCIE_CAP_STURCTURE
*PciExpressCap
1690 Print out information of the device status information.
1692 @param[in] PciExpressCap The pointer to the structure about the device.
1694 @retval EFI_SUCCESS The operation was successful.
1697 ExplainPcieDeviceStatus (
1698 IN PCIE_CAP_STURCTURE
*PciExpressCap
1702 Print out information of the device link information.
1704 @param[in] PciExpressCap The pointer to the structure about the device.
1706 @retval EFI_SUCCESS The operation was successful.
1709 ExplainPcieLinkCap (
1710 IN PCIE_CAP_STURCTURE
*PciExpressCap
1714 Print out information of the device link control information.
1716 @param[in] PciExpressCap The pointer to the structure about the device.
1718 @retval EFI_SUCCESS The operation was successful.
1721 ExplainPcieLinkControl (
1722 IN PCIE_CAP_STURCTURE
*PciExpressCap
1726 Print out information of the device link status information.
1728 @param[in] PciExpressCap The pointer to the structure about the device.
1730 @retval EFI_SUCCESS The operation was successful.
1733 ExplainPcieLinkStatus (
1734 IN PCIE_CAP_STURCTURE
*PciExpressCap
1738 Print out information of the device slot information.
1740 @param[in] PciExpressCap The pointer to the structure about the device.
1742 @retval EFI_SUCCESS The operation was successful.
1745 ExplainPcieSlotCap (
1746 IN PCIE_CAP_STURCTURE
*PciExpressCap
1750 Print out information of the device slot control information.
1752 @param[in] PciExpressCap The pointer to the structure about the device.
1754 @retval EFI_SUCCESS The operation was successful.
1757 ExplainPcieSlotControl (
1758 IN PCIE_CAP_STURCTURE
*PciExpressCap
1762 Print out information of the device slot status information.
1764 @param[in] PciExpressCap The pointer to the structure about the device.
1766 @retval EFI_SUCCESS The operation was successful.
1769 ExplainPcieSlotStatus (
1770 IN PCIE_CAP_STURCTURE
*PciExpressCap
1774 Print out information of the device root information.
1776 @param[in] PciExpressCap The pointer to the structure about the device.
1778 @retval EFI_SUCCESS The operation was successful.
1781 ExplainPcieRootControl (
1782 IN PCIE_CAP_STURCTURE
*PciExpressCap
1786 Print out information of the device root capability information.
1788 @param[in] PciExpressCap The pointer to the structure about the device.
1790 @retval EFI_SUCCESS The operation was successful.
1793 ExplainPcieRootCap (
1794 IN PCIE_CAP_STURCTURE
*PciExpressCap
1798 Print out information of the device root status information.
1800 @param[in] PciExpressCap The pointer to the structure about the device.
1802 @retval EFI_SUCCESS The operation was successful.
1805 ExplainPcieRootStatus (
1806 IN PCIE_CAP_STURCTURE
*PciExpressCap
1809 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCIE_CAP_STURCTURE
*PciExpressCap
);
1815 } PCIE_CAPREG_FIELD_WIDTH
;
1818 PcieExplainTypeCommon
,
1819 PcieExplainTypeDevice
,
1820 PcieExplainTypeLink
,
1821 PcieExplainTypeSlot
,
1822 PcieExplainTypeRoot
,
1824 } PCIE_EXPLAIN_TYPE
;
1830 PCIE_CAPREG_FIELD_WIDTH Width
;
1831 PCIE_EXPLAIN_FUNCTION Func
;
1832 PCIE_EXPLAIN_TYPE Type
;
1833 } PCIE_EXPLAIN_STRUCT
;
1835 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
1837 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
1841 PcieExplainTypeCommon
1844 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
1848 PcieExplainTypeCommon
1851 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
1855 PcieExplainTypeCommon
1858 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
1861 ExplainPcieDeviceCap
,
1862 PcieExplainTypeDevice
1865 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
1868 ExplainPcieDeviceControl
,
1869 PcieExplainTypeDevice
1872 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
1875 ExplainPcieDeviceStatus
,
1876 PcieExplainTypeDevice
1879 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
1886 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
1889 ExplainPcieLinkControl
,
1893 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
1896 ExplainPcieLinkStatus
,
1900 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
1907 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
1910 ExplainPcieSlotControl
,
1914 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
1917 ExplainPcieSlotStatus
,
1921 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
1924 ExplainPcieRootControl
,
1928 STRING_TOKEN (STR_PCIEX_RSVDP
),
1935 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
1938 ExplainPcieRootStatus
,
1944 (PCIE_CAPREG_FIELD_WIDTH
)0,
1953 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
1954 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
1960 CHAR16
*DevicePortTypeTable
[] = {
1961 L
"PCI Express Endpoint",
1962 L
"Legacy PCI Express Endpoint",
1965 L
"Root Port of PCI Express Root Complex",
1966 L
"Upstream Port of PCI Express Switch",
1967 L
"Downstream Port of PCI Express Switch",
1968 L
"PCI Express to PCI/PCI-X Bridge",
1969 L
"PCI/PCI-X to PCI Express Bridge",
1970 L
"Root Complex Integrated Endpoint",
1971 L
"Root Complex Event Collector"
1974 CHAR16
*L0sLatencyStrTable
[] = {
1976 L
"64ns to less than 128ns",
1977 L
"128ns to less than 256ns",
1978 L
"256ns to less than 512ns",
1979 L
"512ns to less than 1us",
1980 L
"1us to less than 2us",
1985 CHAR16
*L1LatencyStrTable
[] = {
1987 L
"1us to less than 2us",
1988 L
"2us to less than 4us",
1989 L
"4us to less than 8us",
1990 L
"8us to less than 16us",
1991 L
"16us to less than 32us",
1996 CHAR16
*ASPMCtrlStrTable
[] = {
1998 L
"L0s Entry Enabled",
1999 L
"L1 Entry Enabled",
2000 L
"L0s and L1 Entry Enabled"
2003 CHAR16
*SlotPwrLmtScaleTable
[] = {
2010 CHAR16
*IndicatorTable
[] = {
2019 Function for 'pci' command.
2021 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2022 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2026 ShellCommandRunPci (
2027 IN EFI_HANDLE ImageHandle
,
2028 IN EFI_SYSTEM_TABLE
*SystemTable
2036 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2038 PCI_COMMON_HEADER PciHeader
;
2039 PCI_CONFIG_SPACE ConfigSpace
;
2043 BOOLEAN ExplainData
;
2047 UINTN HandleBufSize
;
2048 EFI_HANDLE
*HandleBuf
;
2050 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2054 LIST_ENTRY
*Package
;
2055 CHAR16
*ProblemParam
;
2056 SHELL_STATUS ShellStatus
;
2060 ShellStatus
= SHELL_SUCCESS
;
2061 Status
= EFI_SUCCESS
;
2069 // initialize the shell lib (we must be in non-auto-init...)
2071 Status
= ShellInitialize();
2072 ASSERT_EFI_ERROR(Status
);
2074 Status
= CommandInit();
2075 ASSERT_EFI_ERROR(Status
);
2078 // parse the command line
2080 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2081 if (EFI_ERROR(Status
)) {
2082 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2083 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, ProblemParam
);
2084 FreePool(ProblemParam
);
2085 ShellStatus
= SHELL_INVALID_PARAMETER
;
2091 if (ShellCommandLineGetCount(Package
) == 2) {
2092 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
);
2093 ShellStatus
= SHELL_INVALID_PARAMETER
;
2097 if (ShellCommandLineGetCount(Package
) > 4) {
2098 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
);
2099 ShellStatus
= SHELL_INVALID_PARAMETER
;
2102 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2103 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"-s");
2104 ShellStatus
= SHELL_INVALID_PARAMETER
;
2108 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2109 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2110 // space for handles and call it again.
2112 HandleBufSize
= sizeof (EFI_HANDLE
);
2113 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2114 if (HandleBuf
== NULL
) {
2115 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2116 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2120 Status
= gBS
->LocateHandle (
2122 &gEfiPciRootBridgeIoProtocolGuid
,
2128 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2129 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2130 if (HandleBuf
== NULL
) {
2131 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2132 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2136 Status
= gBS
->LocateHandle (
2138 &gEfiPciRootBridgeIoProtocolGuid
,
2145 if (EFI_ERROR (Status
)) {
2146 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
);
2147 ShellStatus
= SHELL_NOT_FOUND
;
2151 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2153 // Argument Count == 1(no other argument): enumerate all pci functions
2155 if (ShellCommandLineGetCount(Package
) == 1) {
2156 gST
->ConOut
->QueryMode (
2158 gST
->ConOut
->Mode
->Mode
,
2165 if ((ScreenSize
& 1) == 1) {
2172 // For each handle, which decides a segment and a bus number range,
2173 // enumerate all devices on it.
2175 for (Index
= 0; Index
< HandleCount
; Index
++) {
2176 Status
= PciGetProtocolAndResource (
2181 if (EFI_ERROR (Status
)) {
2182 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, Status
);
2183 ShellStatus
= SHELL_NOT_FOUND
;
2187 // No document say it's impossible for a RootBridgeIo protocol handle
2188 // to have more than one address space descriptors, so find out every
2189 // bus range and for each of them do device enumeration.
2192 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2194 if (EFI_ERROR (Status
)) {
2195 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, Status
);
2196 ShellStatus
= SHELL_NOT_FOUND
;
2204 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2206 // For each devices, enumerate all functions it contains
2208 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2210 // For each function, read its configuration space and print summary
2212 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2213 if (ShellGetExecutionBreakFlag ()) {
2214 ShellStatus
= SHELL_ABORTED
;
2217 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2227 // If VendorId = 0xffff, there does not exist a device at this
2228 // location. For each device, if there is any function on it,
2229 // there must be 1 function at Function 0. So if Func = 0, there
2230 // will be no more functions in the same device, so we can break
2231 // loop to deal with the next device.
2233 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2237 if (PciHeader
.VendorId
!= 0xffff) {
2240 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2248 sizeof (PciHeader
) / sizeof (UINT32
),
2253 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2254 IoDev
->SegmentNumber
,
2260 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2262 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2265 PciHeader
.ClassCode
[0]
2269 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2271 // If ScreenSize == 0 we have the console redirected so don't
2277 // If this is not a multi-function device, we can leave the loop
2278 // to deal with the next device.
2280 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2288 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2289 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2290 // devices on all bus, we can leave loop.
2292 if (Descriptors
== NULL
) {
2298 Status
= EFI_SUCCESS
;
2302 ExplainData
= FALSE
;
2307 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2311 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2313 Segment
= (UINT16
) ShellStrToUintn (Temp
);
2317 // The first Argument(except "-i") is assumed to be Bus number, second
2318 // to be Device number, and third to be Func number.
2320 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2322 Bus
= (UINT16
)ShellStrToUintn(Temp
);
2323 if (Bus
> MAX_BUS_NUMBER
) {
2324 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2325 ShellStatus
= SHELL_INVALID_PARAMETER
;
2329 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2331 Device
= (UINT16
) ShellStrToUintn(Temp
);
2332 if (Device
> MAX_DEVICE_NUMBER
){
2333 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2334 ShellStatus
= SHELL_INVALID_PARAMETER
;
2339 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2341 Func
= (UINT16
) ShellStrToUintn(Temp
);
2342 if (Func
> MAX_FUNCTION_NUMBER
){
2343 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2344 ShellStatus
= SHELL_INVALID_PARAMETER
;
2350 // Find the protocol interface who's in charge of current segment, and its
2351 // bus range covers the current bus
2353 Status
= PciFindProtocolInterface (
2361 if (EFI_ERROR (Status
)) {
2363 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
,
2364 gShellDebug1HiiHandle
,
2368 ShellStatus
= SHELL_NOT_FOUND
;
2372 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2373 Status
= IoDev
->Pci
.Read (
2377 sizeof (ConfigSpace
),
2381 if (EFI_ERROR (Status
)) {
2382 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, Status
);
2383 ShellStatus
= SHELL_ACCESS_DENIED
;
2387 mConfigSpace
= &ConfigSpace
;
2392 STRING_TOKEN (STR_PCI_INFO
),
2393 gShellDebug1HiiHandle
,
2405 // Dump standard header of configuration space
2407 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2409 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2410 ShellPrintEx(-1,-1, L
"\r\n");
2413 // Dump device dependent Part of configuration space
2418 sizeof (ConfigSpace
) - SizeOfHeader
,
2423 // If "-i" appears in command line, interpret data in configuration space
2426 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
);
2430 if (HandleBuf
!= NULL
) {
2431 FreePool (HandleBuf
);
2433 if (Package
!= NULL
) {
2434 ShellCommandLineFreeVarList (Package
);
2436 mConfigSpace
= NULL
;
2441 This function finds out the protocol which is in charge of the given
2442 segment, and its bus range covers the current bus number. It lookes
2443 each instances of RootBridgeIoProtocol handle, until the one meets the
2446 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2447 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2448 @param[in] Segment Segment number of device we are dealing with.
2449 @param[in] Bus Bus number of device we are dealing with.
2450 @param[out] IoDev Handle used to access configuration space of PCI device.
2452 @retval EFI_SUCCESS The command completed successfully.
2453 @retval EFI_INVALID_PARAMETER Invalid parameter.
2457 PciFindProtocolInterface (
2458 IN EFI_HANDLE
*HandleBuf
,
2459 IN UINTN HandleCount
,
2462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2467 BOOLEAN FoundInterface
;
2468 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2473 FoundInterface
= FALSE
;
2475 // Go through all handles, until the one meets the criteria is found
2477 for (Index
= 0; Index
< HandleCount
; Index
++) {
2478 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2479 if (EFI_ERROR (Status
)) {
2483 // When Descriptors == NULL, the Configuration() is not implemented,
2484 // so we only check the Segment number
2486 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2490 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2495 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2496 if (EFI_ERROR (Status
)) {
2504 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2505 FoundInterface
= TRUE
;
2511 if (FoundInterface
) {
2514 return EFI_INVALID_PARAMETER
;
2519 This function gets the protocol interface from the given handle, and
2520 obtains its address space descriptors.
2522 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2523 @param[out] IoDev Handle used to access configuration space of PCI device.
2524 @param[out] Descriptors Points to the address space descriptors.
2526 @retval EFI_SUCCESS The command completed successfully
2529 PciGetProtocolAndResource (
2530 IN EFI_HANDLE Handle
,
2531 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
2532 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
2538 // Get inferface from protocol
2540 Status
= gBS
->HandleProtocol (
2542 &gEfiPciRootBridgeIoProtocolGuid
,
2546 if (EFI_ERROR (Status
)) {
2550 // Call Configuration() to get address space descriptors
2552 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
2553 if (Status
== EFI_UNSUPPORTED
) {
2554 *Descriptors
= NULL
;
2563 This function get the next bus range of given address space descriptors.
2564 It also moves the pointer backward a node, to get prepared to be called
2567 @param[in, out] Descriptors Points to current position of a serial of address space
2569 @param[out] MinBus The lower range of bus number.
2570 @param[out] MaxBus The upper range of bus number.
2571 @param[out] IsEnd Meet end of the serial of descriptors.
2573 @retval EFI_SUCCESS The command completed successfully.
2576 PciGetNextBusRange (
2577 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2586 // When *Descriptors is NULL, Configuration() is not implemented, so assume
2587 // range is 0~PCI_MAX_BUS
2589 if ((*Descriptors
) == NULL
) {
2591 *MaxBus
= PCI_MAX_BUS
;
2595 // *Descriptors points to one or more address space descriptors, which
2596 // ends with a end tagged descriptor. Examine each of the descriptors,
2597 // if a bus typed one is found and its bus range covers bus, this handle
2598 // is the handle we are looking for.
2601 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2602 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2603 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2604 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2606 return (EFI_SUCCESS
);
2612 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
2620 Explain the data in PCI configuration space. The part which is common for
2621 PCI device and bridge is interpreted in this function. It calls other
2622 functions to interpret data unique for device or bridge.
2624 @param[in] ConfigSpace Data in PCI configuration space.
2625 @param[in] Address Address used to access configuration space of this PCI device.
2626 @param[in] IoDev Handle used to access configuration space of PCI device.
2628 @retval EFI_SUCCESS The command completed successfully.
2632 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2637 PCI_COMMON_HEADER
*Common
;
2638 PCI_HEADER_TYPE HeaderType
;
2642 Common
= &(ConfigSpace
->Common
);
2647 // Print Vendor Id and Device Id
2649 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
2650 INDEX_OF (&(Common
->VendorId
)),
2652 INDEX_OF (&(Common
->DeviceId
)),
2657 // Print register Command
2659 PciExplainCommand (&(Common
->Command
));
2662 // Print register Status
2664 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
2667 // Print register Revision ID
2669 ShellPrintEx(-1, -1, L
"/r/n");
2670 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
2671 INDEX_OF (&(Common
->RevisionId
)),
2676 // Print register BIST
2678 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->Bist
)));
2679 if ((Common
->Bist
& PCI_BIT_7
) != 0) {
2680 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->Bist
);
2682 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
2685 // Print register Cache Line Size
2687 ShellPrintHiiEx(-1, -1, NULL
,
2688 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
2689 gShellDebug1HiiHandle
,
2690 INDEX_OF (&(Common
->CacheLineSize
)),
2691 Common
->CacheLineSize
2695 // Print register Latency Timer
2697 ShellPrintHiiEx(-1, -1, NULL
,
2698 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
2699 gShellDebug1HiiHandle
,
2700 INDEX_OF (&(Common
->PrimaryLatencyTimer
)),
2701 Common
->PrimaryLatencyTimer
2705 // Print register Header Type
2707 ShellPrintHiiEx(-1, -1, NULL
,
2708 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
2709 gShellDebug1HiiHandle
,
2710 INDEX_OF (&(Common
->HeaderType
)),
2714 if ((Common
->HeaderType
& PCI_BIT_7
) != 0) {
2715 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
2718 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
2721 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
2722 switch (HeaderType
) {
2724 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
2728 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
2731 case PciCardBusBridge
:
2732 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
2736 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
2737 HeaderType
= PciUndefined
;
2741 // Print register Class Code
2743 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
2744 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
2747 if (ShellGetExecutionBreakFlag()) {
2752 // Interpret remaining part of PCI configuration header depending on
2756 Status
= EFI_SUCCESS
;
2757 switch (HeaderType
) {
2759 Status
= PciExplainDeviceData (
2760 &(ConfigSpace
->NonCommon
.Device
),
2764 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilitiesPtr
;
2768 Status
= PciExplainBridgeData (
2769 &(ConfigSpace
->NonCommon
.Bridge
),
2773 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilitiesPtr
;
2776 case PciCardBusBridge
:
2777 Status
= PciExplainCardBusData (
2778 &(ConfigSpace
->NonCommon
.CardBus
),
2782 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.CapabilitiesPtr
;
2789 // If Status bit4 is 1, dump or explain capability structure
2791 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
2792 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
);
2799 Explain the device specific part of data in PCI configuration space.
2801 @param[in] Device Data in PCI configuration space.
2802 @param[in] Address Address used to access configuration space of this PCI device.
2803 @param[in] IoDev Handle used to access configuration space of PCI device.
2805 @retval EFI_SUCCESS The command completed successfully.
2808 PciExplainDeviceData (
2809 IN PCI_DEVICE_HEADER
*Device
,
2811 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2820 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
2821 // exist. If these no Bar for this function, print "none", otherwise
2822 // list detail information about this Bar.
2824 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
2827 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
2828 for (Index
= 0; Index
< BarCount
; Index
++) {
2829 if (Device
->Bar
[Index
] == 0) {
2835 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
2836 Print (L
" --------------------------------------------------------------------------");
2839 Status
= PciExplainBar (
2840 &(Device
->Bar
[Index
]),
2841 &(mConfigSpace
->Common
.Command
),
2847 if (EFI_ERROR (Status
)) {
2853 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
2856 Print (L
"\n --------------------------------------------------------------------------");
2860 // Print register Expansion ROM Base Address
2862 if ((Device
->ROMBar
& PCI_BIT_0
) == 0) {
2863 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ROMBar
)));
2866 ShellPrintHiiEx(-1, -1, NULL
,
2867 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
2868 gShellDebug1HiiHandle
,
2869 INDEX_OF (&(Device
->ROMBar
)),
2874 // Print register Cardbus CIS ptr
2876 ShellPrintHiiEx(-1, -1, NULL
,
2877 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
2878 gShellDebug1HiiHandle
,
2879 INDEX_OF (&(Device
->CardBusCISPtr
)),
2880 Device
->CardBusCISPtr
2884 // Print register Sub-vendor ID and subsystem ID
2886 ShellPrintHiiEx(-1, -1, NULL
,
2887 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
2888 gShellDebug1HiiHandle
,
2889 INDEX_OF (&(Device
->SubVendorId
)),
2893 ShellPrintHiiEx(-1, -1, NULL
,
2894 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
2895 gShellDebug1HiiHandle
,
2896 INDEX_OF (&(Device
->SubSystemId
)),
2901 // Print register Capabilities Ptr
2903 ShellPrintHiiEx(-1, -1, NULL
,
2904 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
2905 gShellDebug1HiiHandle
,
2906 INDEX_OF (&(Device
->CapabilitiesPtr
)),
2907 Device
->CapabilitiesPtr
2911 // Print register Interrupt Line and interrupt pin
2913 ShellPrintHiiEx(-1, -1, NULL
,
2914 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
2915 gShellDebug1HiiHandle
,
2916 INDEX_OF (&(Device
->InterruptLine
)),
2917 Device
->InterruptLine
2920 ShellPrintHiiEx(-1, -1, NULL
,
2921 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
2922 gShellDebug1HiiHandle
,
2923 INDEX_OF (&(Device
->InterruptPin
)),
2924 Device
->InterruptPin
2928 // Print register Min_Gnt and Max_Lat
2930 ShellPrintHiiEx(-1, -1, NULL
,
2931 STRING_TOKEN (STR_PCI2_MIN_GNT
),
2932 gShellDebug1HiiHandle
,
2933 INDEX_OF (&(Device
->MinGnt
)),
2937 ShellPrintHiiEx(-1, -1, NULL
,
2938 STRING_TOKEN (STR_PCI2_MAX_LAT
),
2939 gShellDebug1HiiHandle
,
2940 INDEX_OF (&(Device
->MaxLat
)),
2948 Explain the bridge specific part of data in PCI configuration space.
2950 @param[in] Bridge Bridge specific data region in PCI configuration space.
2951 @param[in] Address Address used to access configuration space of this PCI device.
2952 @param[in] IoDev Handle used to access configuration space of PCI device.
2954 @retval EFI_SUCCESS The command completed successfully.
2957 PciExplainBridgeData (
2958 IN PCI_BRIDGE_HEADER
*Bridge
,
2960 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2970 // Print Base Address Registers. When Bar = 0, this Bar does not
2971 // exist. If these no Bar for this function, print "none", otherwise
2972 // list detail information about this Bar.
2974 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
2977 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
2979 for (Index
= 0; Index
< BarCount
; Index
++) {
2980 if (Bridge
->Bar
[Index
] == 0) {
2986 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
2987 Print (L
" --------------------------------------------------------------------------");
2990 Status
= PciExplainBar (
2991 &(Bridge
->Bar
[Index
]),
2992 &(mConfigSpace
->Common
.Command
),
2998 if (EFI_ERROR (Status
)) {
3004 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3006 Print (L
"\n --------------------------------------------------------------------------");
3010 // Expansion register ROM Base Address
3012 if ((Bridge
->ROMBar
& PCI_BIT_0
) == 0) {
3013 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ROMBar
)));
3016 ShellPrintHiiEx(-1, -1, NULL
,
3017 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3018 gShellDebug1HiiHandle
,
3019 INDEX_OF (&(Bridge
->ROMBar
)),
3024 // Print Bus Numbers(Primary, Secondary, and Subordinate
3026 ShellPrintHiiEx(-1, -1, NULL
,
3027 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3028 gShellDebug1HiiHandle
,
3029 INDEX_OF (&(Bridge
->PrimaryBus
)),
3030 INDEX_OF (&(Bridge
->SecondaryBus
)),
3031 INDEX_OF (&(Bridge
->SubordinateBus
))
3034 Print (L
" ------------------------------------------------------\n");
3036 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3037 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3038 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3041 // Print register Secondary Latency Timer
3043 ShellPrintHiiEx(-1, -1, NULL
,
3044 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3045 gShellDebug1HiiHandle
,
3046 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3047 Bridge
->SecondaryLatencyTimer
3051 // Print register Secondary Status
3053 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3056 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3057 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3058 // base and limit address are listed.
3060 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3061 Print (L
"----------------------------------------------------------------------\n");
3066 IoAddress32
= (Bridge
->IoBaseUpper
<< 16 | Bridge
->IoBase
<< 8);
3067 IoAddress32
&= 0xfffff000;
3068 ShellPrintHiiEx(-1, -1, NULL
,
3069 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3070 gShellDebug1HiiHandle
,
3071 INDEX_OF (&(Bridge
->IoBase
)),
3075 IoAddress32
= (Bridge
->IoLimitUpper
<< 16 | Bridge
->IoLimit
<< 8);
3076 IoAddress32
|= 0x00000fff;
3077 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3080 // Memory Base & Limit
3082 ShellPrintHiiEx(-1, -1, NULL
,
3083 STRING_TOKEN (STR_PCI2_MEMORY
),
3084 gShellDebug1HiiHandle
,
3085 INDEX_OF (&(Bridge
->MemoryBase
)),
3086 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3089 ShellPrintHiiEx(-1, -1, NULL
,
3090 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3091 gShellDebug1HiiHandle
,
3092 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3096 // Pre-fetch-able Memory Base & Limit
3098 ShellPrintHiiEx(-1, -1, NULL
,
3099 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3100 gShellDebug1HiiHandle
,
3101 INDEX_OF (&(Bridge
->PrefetchableMemBase
)),
3102 Bridge
->PrefetchableBaseUpper
,
3103 (Bridge
->PrefetchableMemBase
<< 16) & 0xfff00000
3106 ShellPrintHiiEx(-1, -1, NULL
,
3107 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3108 gShellDebug1HiiHandle
,
3109 Bridge
->PrefetchableLimitUpper
,
3110 (Bridge
->PrefetchableMemLimit
<< 16) | 0x000fffff
3114 // Print register Capabilities Pointer
3116 ShellPrintHiiEx(-1, -1, NULL
,
3117 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3118 gShellDebug1HiiHandle
,
3119 INDEX_OF (&(Bridge
->CapabilitiesPtr
)),
3120 Bridge
->CapabilitiesPtr
3124 // Print register Bridge Control
3126 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3129 // Print register Interrupt Line & PIN
3131 ShellPrintHiiEx(-1, -1, NULL
,
3132 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3133 gShellDebug1HiiHandle
,
3134 INDEX_OF (&(Bridge
->InterruptLine
)),
3135 Bridge
->InterruptLine
3138 ShellPrintHiiEx(-1, -1, NULL
,
3139 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3140 gShellDebug1HiiHandle
,
3141 INDEX_OF (&(Bridge
->InterruptPin
)),
3142 Bridge
->InterruptPin
3149 Explain the Base Address Register(Bar) in PCI configuration space.
3151 @param[in] Bar Points to the Base Address Register intended to interpret.
3152 @param[in] Command Points to the register Command.
3153 @param[in] Address Address used to access configuration space of this PCI device.
3154 @param[in] IoDev Handle used to access configuration space of PCI device.
3155 @param[in, out] Index The Index.
3157 @retval EFI_SUCCESS The command completed successfully.
3164 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3185 // According the bar type, list detail about this bar, for example: 32 or
3186 // 64 bits; pre-fetchable or not.
3188 if ((*Bar
& PCI_BIT_0
) == 0) {
3190 // This bar is of memory type
3194 if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) == 0) {
3195 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3196 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3197 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3199 } else if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) != 0) {
3201 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3202 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3203 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3204 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3205 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3213 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3214 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3217 if ((*Bar
& PCI_BIT_3
) == 0) {
3218 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3221 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3226 // This bar is of io type
3229 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3234 // Get BAR length(or the amount of resource this bar demands for). To get
3235 // Bar length, first we should temporarily disable I/O and memory access
3236 // of this function(by set bits in the register Command), then write all
3237 // "1"s to this bar. The bar value read back is the amount of resource
3238 // this bar demands for.
3241 // Disable io & mem access
3243 OldCommand
= *Command
;
3244 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3245 RegAddress
= Address
| INDEX_OF (Command
);
3246 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3248 RegAddress
= Address
| INDEX_OF (Bar
);
3251 // Read after write the BAR to get the size
3255 NewBar32
= 0xffffffff;
3257 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3258 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3259 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3262 NewBar32
= NewBar32
& 0xfffffff0;
3263 NewBar32
= (~NewBar32
) + 1;
3266 NewBar32
= NewBar32
& 0xfffffffc;
3267 NewBar32
= (~NewBar32
) + 1;
3268 NewBar32
= NewBar32
& 0x0000ffff;
3273 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3274 NewBar64
= 0xffffffffffffffffULL
;
3276 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3277 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3278 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3281 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3282 NewBar64
= (~NewBar64
) + 1;
3285 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3286 NewBar64
= (~NewBar64
) + 1;
3287 NewBar64
= NewBar64
& 0x000000000000ffff;
3291 // Enable io & mem access
3293 RegAddress
= Address
| INDEX_OF (Command
);
3294 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3298 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3299 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3302 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, RShiftU64 (NewBar64
, 32));
3303 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3305 ShellPrintHiiEx(-1, -1, NULL
,
3306 STRING_TOKEN (STR_PCI2_RSHIFT
),
3307 gShellDebug1HiiHandle
,
3308 RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3310 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3314 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3315 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3322 Explain the cardbus specific part of data in PCI configuration space.
3324 @param[in] CardBus CardBus specific region of PCI configuration space.
3325 @param[in] Address Address used to access configuration space of this PCI device.
3326 @param[in] IoDev Handle used to access configuration space of PCI device.
3328 @retval EFI_SUCCESS The command completed successfully.
3331 PciExplainCardBusData (
3332 IN PCI_CARDBUS_HEADER
*CardBus
,
3334 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3338 PCI_CARDBUS_DATA
*CardBusData
;
3340 ShellPrintHiiEx(-1, -1, NULL
,
3341 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3342 gShellDebug1HiiHandle
,
3343 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3344 CardBus
->CardBusSocketReg
3348 // Print Secondary Status
3350 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3353 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3354 // Subordinate bus number
3356 ShellPrintHiiEx(-1, -1, NULL
,
3357 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3358 gShellDebug1HiiHandle
,
3359 INDEX_OF (&(CardBus
->PciBusNumber
)),
3360 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3361 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3364 Print (L
" ------------------------------------------------------\n");
3366 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3367 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3368 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3371 // Print CardBus Latency Timer
3373 ShellPrintHiiEx(-1, -1, NULL
,
3374 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3375 gShellDebug1HiiHandle
,
3376 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3377 CardBus
->CardBusLatencyTimer
3381 // Print Memory/Io ranges this cardbus bridge forwards
3383 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3384 Print (L
"----------------------------------------------------------------------\n");
3386 ShellPrintHiiEx(-1, -1, NULL
,
3387 STRING_TOKEN (STR_PCI2_MEM_3
),
3388 gShellDebug1HiiHandle
,
3389 INDEX_OF (&(CardBus
->MemoryBase0
)),
3390 CardBus
->BridgeControl
& PCI_BIT_8
? L
" Prefetchable" : L
"Non-Prefetchable",
3391 CardBus
->MemoryBase0
& 0xfffff000,
3392 CardBus
->MemoryLimit0
| 0x00000fff
3395 ShellPrintHiiEx(-1, -1, NULL
,
3396 STRING_TOKEN (STR_PCI2_MEM_3
),
3397 gShellDebug1HiiHandle
,
3398 INDEX_OF (&(CardBus
->MemoryBase1
)),
3399 CardBus
->BridgeControl
& PCI_BIT_9
? L
" Prefetchable" : L
"Non-Prefetchable",
3400 CardBus
->MemoryBase1
& 0xfffff000,
3401 CardBus
->MemoryLimit1
| 0x00000fff
3404 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& PCI_BIT_0
);
3405 ShellPrintHiiEx(-1, -1, NULL
,
3406 STRING_TOKEN (STR_PCI2_IO_2
),
3407 gShellDebug1HiiHandle
,
3408 INDEX_OF (&(CardBus
->IoBase0
)),
3409 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3410 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3411 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3414 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& PCI_BIT_0
);
3415 ShellPrintHiiEx(-1, -1, NULL
,
3416 STRING_TOKEN (STR_PCI2_IO_2
),
3417 gShellDebug1HiiHandle
,
3418 INDEX_OF (&(CardBus
->IoBase1
)),
3419 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3420 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3421 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3425 // Print register Interrupt Line & PIN
3427 ShellPrintHiiEx(-1, -1, NULL
,
3428 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3429 gShellDebug1HiiHandle
,
3430 INDEX_OF (&(CardBus
->InterruptLine
)),
3431 CardBus
->InterruptLine
,
3432 INDEX_OF (&(CardBus
->InterruptPin
)),
3433 CardBus
->InterruptPin
3437 // Print register Bridge Control
3439 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3442 // Print some registers in data region of PCI configuration space for cardbus
3443 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3446 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_HEADER
));
3448 ShellPrintHiiEx(-1, -1, NULL
,
3449 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3450 gShellDebug1HiiHandle
,
3451 INDEX_OF (&(CardBusData
->SubVendorId
)),
3452 CardBusData
->SubVendorId
,
3453 INDEX_OF (&(CardBusData
->SubSystemId
)),
3454 CardBusData
->SubSystemId
3457 ShellPrintHiiEx(-1, -1, NULL
,
3458 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3459 gShellDebug1HiiHandle
,
3460 INDEX_OF (&(CardBusData
->LegacyBase
)),
3461 CardBusData
->LegacyBase
3468 Explain each meaningful bit of register Status. The definition of Status is
3469 slightly different depending on the PCI header type.
3471 @param[in] Status Points to the content of register Status.
3472 @param[in] MainStatus Indicates if this register is main status(not secondary
3474 @param[in] HeaderType Header type of this PCI device.
3476 @retval EFI_SUCCESS The command completed successfully.
3481 IN BOOLEAN MainStatus
,
3482 IN PCI_HEADER_TYPE HeaderType
3486 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3489 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3492 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_4
) != 0);
3495 // Bit 5 is meaningless for CardBus Bridge
3497 if (HeaderType
== PciCardBusBridge
) {
3498 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3501 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3504 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_7
) != 0);
3506 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_8
) != 0);
3508 // Bit 9 and bit 10 together decides the DEVSEL timing
3510 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3511 if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) == 0) {
3512 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3514 } else if ((*Status
& PCI_BIT_9
) != 0 && (*Status
& PCI_BIT_10
) == 0) {
3515 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3517 } else if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) != 0) {
3518 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3521 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3524 ShellPrintHiiEx(-1, -1, NULL
,
3525 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3526 gShellDebug1HiiHandle
,
3527 (*Status
& PCI_BIT_11
) != 0
3530 ShellPrintHiiEx(-1, -1, NULL
,
3531 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3532 gShellDebug1HiiHandle
,
3533 (*Status
& PCI_BIT_12
) != 0
3536 ShellPrintHiiEx(-1, -1, NULL
,
3537 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3538 gShellDebug1HiiHandle
,
3539 (*Status
& PCI_BIT_13
) != 0
3543 ShellPrintHiiEx(-1, -1, NULL
,
3544 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
3545 gShellDebug1HiiHandle
,
3546 (*Status
& PCI_BIT_14
) != 0
3550 ShellPrintHiiEx(-1, -1, NULL
,
3551 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
3552 gShellDebug1HiiHandle
,
3553 (*Status
& PCI_BIT_14
) != 0
3557 ShellPrintHiiEx(-1, -1, NULL
,
3558 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
3559 gShellDebug1HiiHandle
,
3560 (*Status
& PCI_BIT_15
) != 0
3567 Explain each meaningful bit of register Command.
3569 @param[in] Command Points to the content of register Command.
3571 @retval EFI_SUCCESS The command completed successfully.
3579 // Print the binary value of register Command
3581 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
3584 // Explain register Command bit by bit
3586 ShellPrintHiiEx(-1, -1, NULL
,
3587 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
3588 gShellDebug1HiiHandle
,
3589 (*Command
& PCI_BIT_0
) != 0
3592 ShellPrintHiiEx(-1, -1, NULL
,
3593 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
3594 gShellDebug1HiiHandle
,
3595 (*Command
& PCI_BIT_1
) != 0
3598 ShellPrintHiiEx(-1, -1, NULL
,
3599 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
3600 gShellDebug1HiiHandle
,
3601 (*Command
& PCI_BIT_2
) != 0
3604 ShellPrintHiiEx(-1, -1, NULL
,
3605 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
3606 gShellDebug1HiiHandle
,
3607 (*Command
& PCI_BIT_3
) != 0
3610 ShellPrintHiiEx(-1, -1, NULL
,
3611 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
3612 gShellDebug1HiiHandle
,
3613 (*Command
& PCI_BIT_4
) != 0
3616 ShellPrintHiiEx(-1, -1, NULL
,
3617 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
3618 gShellDebug1HiiHandle
,
3619 (*Command
& PCI_BIT_5
) != 0
3622 ShellPrintHiiEx(-1, -1, NULL
,
3623 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
3624 gShellDebug1HiiHandle
,
3625 (*Command
& PCI_BIT_6
) != 0
3628 ShellPrintHiiEx(-1, -1, NULL
,
3629 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
3630 gShellDebug1HiiHandle
,
3631 (*Command
& PCI_BIT_7
) != 0
3634 ShellPrintHiiEx(-1, -1, NULL
,
3635 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
3636 gShellDebug1HiiHandle
,
3637 (*Command
& PCI_BIT_8
) != 0
3640 ShellPrintHiiEx(-1, -1, NULL
,
3641 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
3642 gShellDebug1HiiHandle
,
3643 (*Command
& PCI_BIT_9
) != 0
3650 Explain each meaningful bit of register Bridge Control.
3652 @param[in] BridgeControl Points to the content of register Bridge Control.
3653 @param[in] HeaderType The headertype.
3655 @retval EFI_SUCCESS The command completed successfully.
3658 PciExplainBridgeControl (
3659 IN UINT16
*BridgeControl
,
3660 IN PCI_HEADER_TYPE HeaderType
3663 ShellPrintHiiEx(-1, -1, NULL
,
3664 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
3665 gShellDebug1HiiHandle
,
3666 INDEX_OF (BridgeControl
),
3670 ShellPrintHiiEx(-1, -1, NULL
,
3671 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
3672 gShellDebug1HiiHandle
,
3673 (*BridgeControl
& PCI_BIT_0
) != 0
3675 ShellPrintHiiEx(-1, -1, NULL
,
3676 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
3677 gShellDebug1HiiHandle
,
3678 (*BridgeControl
& PCI_BIT_1
) != 0
3680 ShellPrintHiiEx(-1, -1, NULL
,
3681 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
3682 gShellDebug1HiiHandle
,
3683 (*BridgeControl
& PCI_BIT_2
) != 0
3685 ShellPrintHiiEx(-1, -1, NULL
,
3686 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
3687 gShellDebug1HiiHandle
,
3688 (*BridgeControl
& PCI_BIT_3
) != 0
3690 ShellPrintHiiEx(-1, -1, NULL
,
3691 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
3692 gShellDebug1HiiHandle
,
3693 (*BridgeControl
& PCI_BIT_5
) != 0
3697 // Register Bridge Control has some slight differences between P2P bridge
3698 // and Cardbus bridge from bit 6 to bit 11.
3700 if (HeaderType
== PciP2pBridge
) {
3701 ShellPrintHiiEx(-1, -1, NULL
,
3702 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
3703 gShellDebug1HiiHandle
,
3704 (*BridgeControl
& PCI_BIT_6
) != 0
3706 ShellPrintHiiEx(-1, -1, NULL
,
3707 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
3708 gShellDebug1HiiHandle
,
3709 (*BridgeControl
& PCI_BIT_7
) != 0
3711 ShellPrintHiiEx(-1, -1, NULL
,
3712 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
3713 gShellDebug1HiiHandle
,
3714 (*BridgeControl
& PCI_BIT_8
)!=0 ? L
"2^10" : L
"2^15"
3716 ShellPrintHiiEx(-1, -1, NULL
,
3717 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
3718 gShellDebug1HiiHandle
,
3719 (*BridgeControl
& PCI_BIT_9
)!=0 ? L
"2^10" : L
"2^15"
3721 ShellPrintHiiEx(-1, -1, NULL
,
3722 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
3723 gShellDebug1HiiHandle
,
3724 (*BridgeControl
& PCI_BIT_10
) != 0
3726 ShellPrintHiiEx(-1, -1, NULL
,
3727 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
3728 gShellDebug1HiiHandle
,
3729 (*BridgeControl
& PCI_BIT_11
) != 0
3733 ShellPrintHiiEx(-1, -1, NULL
,
3734 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
3735 gShellDebug1HiiHandle
,
3736 (*BridgeControl
& PCI_BIT_6
) != 0
3738 ShellPrintHiiEx(-1, -1, NULL
,
3739 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
3740 gShellDebug1HiiHandle
,
3741 (*BridgeControl
& PCI_BIT_7
) != 0
3743 ShellPrintHiiEx(-1, -1, NULL
,
3744 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
3745 gShellDebug1HiiHandle
,
3746 (*BridgeControl
& PCI_BIT_10
) != 0
3754 Print each capability structure.
3756 @param[in] IoDev The pointer to the deivce.
3757 @param[in] Address The address to start at.
3758 @param[in] CapPtr The offset from the address.
3760 @retval EFI_SUCCESS The operation was successful.
3763 PciExplainCapabilityStruct (
3764 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3769 UINT8 CapabilityPtr
;
3770 UINT16 CapabilityEntry
;
3774 CapabilityPtr
= CapPtr
;
3777 // Go through the Capability list
3779 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
3780 RegAddress
= Address
+ CapabilityPtr
;
3781 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
3783 CapabilityID
= (UINT8
) CapabilityEntry
;
3786 // Explain PciExpress data
3788 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
3789 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
);
3793 // Explain other capabilities here
3795 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
3802 Print out information of the capability information.
3804 @param[in] PciExpressCap The pointer to the structure about the device.
3806 @retval EFI_SUCCESS The operation was successful.
3810 IN PCIE_CAP_STURCTURE
*PciExpressCap
3814 CHAR16
*DevicePortType
;
3816 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3818 L
" Capability Version(3:0): %E0x%04x%N\n",
3819 PCIE_CAP_VERSION (PcieCapReg
)
3821 if ((UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) < PCIE_DEVICE_PORT_TYPE_MAX
) {
3822 DevicePortType
= DevicePortTypeTable
[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
)];
3824 DevicePortType
= L
"Unknown Type";
3827 L
" Device/PortType(7:4): %E%s%N\n",
3831 // 'Slot Implemented' is only valid for:
3832 // a) Root Port of PCI Express Root Complex, or
3833 // b) Downstream Port of PCI Express Switch
3835 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_ROOT_COMPLEX_ROOT_PORT
||
3836 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_SWITCH_DOWNSTREAM_PORT
) {
3838 L
" Slot Implemented(8): %E%d%N\n",
3839 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg
)
3843 L
" Interrupt Message Number(13:9): %E0x%05x%N\n",
3844 PCIE_CAP_INT_MSG_NUM (PcieCapReg
)
3850 Print out information of the device capability information.
3852 @param[in] PciExpressCap The pointer to the structure about the device.
3854 @retval EFI_SUCCESS The operation was successful.
3857 ExplainPcieDeviceCap (
3858 IN PCIE_CAP_STURCTURE
*PciExpressCap
3862 UINT32 PcieDeviceCap
;
3863 UINT8 DevicePortType
;
3867 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3868 PcieDeviceCap
= PciExpressCap
->PcieDeviceCap
;
3869 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
);
3870 Print (L
" Max_Payload_Size Supported(2:0): ");
3871 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) < 6) {
3872 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) + 7));
3874 Print (L
"%EUnknown%N\n");
3877 L
" Phantom Functions Supported(4:3): %E%d%N\n",
3878 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap
)
3881 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",
3882 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap
) ? 8 : 5
3885 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
3887 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3888 L0sLatency
= (UINT8
) PCIE_CAP_L0SLATENCY (PcieDeviceCap
);
3889 L1Latency
= (UINT8
) PCIE_CAP_L1LATENCY (PcieDeviceCap
);
3890 Print (L
" Endpoint L0s Acceptable Latency(8:6): ");
3891 if (L0sLatency
< 4) {
3892 Print (L
"%EMaximum of %d ns%N\n", 1 << (L0sLatency
+ 6));
3894 if (L0sLatency
< 7) {
3895 Print (L
"%EMaximum of %d us%N\n", 1 << (L0sLatency
- 3));
3897 Print (L
"%ENo limit%N\n");
3900 Print (L
" Endpoint L1 Acceptable Latency(11:9): ");
3901 if (L1Latency
< 7) {
3902 Print (L
"%EMaximum of %d us%N\n", 1 << (L1Latency
+ 1));
3904 Print (L
"%ENo limit%N\n");
3908 L
" Role-based Error Reporting(15): %E%d%N\n",
3909 PCIE_CAP_ERR_REPORTING (PcieDeviceCap
)
3912 // Only valid for Upstream Port:
3913 // a) Captured Slot Power Limit Value
3914 // b) Captured Slot Power Scale
3916 if (DevicePortType
== PCIE_SWITCH_UPSTREAM_PORT
) {
3918 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",
3919 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap
)
3922 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\n",
3923 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap
)]
3927 // Function Level Reset Capability is only valid for Endpoint
3929 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3931 L
" Function Level Reset Capability(28): %E%d%N\n",
3932 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap
)
3939 Print out information of the device control information.
3941 @param[in] PciExpressCap The pointer to the structure about the device.
3943 @retval EFI_SUCCESS The operation was successful.
3946 ExplainPcieDeviceControl (
3947 IN PCIE_CAP_STURCTURE
*PciExpressCap
3951 UINT16 PcieDeviceControl
;
3953 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3954 PcieDeviceControl
= PciExpressCap
->DeviceControl
;
3956 L
" Correctable Error Reporting Enable(0): %E%d%N\n",
3957 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3960 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\n",
3961 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3964 L
" Fatal Error Reporting Enable(2): %E%d%N\n",
3965 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3968 L
" Unsupported Request Reporting Enable(3): %E%d%N\n",
3969 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl
)
3972 L
" Enable Relaxed Ordering(4): %E%d%N\n",
3973 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl
)
3975 Print (L
" Max_Payload_Size(7:5): ");
3976 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) < 6) {
3977 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) + 7));
3979 Print (L
"%EUnknown%N\n");
3982 L
" Extended Tag Field Enable(8): %E%d%N\n",
3983 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl
)
3986 L
" Phantom Functions Enable(9): %E%d%N\n",
3987 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl
)
3990 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",
3991 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl
)
3994 L
" Enable No Snoop(11): %E%d%N\n",
3995 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl
)
3997 Print (L
" Max_Read_Request_Size(14:12): ");
3998 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) < 6) {
3999 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) + 7));
4001 Print (L
"%EUnknown%N\n");
4004 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4006 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_PCIE_TO_PCIX_BRIDGE
) {
4008 L
" Bridge Configuration Retry Enable(15): %E%d%N\n",
4009 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl
)
4016 Print out information of the device status information.
4018 @param[in] PciExpressCap The pointer to the structure about the device.
4020 @retval EFI_SUCCESS The operation was successful.
4023 ExplainPcieDeviceStatus (
4024 IN PCIE_CAP_STURCTURE
*PciExpressCap
4027 UINT16 PcieDeviceStatus
;
4029 PcieDeviceStatus
= PciExpressCap
->DeviceStatus
;
4031 L
" Correctable Error Detected(0): %E%d%N\n",
4032 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus
)
4035 L
" Non-Fatal Error Detected(1): %E%d%N\n",
4036 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus
)
4039 L
" Fatal Error Detected(2): %E%d%N\n",
4040 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus
)
4043 L
" Unsupported Request Detected(3): %E%d%N\n",
4044 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus
)
4047 L
" AUX Power Detected(4): %E%d%N\n",
4048 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus
)
4051 L
" Transactions Pending(5): %E%d%N\n",
4052 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus
)
4058 Print out information of the device link information.
4060 @param[in] PciExpressCap The pointer to the structure about the device.
4062 @retval EFI_SUCCESS The operation was successful.
4065 ExplainPcieLinkCap (
4066 IN PCIE_CAP_STURCTURE
*PciExpressCap
4070 CHAR16
*SupLinkSpeeds
;
4073 PcieLinkCap
= PciExpressCap
->LinkCap
;
4074 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap
)) {
4076 SupLinkSpeeds
= L
"2.5 GT/s";
4079 SupLinkSpeeds
= L
"5.0 GT/s and 2.5 GT/s";
4082 SupLinkSpeeds
= L
"Unknown";
4086 L
" Supported Link Speeds(3:0): %E%s supported%N\n",
4090 L
" Maximum Link Width(9:4): %Ex%d%N\n",
4091 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap
)
4093 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap
)) {
4095 AspmValue
= L
"L0s Entry";
4098 AspmValue
= L
"L0s and L1";
4101 AspmValue
= L
"Reserved";
4105 L
" Active State Power Management Support(11:10): %E%s Supported%N\n",
4109 L
" L0s Exit Latency(14:12): %E%s%N\n",
4110 L0sLatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4113 L
" L1 Exit Latency(17:15): %E%s%N\n",
4114 L1LatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4117 L
" Clock Power Management(18): %E%d%N\n",
4118 PCIE_CAP_CLOCK_PM (PcieLinkCap
)
4121 L
" Surprise Down Error Reporting Capable(19): %E%d%N\n",
4122 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap
)
4125 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",
4126 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap
)
4129 L
" Link Bandwidth Notification Capability(21): %E%d%N\n",
4130 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap
)
4133 L
" Port Number(31:24): %E0x%02x%N\n",
4134 PCIE_CAP_PORT_NUMBER (PcieLinkCap
)
4140 Print out information of the device link control information.
4142 @param[in] PciExpressCap The pointer to the structure about the device.
4144 @retval EFI_SUCCESS The operation was successful.
4147 ExplainPcieLinkControl (
4148 IN PCIE_CAP_STURCTURE
*PciExpressCap
4151 UINT16 PcieLinkControl
;
4152 UINT8 DevicePortType
;
4154 PcieLinkControl
= PciExpressCap
->LinkControl
;
4155 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
->PcieCapReg
);
4157 L
" Active State Power Management Control(1:0): %E%s%N\n",
4158 ASPMCtrlStrTable
[PCIE_CAP_ASPM_CONTROL (PcieLinkControl
)]
4161 // RCB is not applicable to switches
4163 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4165 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\n",
4166 1 << (PCIE_CAP_RCB (PcieLinkControl
) + 6)
4170 // Link Disable is reserved on
4172 // b) PCI Express to PCI/PCI-X bridges
4173 // c) Upstream Ports of Switches
4175 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4176 DevicePortType
!= PCIE_SWITCH_UPSTREAM_PORT
&&
4177 DevicePortType
!= PCIE_PCIE_TO_PCIX_BRIDGE
) {
4179 L
" Link Disable(4): %E%d%N\n",
4180 PCIE_CAP_LINK_DISABLE (PcieLinkControl
)
4184 L
" Common Clock Configuration(6): %E%d%N\n",
4185 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl
)
4188 L
" Extended Synch(7): %E%d%N\n",
4189 PCIE_CAP_EXT_SYNC (PcieLinkControl
)
4192 L
" Enable Clock Power Management(8): %E%d%N\n",
4193 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl
)
4196 L
" Hardware Autonomous Width Disable(9): %E%d%N\n",
4197 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl
)
4200 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",
4201 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl
)
4204 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",
4205 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl
)
4211 Print out information of the device link status information.
4213 @param[in] PciExpressCap The pointer to the structure about the device.
4215 @retval EFI_SUCCESS The operation was successful.
4218 ExplainPcieLinkStatus (
4219 IN PCIE_CAP_STURCTURE
*PciExpressCap
4222 UINT16 PcieLinkStatus
;
4223 CHAR16
*SupLinkSpeeds
;
4225 PcieLinkStatus
= PciExpressCap
->LinkStatus
;
4226 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus
)) {
4228 SupLinkSpeeds
= L
"2.5 GT/s";
4231 SupLinkSpeeds
= L
"5.0 GT/s";
4234 SupLinkSpeeds
= L
"Reserved";
4238 L
" Current Link Speed(3:0): %E%s%N\n",
4242 L
" Negotiated Link Width(9:4): %Ex%d%N\n",
4243 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus
)
4246 L
" Link Training(11): %E%d%N\n",
4247 PCIE_CAP_LINK_TRAINING (PcieLinkStatus
)
4250 L
" Slot Clock Configuration(12): %E%d%N\n",
4251 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus
)
4254 L
" Data Link Layer Link Active(13): %E%d%N\n",
4255 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus
)
4258 L
" Link Bandwidth Management Status(14): %E%d%N\n",
4259 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus
)
4262 L
" Link Autonomous Bandwidth Status(15): %E%d%N\n",
4263 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus
)
4269 Print out information of the device slot information.
4271 @param[in] PciExpressCap The pointer to the structure about the device.
4273 @retval EFI_SUCCESS The operation was successful.
4276 ExplainPcieSlotCap (
4277 IN PCIE_CAP_STURCTURE
*PciExpressCap
4282 PcieSlotCap
= PciExpressCap
->SlotCap
;
4285 L
" Attention Button Present(0): %E%d%N\n",
4286 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap
)
4289 L
" Power Controller Present(1): %E%d%N\n",
4290 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap
)
4293 L
" MRL Sensor Present(2): %E%d%N\n",
4294 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap
)
4297 L
" Attention Indicator Present(3): %E%d%N\n",
4298 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap
)
4301 L
" Power Indicator Present(4): %E%d%N\n",
4302 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap
)
4305 L
" Hot-Plug Surprise(5): %E%d%N\n",
4306 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap
)
4309 L
" Hot-Plug Capable(6): %E%d%N\n",
4310 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap
)
4313 L
" Slot Power Limit Value(14:7): %E0x%02x%N\n",
4314 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap
)
4317 L
" Slot Power Limit Scale(16:15): %E%s%N\n",
4318 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap
)]
4321 L
" Electromechanical Interlock Present(17): %E%d%N\n",
4322 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap
)
4325 L
" No Command Completed Support(18): %E%d%N\n",
4326 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap
)
4329 L
" Physical Slot Number(31:19): %E%d%N\n",
4330 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap
)
4337 Print out information of the device slot control information.
4339 @param[in] PciExpressCap The pointer to the structure about the device.
4341 @retval EFI_SUCCESS The operation was successful.
4344 ExplainPcieSlotControl (
4345 IN PCIE_CAP_STURCTURE
*PciExpressCap
4348 UINT16 PcieSlotControl
;
4350 PcieSlotControl
= PciExpressCap
->SlotControl
;
4352 L
" Attention Button Pressed Enable(0): %E%d%N\n",
4353 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl
)
4356 L
" Power Fault Detected Enable(1): %E%d%N\n",
4357 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl
)
4360 L
" MRL Sensor Changed Enable(2): %E%d%N\n",
4361 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl
)
4364 L
" Presence Detect Changed Enable(3): %E%d%N\n",
4365 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl
)
4368 L
" Command Completed Interrupt Enable(4): %E%d%N\n",
4369 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl
)
4372 L
" Hot-Plug Interrupt Enable(5): %E%d%N\n",
4373 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl
)
4376 L
" Attention Indicator Control(7:6): %E%s%N\n",
4377 IndicatorTable
[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl
)]
4380 L
" Power Indicator Control(9:8): %E%s%N\n",
4381 IndicatorTable
[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl
)]
4383 Print (L
" Power Controller Control(10): %EPower ");
4384 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl
)) {
4390 L
" Electromechanical Interlock Control(11): %E%d%N\n",
4391 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl
)
4394 L
" Data Link Layer State Changed Enable(12): %E%d%N\n",
4395 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl
)
4401 Print out information of the device slot status information.
4403 @param[in] PciExpressCap The pointer to the structure about the device.
4405 @retval EFI_SUCCESS The operation was successful.
4408 ExplainPcieSlotStatus (
4409 IN PCIE_CAP_STURCTURE
*PciExpressCap
4412 UINT16 PcieSlotStatus
;
4414 PcieSlotStatus
= PciExpressCap
->SlotStatus
;
4417 L
" Attention Button Pressed(0): %E%d%N\n",
4418 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus
)
4421 L
" Power Fault Detected(1): %E%d%N\n",
4422 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus
)
4425 L
" MRL Sensor Changed(2): %E%d%N\n",
4426 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus
)
4429 L
" Presence Detect Changed(3): %E%d%N\n",
4430 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus
)
4433 L
" Command Completed(4): %E%d%N\n",
4434 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus
)
4436 Print (L
" MRL Sensor State(5): %EMRL ");
4437 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus
)) {
4438 Print (L
" Opened%N\n");
4440 Print (L
" Closed%N\n");
4442 Print (L
" Presence Detect State(6): ");
4443 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus
)) {
4444 Print (L
"%ECard Present in slot%N\n");
4446 Print (L
"%ESlot Empty%N\n");
4448 Print (L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4449 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus
)) {
4450 Print (L
"Engaged%N\n");
4452 Print (L
"Disengaged%N\n");
4455 L
" Data Link Layer State Changed(8): %E%d%N\n",
4456 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus
)
4462 Print out information of the device root information.
4464 @param[in] PciExpressCap The pointer to the structure about the device.
4466 @retval EFI_SUCCESS The operation was successful.
4469 ExplainPcieRootControl (
4470 IN PCIE_CAP_STURCTURE
*PciExpressCap
4473 UINT16 PcieRootControl
;
4475 PcieRootControl
= PciExpressCap
->RootControl
;
4478 L
" System Error on Correctable Error Enable(0): %E%d%N\n",
4479 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl
)
4482 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\n",
4483 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl
)
4486 L
" System Error on Fatal Error Enable(2): %E%d%N\n",
4487 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl
)
4490 L
" PME Interrupt Enable(3): %E%d%N\n",
4491 PCIE_CAP_PME_INT_ENABLE (PcieRootControl
)
4494 L
" CRS Software Visibility Enable(4): %E%d%N\n",
4495 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl
)
4502 Print out information of the device root capability information.
4504 @param[in] PciExpressCap The pointer to the structure about the device.
4506 @retval EFI_SUCCESS The operation was successful.
4509 ExplainPcieRootCap (
4510 IN PCIE_CAP_STURCTURE
*PciExpressCap
4515 PcieRootCap
= PciExpressCap
->RsvdP
;
4518 L
" CRS Software Visibility(0): %E%d%N\n",
4519 PCIE_CAP_CRS_SW_VIS (PcieRootCap
)
4526 Print out information of the device root status information.
4528 @param[in] PciExpressCap The pointer to the structure about the device.
4530 @retval EFI_SUCCESS The operation was successful.
4533 ExplainPcieRootStatus (
4534 IN PCIE_CAP_STURCTURE
*PciExpressCap
4537 UINT32 PcieRootStatus
;
4539 PcieRootStatus
= PciExpressCap
->RootStatus
;
4542 L
" PME Requester ID(15:0): %E0x%04x%N\n",
4543 PCIE_CAP_PME_REQ_ID (PcieRootStatus
)
4546 L
" PME Status(16): %E%d%N\n",
4547 PCIE_CAP_PME_STATUS (PcieRootStatus
)
4550 L
" PME Pending(17): %E%d%N\n",
4551 PCIE_CAP_PME_PENDING (PcieRootStatus
)
4557 Display Pcie device structure.
4559 @param[in] IoDev The pointer to the root pci protocol.
4560 @param[in] Address The Address to start at.
4561 @param[in] CapabilityPtr The offset from the address to start.
4564 PciExplainPciExpress (
4565 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
4567 IN UINT8 CapabilityPtr
4571 PCIE_CAP_STURCTURE PciExpressCap
;
4573 UINT64 CapRegAddress
;
4578 UINTN ExtendRegSize
;
4579 UINT64 Pciex_Address
;
4580 UINT8 DevicePortType
;
4585 CapRegAddress
= Address
+ CapabilityPtr
;
4590 sizeof (PciExpressCap
) / sizeof (UINT32
),
4594 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
.PcieCapReg
);
4596 Print (L
"\nPci Express device capability structure:\n");
4598 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
4599 if (ShellGetExecutionBreakFlag()) {
4602 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
4603 switch (PcieExplainList
[Index
].Width
) {
4604 case FieldWidthUINT8
:
4605 RegValue
= *(UINT8
*) RegAddr
;
4607 case FieldWidthUINT16
:
4608 RegValue
= *(UINT16
*) RegAddr
;
4610 case FieldWidthUINT32
:
4611 RegValue
= *(UINT32
*) RegAddr
;
4617 ShellPrintHiiEx(-1, -1, NULL
,
4618 PcieExplainList
[Index
].Token
,
4619 gShellDebug1HiiHandle
,
4620 PcieExplainList
[Index
].Offset
,
4623 if (PcieExplainList
[Index
].Func
== NULL
) {
4626 switch (PcieExplainList
[Index
].Type
) {
4627 case PcieExplainTypeLink
:
4629 // Link registers should not be used by
4630 // a) Root Complex Integrated Endpoint
4631 // b) Root Complex Event Collector
4633 if (DevicePortType
== PCIE_ROOT_COMPLEX_INTEGRATED_PORT
||
4634 DevicePortType
== PCIE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
4638 case PcieExplainTypeSlot
:
4640 // Slot registers are only valid for
4641 // a) Root Port of PCI Express Root Complex
4642 // b) Downstream Port of PCI Express Switch
4643 // and when SlotImplemented bit is set in PCIE cap register.
4645 if ((DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
&&
4646 DevicePortType
!= PCIE_SWITCH_DOWNSTREAM_PORT
) ||
4647 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap
.PcieCapReg
)) {
4651 case PcieExplainTypeRoot
:
4653 // Root registers are only valid for
4654 // Root Port of PCI Express Root Complex
4656 if (DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
) {
4663 PcieExplainList
[Index
].Func (&PciExpressCap
);
4666 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
4667 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
4668 Func
= (UINT8
) (RShiftU64 (Address
, 8));
4670 Pciex_Address
= CALC_EFI_PCIEX_ADDRESS (Bus
, Dev
, Func
, 0x100);
4672 ExtendRegSize
= 0x1000 - 0x100;
4674 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
4677 // PciRootBridgeIo protocol should support pci express extend space IO
4678 // (Begins at offset 0x100)
4680 Status
= IoDev
->Pci
.Read (
4684 (ExtendRegSize
) / sizeof (UINT32
),
4685 (VOID
*) (ExRegBuffer
)
4687 if (EFI_ERROR (Status
)) {
4688 FreePool ((VOID
*) ExRegBuffer
);
4689 return EFI_UNSUPPORTED
;
4692 // Start outputing PciEx extend space( 0xFF-0xFFF)
4694 Print (L
"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");
4696 if (ExRegBuffer
!= NULL
) {
4701 (VOID
*) (ExRegBuffer
)
4704 FreePool ((VOID
*) ExRegBuffer
);