2 Produces the CPU I/O 2 Protocol.
4 Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include "CpuIo2Dxe.h"
14 // Handle for the CPU I/O 2 Protocol
16 EFI_HANDLE mHandle
= NULL
;
19 // CPU I/O 2 Protocol instance
21 EFI_CPU_IO2_PROTOCOL mCpuIo2
= {
33 // Lookup table for increment values based on transfer widths
36 1, // EfiCpuIoWidthUint8
37 2, // EfiCpuIoWidthUint16
38 4, // EfiCpuIoWidthUint32
39 8, // EfiCpuIoWidthUint64
40 0, // EfiCpuIoWidthFifoUint8
41 0, // EfiCpuIoWidthFifoUint16
42 0, // EfiCpuIoWidthFifoUint32
43 0, // EfiCpuIoWidthFifoUint64
44 1, // EfiCpuIoWidthFillUint8
45 2, // EfiCpuIoWidthFillUint16
46 4, // EfiCpuIoWidthFillUint32
47 8 // EfiCpuIoWidthFillUint64
51 // Lookup table for increment values based on transfer widths
53 UINT8 mOutStride
[] = {
54 1, // EfiCpuIoWidthUint8
55 2, // EfiCpuIoWidthUint16
56 4, // EfiCpuIoWidthUint32
57 8, // EfiCpuIoWidthUint64
58 1, // EfiCpuIoWidthFifoUint8
59 2, // EfiCpuIoWidthFifoUint16
60 4, // EfiCpuIoWidthFifoUint32
61 8, // EfiCpuIoWidthFifoUint64
62 0, // EfiCpuIoWidthFillUint8
63 0, // EfiCpuIoWidthFillUint16
64 0, // EfiCpuIoWidthFillUint32
65 0 // EfiCpuIoWidthFillUint64
69 Check parameters to a CPU I/O 2 Protocol service request.
71 The I/O operations are carried out exactly as requested. The caller is responsible
72 for satisfying any alignment and I/O width restrictions that a PI System on a
73 platform might require. For example on some platforms, width requests of
74 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
75 be handled by the driver.
77 @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
78 @param[in] Width Signifies the width of the I/O or Memory operation.
79 @param[in] Address The base address of the I/O operation.
80 @param[in] Count The number of I/O operations to perform. The number of
81 bytes moved is Width size * Count, starting at Address.
82 @param[in] Buffer For read operations, the destination buffer to store the results.
83 For write operations, the source buffer from which to write data.
85 @retval EFI_SUCCESS The parameters for this request pass the checks.
86 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
87 @retval EFI_INVALID_PARAMETER Buffer is NULL.
88 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
89 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
90 and Count is not valid for this PI system.
95 IN BOOLEAN MmioOperation
,
96 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
106 // Check to see if Buffer is NULL
108 if (Buffer
== NULL
) {
109 return EFI_INVALID_PARAMETER
;
113 // Check to see if Width is in the valid range
115 if ((UINT32
)Width
>= EfiCpuIoWidthMaximum
) {
116 return EFI_INVALID_PARAMETER
;
120 // For FIFO type, the target address won't increase during the access,
121 // so treat Count as 1
123 if (Width
>= EfiCpuIoWidthFifoUint8
&& Width
<= EfiCpuIoWidthFifoUint64
) {
128 // Check to see if Width is in the valid range for I/O Port operations
130 Width
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
131 if (!MmioOperation
&& (Width
== EfiCpuIoWidthUint64
)) {
132 return EFI_INVALID_PARAMETER
;
136 // Check to see if Address is aligned
138 if ((Address
& ((UINT64
)mInStride
[Width
] - 1)) != 0) {
139 return EFI_UNSUPPORTED
;
143 // Check to see if any address associated with this transfer exceeds the maximum
144 // allowed address. The maximum address implied by the parameters passed in is
145 // Address + Size * Count. If the following condition is met, then the transfer
148 // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
150 // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
151 // can also be the maximum integer value supported by the CPU, this range
152 // check must be adjusted to avoid all oveflow conditions.
154 // The following form of the range check is equivalent but assumes that
155 // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
157 Limit
= (MmioOperation
? MAX_ADDRESS
: MAX_IO_PORT_ADDRESS
);
159 if (Address
> Limit
) {
160 return EFI_UNSUPPORTED
;
163 MaxCount
= RShiftU64 (Limit
, Width
);
164 if (MaxCount
< (Count
- 1)) {
165 return EFI_UNSUPPORTED
;
167 if (Address
> LShiftU64 (MaxCount
- Count
+ 1, Width
)) {
168 return EFI_UNSUPPORTED
;
173 // Check to see if Buffer is aligned
174 // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.)
176 if (((UINTN
)Buffer
& ((MIN (sizeof (UINTN
), mInStride
[Width
]) - 1))) != 0) {
177 return EFI_UNSUPPORTED
;
184 Reads memory-mapped registers.
186 The I/O operations are carried out exactly as requested. The caller is responsible
187 for satisfying any alignment and I/O width restrictions that a PI System on a
188 platform might require. For example on some platforms, width requests of
189 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
190 be handled by the driver.
192 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
193 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
194 each of the Count operations that is performed.
196 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
197 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
198 incremented for each of the Count operations that is performed. The read or
199 write operation is performed Count times on the same Address.
201 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
202 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
203 incremented for each of the Count operations that is performed. The read or
204 write operation is performed Count times from the first element of Buffer.
206 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
207 @param[in] Width Signifies the width of the I/O or Memory operation.
208 @param[in] Address The base address of the I/O operation.
209 @param[in] Count The number of I/O operations to perform. The number of
210 bytes moved is Width size * Count, starting at Address.
211 @param[out] Buffer For read operations, the destination buffer to store the results.
212 For write operations, the source buffer from which to write data.
214 @retval EFI_SUCCESS The data was read from or written to the PI system.
215 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
216 @retval EFI_INVALID_PARAMETER Buffer is NULL.
217 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
218 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
219 and Count is not valid for this PI system.
224 CpuMemoryServiceRead (
225 IN EFI_CPU_IO2_PROTOCOL
*This
,
226 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
235 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
238 Status
= CpuIoCheckParameter (TRUE
, Width
, Address
, Count
, Buffer
);
239 if (EFI_ERROR (Status
)) {
244 // Select loop based on the width of the transfer
246 InStride
= mInStride
[Width
];
247 OutStride
= mOutStride
[Width
];
248 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
249 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
250 if (OperationWidth
== EfiCpuIoWidthUint8
) {
251 *Uint8Buffer
= MmioRead8 ((UINTN
)Address
);
252 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
253 *((UINT16
*)Uint8Buffer
) = MmioRead16 ((UINTN
)Address
);
254 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
255 *((UINT32
*)Uint8Buffer
) = MmioRead32 ((UINTN
)Address
);
256 } else if (OperationWidth
== EfiCpuIoWidthUint64
) {
257 *((UINT64
*)Uint8Buffer
) = MmioRead64 ((UINTN
)Address
);
264 Writes memory-mapped registers.
266 The I/O operations are carried out exactly as requested. The caller is responsible
267 for satisfying any alignment and I/O width restrictions that a PI System on a
268 platform might require. For example on some platforms, width requests of
269 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
270 be handled by the driver.
272 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
273 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
274 each of the Count operations that is performed.
276 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
277 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
278 incremented for each of the Count operations that is performed. The read or
279 write operation is performed Count times on the same Address.
281 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
282 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
283 incremented for each of the Count operations that is performed. The read or
284 write operation is performed Count times from the first element of Buffer.
286 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
287 @param[in] Width Signifies the width of the I/O or Memory operation.
288 @param[in] Address The base address of the I/O operation.
289 @param[in] Count The number of I/O operations to perform. The number of
290 bytes moved is Width size * Count, starting at Address.
291 @param[in] Buffer For read operations, the destination buffer to store the results.
292 For write operations, the source buffer from which to write data.
294 @retval EFI_SUCCESS The data was read from or written to the PI system.
295 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
296 @retval EFI_INVALID_PARAMETER Buffer is NULL.
297 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
298 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
299 and Count is not valid for this PI system.
304 CpuMemoryServiceWrite (
305 IN EFI_CPU_IO2_PROTOCOL
*This
,
306 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
315 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
318 Status
= CpuIoCheckParameter (TRUE
, Width
, Address
, Count
, Buffer
);
319 if (EFI_ERROR (Status
)) {
324 // Select loop based on the width of the transfer
326 InStride
= mInStride
[Width
];
327 OutStride
= mOutStride
[Width
];
328 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
329 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
330 if (OperationWidth
== EfiCpuIoWidthUint8
) {
331 MmioWrite8 ((UINTN
)Address
, *Uint8Buffer
);
332 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
333 MmioWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
334 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
335 MmioWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
336 } else if (OperationWidth
== EfiCpuIoWidthUint64
) {
337 MmioWrite64 ((UINTN
)Address
, *((UINT64
*)Uint8Buffer
));
346 The I/O operations are carried out exactly as requested. The caller is responsible
347 for satisfying any alignment and I/O width restrictions that a PI System on a
348 platform might require. For example on some platforms, width requests of
349 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
350 be handled by the driver.
352 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
353 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
354 each of the Count operations that is performed.
356 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
357 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
358 incremented for each of the Count operations that is performed. The read or
359 write operation is performed Count times on the same Address.
361 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
362 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
363 incremented for each of the Count operations that is performed. The read or
364 write operation is performed Count times from the first element of Buffer.
366 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
367 @param[in] Width Signifies the width of the I/O or Memory operation.
368 @param[in] Address The base address of the I/O operation.
369 @param[in] Count The number of I/O operations to perform. The number of
370 bytes moved is Width size * Count, starting at Address.
371 @param[out] Buffer For read operations, the destination buffer to store the results.
372 For write operations, the source buffer from which to write data.
374 @retval EFI_SUCCESS The data was read from or written to the PI system.
375 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
376 @retval EFI_INVALID_PARAMETER Buffer is NULL.
377 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
378 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
379 and Count is not valid for this PI system.
385 IN EFI_CPU_IO2_PROTOCOL
*This
,
386 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
395 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
398 Status
= CpuIoCheckParameter (FALSE
, Width
, Address
, Count
, Buffer
);
399 if (EFI_ERROR (Status
)) {
404 // Select loop based on the width of the transfer
406 InStride
= mInStride
[Width
];
407 OutStride
= mOutStride
[Width
];
408 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
411 // Fifo operations supported for (mInStride[Width] == 0)
414 switch (OperationWidth
) {
415 case EfiCpuIoWidthUint8
:
416 IoReadFifo8 ((UINTN
)Address
, Count
, Buffer
);
418 case EfiCpuIoWidthUint16
:
419 IoReadFifo16 ((UINTN
)Address
, Count
, Buffer
);
421 case EfiCpuIoWidthUint32
:
422 IoReadFifo32 ((UINTN
)Address
, Count
, Buffer
);
426 // The CpuIoCheckParameter call above will ensure that this
427 // path is not taken.
434 for (Uint8Buffer
= Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
435 if (OperationWidth
== EfiCpuIoWidthUint8
) {
436 *Uint8Buffer
= IoRead8 ((UINTN
)Address
);
437 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
438 *((UINT16
*)Uint8Buffer
) = IoRead16 ((UINTN
)Address
);
439 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
440 *((UINT32
*)Uint8Buffer
) = IoRead32 ((UINTN
)Address
);
450 The I/O operations are carried out exactly as requested. The caller is responsible
451 for satisfying any alignment and I/O width restrictions that a PI System on a
452 platform might require. For example on some platforms, width requests of
453 EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
454 be handled by the driver.
456 If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
457 or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
458 each of the Count operations that is performed.
460 If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
461 EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
462 incremented for each of the Count operations that is performed. The read or
463 write operation is performed Count times on the same Address.
465 If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
466 EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
467 incremented for each of the Count operations that is performed. The read or
468 write operation is performed Count times from the first element of Buffer.
470 @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
471 @param[in] Width Signifies the width of the I/O or Memory operation.
472 @param[in] Address The base address of the I/O operation.
473 @param[in] Count The number of I/O operations to perform. The number of
474 bytes moved is Width size * Count, starting at Address.
475 @param[in] Buffer For read operations, the destination buffer to store the results.
476 For write operations, the source buffer from which to write data.
478 @retval EFI_SUCCESS The data was read from or written to the PI system.
479 @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
480 @retval EFI_INVALID_PARAMETER Buffer is NULL.
481 @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
482 @retval EFI_UNSUPPORTED The address range specified by Address, Width,
483 and Count is not valid for this PI system.
489 IN EFI_CPU_IO2_PROTOCOL
*This
,
490 IN EFI_CPU_IO_PROTOCOL_WIDTH Width
,
499 EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth
;
503 // Make sure the parameters are valid
505 Status
= CpuIoCheckParameter (FALSE
, Width
, Address
, Count
, Buffer
);
506 if (EFI_ERROR (Status
)) {
511 // Select loop based on the width of the transfer
513 InStride
= mInStride
[Width
];
514 OutStride
= mOutStride
[Width
];
515 OperationWidth
= (EFI_CPU_IO_PROTOCOL_WIDTH
) (Width
& 0x03);
518 // Fifo operations supported for (mInStride[Width] == 0)
521 switch (OperationWidth
) {
522 case EfiCpuIoWidthUint8
:
523 IoWriteFifo8 ((UINTN
)Address
, Count
, Buffer
);
525 case EfiCpuIoWidthUint16
:
526 IoWriteFifo16 ((UINTN
)Address
, Count
, Buffer
);
528 case EfiCpuIoWidthUint32
:
529 IoWriteFifo32 ((UINTN
)Address
, Count
, Buffer
);
533 // The CpuIoCheckParameter call above will ensure that this
534 // path is not taken.
541 for (Uint8Buffer
= (UINT8
*)Buffer
; Count
> 0; Address
+= InStride
, Uint8Buffer
+= OutStride
, Count
--) {
542 if (OperationWidth
== EfiCpuIoWidthUint8
) {
543 IoWrite8 ((UINTN
)Address
, *Uint8Buffer
);
544 } else if (OperationWidth
== EfiCpuIoWidthUint16
) {
545 IoWrite16 ((UINTN
)Address
, *((UINT16
*)Uint8Buffer
));
546 } else if (OperationWidth
== EfiCpuIoWidthUint32
) {
547 IoWrite32 ((UINTN
)Address
, *((UINT32
*)Uint8Buffer
));
555 The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
557 @param[in] ImageHandle The firmware allocated handle for the EFI image.
558 @param[in] SystemTable A pointer to the EFI System Table.
560 @retval EFI_SUCCESS The entry point is executed successfully.
561 @retval other Some error occurs when executing this entry point.
567 IN EFI_HANDLE ImageHandle
,
568 IN EFI_SYSTEM_TABLE
*SystemTable
573 ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL
, &gEfiCpuIo2ProtocolGuid
);
574 Status
= gBS
->InstallMultipleProtocolInterfaces (
576 &gEfiCpuIo2ProtocolGuid
, &mCpuIo2
,
579 ASSERT_EFI_ERROR (Status
);