2 Architectural MSR Definitions.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
24 #ifndef __ARCHITECTURAL_MSR_H__
25 #define __ARCHITECTURAL_MSR_H__
28 See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
30 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
31 @param EAX Lower 32-bits of MSR value.
32 @param EDX Upper 32-bits of MSR value.
38 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
39 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
42 #define MSR_IA32_P5_MC_ADDR 0x00000000
46 See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.
48 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
49 @param EAX Lower 32-bits of MSR value.
50 @param EDX Upper 32-bits of MSR value.
56 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
57 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
60 #define MSR_IA32_P5_MC_TYPE 0x00000001
64 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
65 at Display Family / Display Model 0F_03H.
67 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
68 @param EAX Lower 32-bits of MSR value.
69 @param EDX Upper 32-bits of MSR value.
75 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
76 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
79 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
83 See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /
86 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
87 @param EAX Lower 32-bits of MSR value.
88 @param EDX Upper 32-bits of MSR value.
94 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
95 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
98 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
102 Platform ID (RO) The operating system can use this MSR to determine "slot"
103 information for the processor and the proper microcode update to load.
104 Introduced at Display Family / Display Model 06_01H.
106 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
107 @param EAX Lower 32-bits of MSR value.
108 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
109 @param EDX Upper 32-bits of MSR value.
110 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
114 MSR_IA32_PLATFORM_ID_REGISTER Msr;
116 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
119 #define MSR_IA32_PLATFORM_ID 0x00000017
122 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
126 /// Individual bit fields
132 /// [Bits 52:50] Platform Id (RO) Contains information concerning the
133 /// intended platform for the processor.
136 /// 0 0 0 Processor Flag 0.
137 /// 0 0 1 Processor Flag 1
138 /// 0 1 0 Processor Flag 2
139 /// 0 1 1 Processor Flag 3
140 /// 1 0 0 Processor Flag 4
141 /// 1 0 1 Processor Flag 5
142 /// 1 1 0 Processor Flag 6
143 /// 1 1 1 Processor Flag 7
149 /// All bit fields as a 64-bit value
152 } MSR_IA32_PLATFORM_ID_REGISTER
;
158 @param ECX MSR_IA32_APIC_BASE (0x0000001B)
159 @param EAX Lower 32-bits of MSR value.
160 Described by the type MSR_IA32_APIC_BASE_REGISTER.
161 @param EDX Upper 32-bits of MSR value.
162 Described by the type MSR_IA32_APIC_BASE_REGISTER.
166 MSR_IA32_APIC_BASE_REGISTER Msr;
168 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
169 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
172 #define MSR_IA32_APIC_BASE 0x0000001B
175 MSR information returned for MSR index #MSR_IA32_APIC_BASE
179 /// Individual bit fields
184 /// [Bit 8] BSP flag (R/W).
189 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
194 /// [Bit 11] APIC Global Enable (R/W).
198 /// [Bits 31:12] APIC Base (R/W).
202 /// [Bits 63:32] APIC Base (R/W).
204 UINT32 ApicBaseHi
:32;
207 /// All bit fields as a 64-bit value
210 } MSR_IA32_APIC_BASE_REGISTER
;
214 Control Features in Intel 64 Processor (R/W). If any one enumeration
215 condition for defined bit field holds.
217 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
218 @param EAX Lower 32-bits of MSR value.
219 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
220 @param EDX Upper 32-bits of MSR value.
221 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
225 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
227 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
228 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
231 #define MSR_IA32_FEATURE_CONTROL 0x0000003A
234 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
238 /// Individual bit fields
242 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
243 /// being written, writes to this bit will result in GP(0). Note: Once the
244 /// Lock bit is set, the contents of this register cannot be modified.
245 /// Therefore the lock bit must be set after configuring support for Intel
246 /// Virtualization Technology and prior to transferring control to an
247 /// option ROM or the OS. Hence, once the Lock bit is set, the entire
248 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
249 /// is not deasserted. If any one enumeration condition for defined bit
250 /// field position greater than bit 0 holds.
254 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
255 /// system executive to use VMX in conjunction with SMX to support
256 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
257 /// when the CPUID function 1 returns VMX feature flag and SMX feature
258 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
259 /// CPUID.01H:ECX[6] = 1.
261 UINT32 EnableVmxInsideSmx
:1;
263 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
264 /// for system executive that do not require SMX. BIOS must set this bit
265 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
266 /// 5). If CPUID.01H:ECX[5] = 1.
268 UINT32 EnableVmxOutsideSmx
:1;
271 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
272 /// in the field represents an enable control for a corresponding SENTER
273 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
274 /// CPUID.01H:ECX[6] = 1.
276 UINT32 SenterLocalFunctionEnables
:7;
278 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
279 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
280 /// 6] is set. If CPUID.01H:ECX[6] = 1.
282 UINT32 SenterGlobalEnable
:1;
285 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
286 /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is
287 /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
292 /// [Bit 20] LMCE On (R/WL): When set, system software can program the
293 /// MSRs associated with LMCE to configure delivery of some machine check
294 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
301 /// All bit fields as a 32-bit value
305 /// All bit fields as a 64-bit value
308 } MSR_IA32_FEATURE_CONTROL_REGISTER
;
312 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
313 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
314 a logical processor. Reset value is Zero. A write to IA32_TSC will modify
315 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
316 not affect the internal invariant TSC hardware.
318 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
319 @param EAX Lower 32-bits of MSR value.
320 @param EDX Upper 32-bits of MSR value.
326 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
327 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
330 #define MSR_IA32_TSC_ADJUST 0x0000003B
334 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
335 microcode update to be loaded into the processor. See Section 9.11.6,
336 "Microcode Update Loader." A processor may prevent writing to this MSR when
337 loading guest states on VM entries or saving guest states on VM exits.
338 Introduced at Display Family / Display Model 06_01H.
340 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
341 @param EAX Lower 32-bits of MSR value.
342 @param EDX Upper 32-bits of MSR value.
349 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
352 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
356 BIOS Update Signature (RO) Returns the microcode update signature following
357 the execution of CPUID.01H. A processor may prevent writing to this MSR when
358 loading guest states on VM entries or saving guest states on VM exits.
359 Introduced at Display Family / Display Model 06_01H.
361 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
362 @param EAX Lower 32-bits of MSR value.
363 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
364 @param EDX Upper 32-bits of MSR value.
365 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
369 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
371 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
374 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B
377 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
381 /// Individual bit fields
386 /// [Bits 63:32] Microcode update signature. This field contains the
387 /// signature of the currently loaded microcode update when read following
388 /// the execution of the CPUID instruction, function 1. It is required
389 /// that this register field be pre-loaded with zero prior to executing
390 /// the CPUID, function 1. If the field remains equal to zero, then there
391 /// is no microcode update loaded. Another nonzero value will be the
394 UINT32 MicrocodeUpdateSignature
:32;
397 /// All bit fields as a 64-bit value
400 } MSR_IA32_BIOS_SIGN_ID_REGISTER
;
404 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1. CPUID.01H: ECX[6] =
407 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
408 @param EAX Lower 32-bits of MSR value.
409 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
410 @param EDX Upper 32-bits of MSR value.
411 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
415 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
417 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
418 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
421 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
424 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
428 /// Individual bit fields
432 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
433 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
434 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
435 /// if the bit is 0. This bit is cleared when the logical processor is
441 /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
442 /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
443 /// unless bit 2 is 1 (the value of bit 0 is irrelevant).
448 /// [Bits 31:12] MSEG Base (R/W).
454 /// All bit fields as a 32-bit value
458 /// All bit fields as a 64-bit value
461 } MSR_IA32_SMM_MONITOR_CTL_REGISTER
;
465 Base address of the logical processor's SMRAM image (RO, SMM only). If
468 @param ECX MSR_IA32_SMBASE (0x0000009E)
469 @param EAX Lower 32-bits of MSR value.
470 @param EDX Upper 32-bits of MSR value.
476 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
479 #define MSR_IA32_SMBASE 0x0000009E
483 General Performance Counters (R/W).
484 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
486 @param ECX MSR_IA32_PMCn
487 @param EAX Lower 32-bits of MSR value.
488 @param EDX Upper 32-bits of MSR value.
494 Msr = AsmReadMsr64 (MSR_IA32_PMC0);
495 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
499 #define MSR_IA32_PMC0 0x000000C1
500 #define MSR_IA32_PMC1 0x000000C2
501 #define MSR_IA32_PMC2 0x000000C3
502 #define MSR_IA32_PMC3 0x000000C4
503 #define MSR_IA32_PMC4 0x000000C5
504 #define MSR_IA32_PMC5 0x000000C6
505 #define MSR_IA32_PMC6 0x000000C7
506 #define MSR_IA32_PMC7 0x000000C8
511 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
512 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
513 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
514 wrap-around of IA32_APERF.
516 @param ECX MSR_IA32_MPERF (0x000000E7)
517 @param EAX Lower 32-bits of MSR value.
518 @param EDX Upper 32-bits of MSR value.
524 Msr = AsmReadMsr64 (MSR_IA32_MPERF);
525 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
528 #define MSR_IA32_MPERF 0x000000E7
532 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
533 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
534 the coordinated clock frequency, when the logical processor is in C0.
535 Cleared upon overflow / wrap-around of IA32_MPERF.
537 @param ECX MSR_IA32_APERF (0x000000E8)
538 @param EAX Lower 32-bits of MSR value.
539 @param EDX Upper 32-bits of MSR value.
545 Msr = AsmReadMsr64 (MSR_IA32_APERF);
546 AsmWriteMsr64 (MSR_IA32_APERF, Msr);
549 #define MSR_IA32_APERF 0x000000E8
553 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
554 Introduced at Display Family / Display Model 06_01H.
556 @param ECX MSR_IA32_MTRRCAP (0x000000FE)
557 @param EAX Lower 32-bits of MSR value.
558 Described by the type MSR_IA32_MTRRCAP_REGISTER.
559 @param EDX Upper 32-bits of MSR value.
560 Described by the type MSR_IA32_MTRRCAP_REGISTER.
564 MSR_IA32_MTRRCAP_REGISTER Msr;
566 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
569 #define MSR_IA32_MTRRCAP 0x000000FE
572 MSR information returned for MSR index #MSR_IA32_MTRRCAP
576 /// Individual bit fields
580 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
585 /// [Bit 8] Fixed range MTRRs are supported when set.
590 /// [Bit 10] WC Supported when set.
594 /// [Bit 11] SMRR Supported when set.
601 /// All bit fields as a 32-bit value
605 /// All bit fields as a 64-bit value
608 } MSR_IA32_MTRRCAP_REGISTER
;
612 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
614 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
615 @param EAX Lower 32-bits of MSR value.
616 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
617 @param EDX Upper 32-bits of MSR value.
618 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
622 MSR_IA32_SYSENTER_CS_REGISTER Msr;
624 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
625 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
628 #define MSR_IA32_SYSENTER_CS 0x00000174
631 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
635 /// Individual bit fields
639 /// [Bits 15:0] CS Selector.
646 /// All bit fields as a 32-bit value
650 /// All bit fields as a 64-bit value
653 } MSR_IA32_SYSENTER_CS_REGISTER
;
657 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
659 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
660 @param EAX Lower 32-bits of MSR value.
661 @param EDX Upper 32-bits of MSR value.
667 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
668 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
671 #define MSR_IA32_SYSENTER_ESP 0x00000175
675 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
677 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
678 @param EAX Lower 32-bits of MSR value.
679 @param EDX Upper 32-bits of MSR value.
685 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
686 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
689 #define MSR_IA32_SYSENTER_EIP 0x00000176
693 Global Machine Check Capability (RO). Introduced at Display Family / Display
696 @param ECX MSR_IA32_MCG_CAP (0x00000179)
697 @param EAX Lower 32-bits of MSR value.
698 Described by the type MSR_IA32_MCG_CAP_REGISTER.
699 @param EDX Upper 32-bits of MSR value.
700 Described by the type MSR_IA32_MCG_CAP_REGISTER.
704 MSR_IA32_MCG_CAP_REGISTER Msr;
706 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
709 #define MSR_IA32_MCG_CAP 0x00000179
712 MSR information returned for MSR index #MSR_IA32_MCG_CAP
716 /// Individual bit fields
720 /// [Bits 7:0] Count: Number of reporting banks.
724 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
728 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
729 /// if this bit is set.
733 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
734 /// Introduced at Display Family / Display Model 06_01H.
738 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
739 /// if this bit is set.
744 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
745 /// registers present.
747 UINT32 MCG_EXT_CNT
:8;
749 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
755 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
756 /// firmware to be invoked when an error is detected so that it may
757 /// provide additional platform specific information in an ACPI format
758 /// "Generic Error Data Entry" that augments the data included in machine
759 /// check bank registers. Introduced at Display Family / Display Model
764 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
765 /// state in IA32_MCG_STATUS and associated MSR necessary to configure
766 /// Local Machine Check Exception (LMCE). Introduced at Display Family /
767 /// Display Model 06_3EH.
774 /// All bit fields as a 32-bit value
778 /// All bit fields as a 64-bit value
781 } MSR_IA32_MCG_CAP_REGISTER
;
785 Global Machine Check Status (R/W0). Introduced at Display Family / Display
788 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
789 @param EAX Lower 32-bits of MSR value.
790 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
791 @param EDX Upper 32-bits of MSR value.
792 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
796 MSR_IA32_MCG_STATUS_REGISTER Msr;
798 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
799 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
802 #define MSR_IA32_MCG_STATUS 0x0000017A
805 MSR information returned for MSR index #MSR_IA32_MCG_STATUS
809 /// Individual bit fields
813 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
818 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
823 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
824 /// / Display Model 06_01H.
828 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
835 /// All bit fields as a 32-bit value
839 /// All bit fields as a 64-bit value
842 } MSR_IA32_MCG_STATUS_REGISTER
;
846 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
848 @param ECX MSR_IA32_MCG_CTL (0x0000017B)
849 @param EAX Lower 32-bits of MSR value.
850 @param EDX Upper 32-bits of MSR value.
856 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
857 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
860 #define MSR_IA32_MCG_CTL 0x0000017B
864 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
866 @param ECX MSR_IA32_PERFEVTSELn
867 @param EAX Lower 32-bits of MSR value.
868 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
869 @param EDX Upper 32-bits of MSR value.
870 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
874 MSR_IA32_PERFEVTSEL_REGISTER Msr;
876 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
877 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
881 #define MSR_IA32_PERFEVTSEL0 0x00000186
882 #define MSR_IA32_PERFEVTSEL1 0x00000187
883 #define MSR_IA32_PERFEVTSEL2 0x00000188
884 #define MSR_IA32_PERFEVTSEL3 0x00000189
888 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
889 #MSR_IA32_PERFEVTSEL3
893 /// Individual bit fields
897 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
899 UINT32 EventSelect
:8;
901 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
902 /// detect on the selected event logic.
906 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
910 /// [Bit 17] OS: Counts while in privilege level is ring 0.
914 /// [Bit 18] Edge: Enables edge detection if set.
918 /// [Bit 19] PC: enables pin control.
922 /// [Bit 20] INT: enables interrupt on counter overflow.
926 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
927 /// event conditions occurring across all logical processors sharing a
928 /// processor core. When set to 0, the counter only increments the
929 /// associated event conditions occurring in the logical processor which
930 /// programmed the MSR.
934 /// [Bit 22] EN: enables the corresponding performance counter to commence
935 /// counting when this bit is set.
939 /// [Bit 23] INV: invert the CMASK.
943 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
944 /// performance counter increments each cycle if the event count is
945 /// greater than or equal to the CMASK.
951 /// All bit fields as a 32-bit value
955 /// All bit fields as a 64-bit value
958 } MSR_IA32_PERFEVTSEL_REGISTER
;
962 Current performance state(P-State) operating point (RO). Introduced at
963 Display Family / Display Model 0F_03H.
965 @param ECX MSR_IA32_PERF_STATUS (0x00000198)
966 @param EAX Lower 32-bits of MSR value.
967 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
968 @param EDX Upper 32-bits of MSR value.
969 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
973 MSR_IA32_PERF_STATUS_REGISTER Msr;
975 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
978 #define MSR_IA32_PERF_STATUS 0x00000198
981 MSR information returned for MSR index #MSR_IA32_PERF_STATUS
985 /// Individual bit fields
989 /// [Bits 15:0] Current performance State Value.
996 /// All bit fields as a 32-bit value
1000 /// All bit fields as a 64-bit value
1003 } MSR_IA32_PERF_STATUS_REGISTER
;
1007 (R/W). Introduced at Display Family / Display Model 0F_03H.
1009 @param ECX MSR_IA32_PERF_CTL (0x00000199)
1010 @param EAX Lower 32-bits of MSR value.
1011 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1012 @param EDX Upper 32-bits of MSR value.
1013 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1015 <b>Example usage</b>
1017 MSR_IA32_PERF_CTL_REGISTER Msr;
1019 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
1020 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
1023 #define MSR_IA32_PERF_CTL 0x00000199
1026 MSR information returned for MSR index #MSR_IA32_PERF_CTL
1030 /// Individual bit fields
1034 /// [Bits 15:0] Target performance State Value.
1036 UINT32 TargetState
:16;
1037 UINT32 Reserved1
:16;
1039 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
1043 UINT32 Reserved2
:31;
1046 /// All bit fields as a 64-bit value
1049 } MSR_IA32_PERF_CTL_REGISTER
;
1053 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
1054 Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.
1056 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
1057 @param EAX Lower 32-bits of MSR value.
1058 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1059 @param EDX Upper 32-bits of MSR value.
1060 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1062 <b>Example usage</b>
1064 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
1066 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
1067 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
1070 #define MSR_IA32_CLOCK_MODULATION 0x0000019A
1073 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
1077 /// Individual bit fields
1081 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
1082 /// CPUID.06H:EAX[5] = 1.
1084 UINT32 ExtendedOnDemandClockModulationDutyCycle
:1;
1086 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
1087 /// values for target duty cycle modulation.
1089 UINT32 OnDemandClockModulationDutyCycle
:3;
1091 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
1093 UINT32 OnDemandClockModulationEnable
:1;
1094 UINT32 Reserved1
:27;
1095 UINT32 Reserved2
:32;
1098 /// All bit fields as a 32-bit value
1102 /// All bit fields as a 64-bit value
1105 } MSR_IA32_CLOCK_MODULATION_REGISTER
;
1109 Thermal Interrupt Control (R/W) Enables and disables the generation of an
1110 interrupt on temperature transitions detected with the processor's thermal
1111 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
1112 Introduced at Display Family / Display Model 0F_0H.
1114 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
1115 @param EAX Lower 32-bits of MSR value.
1116 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1117 @param EDX Upper 32-bits of MSR value.
1118 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1120 <b>Example usage</b>
1122 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
1124 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
1125 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
1128 #define MSR_IA32_THERM_INTERRUPT 0x0000019B
1131 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
1135 /// Individual bit fields
1139 /// [Bit 0] High-Temperature Interrupt Enable.
1141 UINT32 HighTempEnable
:1;
1143 /// [Bit 1] Low-Temperature Interrupt Enable.
1145 UINT32 LowTempEnable
:1;
1147 /// [Bit 2] PROCHOT# Interrupt Enable.
1149 UINT32 PROCHOT_Enable
:1;
1151 /// [Bit 3] FORCEPR# Interrupt Enable.
1153 UINT32 FORCEPR_Enable
:1;
1155 /// [Bit 4] Critical Temperature Interrupt Enable.
1157 UINT32 CriticalTempEnable
:1;
1160 /// [Bits 14:8] Threshold #1 Value.
1162 UINT32 Threshold1
:7;
1164 /// [Bit 15] Threshold #1 Interrupt Enable.
1166 UINT32 Threshold1Enable
:1;
1168 /// [Bits 22:16] Threshold #2 Value.
1170 UINT32 Threshold2
:7;
1172 /// [Bit 23] Threshold #2 Interrupt Enable.
1174 UINT32 Threshold2Enable
:1;
1176 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
1178 UINT32 PowerLimitNotificationEnable
:1;
1180 UINT32 Reserved3
:32;
1183 /// All bit fields as a 32-bit value
1187 /// All bit fields as a 64-bit value
1190 } MSR_IA32_THERM_INTERRUPT_REGISTER
;
1194 Thermal Status Information (RO) Contains status information about the
1195 processor's thermal sensor and automatic thermal monitoring facilities. See
1196 Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display
1199 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
1200 @param EAX Lower 32-bits of MSR value.
1201 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1202 @param EDX Upper 32-bits of MSR value.
1203 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1205 <b>Example usage</b>
1207 MSR_IA32_THERM_STATUS_REGISTER Msr;
1209 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
1212 #define MSR_IA32_THERM_STATUS 0x0000019C
1215 MSR information returned for MSR index #MSR_IA32_THERM_STATUS
1219 /// Individual bit fields
1223 /// [Bit 0] Thermal Status (RO):.
1225 UINT32 ThermalStatus
:1;
1227 /// [Bit 1] Thermal Status Log (R/W):.
1229 UINT32 ThermalStatusLog
:1;
1231 /// [Bit 2] PROCHOT # or FORCEPR# event (RO).
1233 UINT32 PROCHOT_FORCEPR_Event
:1;
1235 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).
1237 UINT32 PROCHOT_FORCEPR_Log
:1;
1239 /// [Bit 4] Critical Temperature Status (RO).
1241 UINT32 CriticalTempStatus
:1;
1243 /// [Bit 5] Critical Temperature Status log (R/WC0).
1245 UINT32 CriticalTempStatusLog
:1;
1247 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
1249 UINT32 ThermalThreshold1Status
:1;
1251 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1253 UINT32 ThermalThreshold1Log
:1;
1255 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
1257 UINT32 ThermalThreshold2Status
:1;
1259 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1261 UINT32 ThermalThreshold2Log
:1;
1263 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
1265 UINT32 PowerLimitStatus
:1;
1267 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
1269 UINT32 PowerLimitLog
:1;
1271 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1273 UINT32 CurrentLimitStatus
:1;
1275 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1277 UINT32 CurrentLimitLog
:1;
1279 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1281 UINT32 CrossDomainLimitStatus
:1;
1283 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1285 UINT32 CrossDomainLimitLog
:1;
1287 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
1289 UINT32 DigitalReadout
:7;
1292 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
1295 UINT32 ResolutionInDegreesCelsius
:4;
1297 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
1299 UINT32 ReadingValid
:1;
1300 UINT32 Reserved2
:32;
1303 /// All bit fields as a 32-bit value
1307 /// All bit fields as a 64-bit value
1310 } MSR_IA32_THERM_STATUS_REGISTER
;
1314 Enable Misc. Processor Features (R/W) Allows a variety of processor
1315 functions to be enabled and disabled.
1317 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
1318 @param EAX Lower 32-bits of MSR value.
1319 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1320 @param EDX Upper 32-bits of MSR value.
1321 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1323 <b>Example usage</b>
1325 MSR_IA32_MISC_ENABLE_REGISTER Msr;
1327 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
1328 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
1331 #define MSR_IA32_MISC_ENABLE 0x000001A0
1334 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
1338 /// Individual bit fields
1342 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
1343 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
1344 /// are disabled. Introduced at Display Family / Display Model 0F_0H.
1346 UINT32 FastStrings
:1;
1349 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
1350 /// this bit enables the thermal control circuit (TCC) portion of the
1351 /// Intel Thermal Monitor feature. This allows the processor to
1352 /// automatically reduce power consumption in response to TCC activation.
1353 /// 0 = Disabled. Note: In some products clearing this bit might be
1354 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
1355 /// thermal throttling will still be activated. Introduced at Display
1356 /// Family / Display Model 0F_0H.
1358 UINT32 AutomaticThermalControlCircuit
:1;
1361 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
1362 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
1363 /// Display Family / Display Model 0F_0H.
1365 UINT32 PerformanceMonitoring
:1;
1368 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
1369 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
1370 /// Display Family / Display Model 0F_0H.
1374 /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =
1375 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
1376 /// Family / Display Model 06_0FH.
1381 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
1382 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
1383 /// Technology enabled. If CPUID.01H: ECX[7] =1.
1388 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
1389 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
1390 /// indicates that MONITOR/MWAIT are not supported. Software attempts to
1391 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
1392 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
1393 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
1394 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
1395 /// in the default state. Writing this bit when the SSE3 feature flag is
1396 /// set to 0 may generate a #GP exception. Introduced at Display Family /
1397 /// Display Model 0F_03H.
1402 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
1403 /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup
1404 /// question that allows users to specify when the installed OS does not
1405 /// support CPUID functions greater than 3. Before setting this bit, BIOS
1406 /// must execute the CPUID.0H and examine the maximum value returned in
1407 /// EAX[7:0]. If the maximum value is greater than 3, the bit is
1408 /// supported. Otherwise, the bit is not supported. Writing to this bit
1409 /// when the maximum value is greater than 3 may generate a #GP exception.
1410 /// Setting this bit may cause unexpected behavior in software that
1411 /// depends on the availability of CPUID leaves greater than 3. Introduced
1412 /// at Display Family / Display Model 0F_03H.
1414 UINT32 LimitCpuidMaxval
:1;
1416 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
1417 /// disabled. xTPR messages are optional messages that allow the processor
1418 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
1420 UINT32 xTPR_Message_Disable
:1;
1424 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
1425 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
1426 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
1427 /// Execute Disable Bit feature (if available) allows the OS to enable PAE
1428 /// paging and take advantage of data only pages. BIOS must not alter the
1429 /// contents of this bit location, if XD bit is not supported. Writing
1430 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
1431 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
1434 UINT32 Reserved9
:29;
1437 /// All bit fields as a 64-bit value
1440 } MSR_IA32_MISC_ENABLE_REGISTER
;
1444 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
1446 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
1447 @param EAX Lower 32-bits of MSR value.
1448 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1449 @param EDX Upper 32-bits of MSR value.
1450 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1452 <b>Example usage</b>
1454 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
1456 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
1457 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
1460 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1463 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
1467 /// Individual bit fields
1471 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
1472 /// performance. 15 indicates preference to maximize energy saving.
1474 UINT32 PowerPolicyPreference
:4;
1475 UINT32 Reserved1
:28;
1476 UINT32 Reserved2
:32;
1479 /// All bit fields as a 32-bit value
1483 /// All bit fields as a 64-bit value
1486 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER
;
1490 Package Thermal Status Information (RO) Contains status information about
1491 the package's thermal sensor. See Section 14.8, "Package Level Thermal
1492 Management.". If CPUID.06H: EAX[6] = 1.
1494 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
1495 @param EAX Lower 32-bits of MSR value.
1496 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1497 @param EDX Upper 32-bits of MSR value.
1498 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1500 <b>Example usage</b>
1502 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
1504 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
1507 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1510 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
1514 /// Individual bit fields
1518 /// [Bit 0] Pkg Thermal Status (RO):.
1520 UINT32 ThermalStatus
:1;
1522 /// [Bit 1] Pkg Thermal Status Log (R/W):.
1524 UINT32 ThermalStatusLog
:1;
1526 /// [Bit 2] Pkg PROCHOT # event (RO).
1528 UINT32 PROCHOT_Event
:1;
1530 /// [Bit 3] Pkg PROCHOT # log (R/WC0).
1532 UINT32 PROCHOT_Log
:1;
1534 /// [Bit 4] Pkg Critical Temperature Status (RO).
1536 UINT32 CriticalTempStatus
:1;
1538 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
1540 UINT32 CriticalTempStatusLog
:1;
1542 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
1544 UINT32 ThermalThreshold1Status
:1;
1546 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
1548 UINT32 ThermalThreshold1Log
:1;
1550 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
1552 UINT32 ThermalThreshold2Status
:1;
1554 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
1556 UINT32 ThermalThreshold2Log
:1;
1558 /// [Bit 10] Pkg Power Limitation Status (RO).
1560 UINT32 PowerLimitStatus
:1;
1562 /// [Bit 11] Pkg Power Limitation log (R/WC0).
1564 UINT32 PowerLimitLog
:1;
1567 /// [Bits 22:16] Pkg Digital Readout (RO).
1569 UINT32 DigitalReadout
:7;
1571 UINT32 Reserved3
:32;
1574 /// All bit fields as a 32-bit value
1578 /// All bit fields as a 64-bit value
1581 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
;
1585 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
1586 an interrupt on temperature transitions detected with the package's thermal
1587 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
1590 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
1591 @param EAX Lower 32-bits of MSR value.
1592 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1593 @param EDX Upper 32-bits of MSR value.
1594 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1596 <b>Example usage</b>
1598 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
1600 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
1601 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
1604 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1607 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
1611 /// Individual bit fields
1615 /// [Bit 0] Pkg High-Temperature Interrupt Enable.
1617 UINT32 HighTempEnable
:1;
1619 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
1621 UINT32 LowTempEnable
:1;
1623 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
1625 UINT32 PROCHOT_Enable
:1;
1628 /// [Bit 4] Pkg Overheat Interrupt Enable.
1630 UINT32 OverheatEnable
:1;
1633 /// [Bits 14:8] Pkg Threshold #1 Value.
1635 UINT32 Threshold1
:7;
1637 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
1639 UINT32 Threshold1Enable
:1;
1641 /// [Bits 22:16] Pkg Threshold #2 Value.
1643 UINT32 Threshold2
:7;
1645 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
1647 UINT32 Threshold2Enable
:1;
1649 /// [Bit 24] Pkg Power Limit Notification Enable.
1651 UINT32 PowerLimitNotificationEnable
:1;
1653 UINT32 Reserved4
:32;
1656 /// All bit fields as a 32-bit value
1660 /// All bit fields as a 64-bit value
1663 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
;
1667 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
1670 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
1671 @param EAX Lower 32-bits of MSR value.
1672 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1673 @param EDX Upper 32-bits of MSR value.
1674 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1676 <b>Example usage</b>
1678 MSR_IA32_DEBUGCTL_REGISTER Msr;
1680 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
1681 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
1684 #define MSR_IA32_DEBUGCTL 0x000001D9
1687 MSR information returned for MSR index #MSR_IA32_DEBUGCTL
1691 /// Individual bit fields
1695 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
1696 /// running trace of the most recent branches taken by the processor in
1697 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
1701 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
1702 /// EFLAGS.TF as single-step on branches instead of single-step on
1703 /// instructions. Introduced at Display Family / Display Model 06_01H.
1708 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
1709 /// sent. Introduced at Display Family / Display Model 06_0EH.
1713 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
1714 /// be logged in a BTS buffer. Introduced at Display Family / Display
1719 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
1720 /// fashion. When this bit is set, an interrupt is generated by the BTS
1721 /// facility when the BTS buffer is full. Introduced at Display Family /
1722 /// Display Model 06_0EH.
1726 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
1727 /// Introduced at Display Family / Display Model 06_0FH.
1729 UINT32 BTS_OFF_OS
:1;
1731 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
1732 /// Introduced at Display Family / Display Model 06_0FH.
1734 UINT32 BTS_OFF_USR
:1;
1736 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
1737 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1739 UINT32 FREEZE_LBRS_ON_PMI
:1;
1741 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
1742 /// global counter control MSR are frozen (address 38FH) on a PMI request.
1743 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1745 UINT32 FREEZE_PERFMON_ON_PMI
:1;
1747 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
1748 /// receive and generate PMI on behalf of the uncore. Introduced at
1749 /// Display Family / Display Model 06_1AH.
1751 UINT32 ENABLE_UNCORE_PMI
:1;
1753 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
1754 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
1756 UINT32 FREEZE_WHILE_SMM
:1;
1758 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
1759 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
1762 UINT32 Reserved2
:16;
1763 UINT32 Reserved3
:32;
1766 /// All bit fields as a 32-bit value
1770 /// All bit fields as a 64-bit value
1773 } MSR_IA32_DEBUGCTL_REGISTER
;
1777 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
1778 If IA32_MTRRCAP.SMRR[11] = 1.
1780 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
1781 @param EAX Lower 32-bits of MSR value.
1782 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1783 @param EDX Upper 32-bits of MSR value.
1784 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1786 <b>Example usage</b>
1788 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
1790 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
1791 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
1794 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1797 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
1801 /// Individual bit fields
1805 /// [Bits 7:0] Type. Specifies memory type of the range.
1810 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
1813 UINT32 Reserved2
:32;
1816 /// All bit fields as a 32-bit value
1820 /// All bit fields as a 64-bit value
1823 } MSR_IA32_SMRR_PHYSBASE_REGISTER
;
1827 SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
1828 IA32_MTRRCAP[SMRR] = 1.
1830 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
1831 @param EAX Lower 32-bits of MSR value.
1832 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1833 @param EDX Upper 32-bits of MSR value.
1834 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1836 <b>Example usage</b>
1838 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
1840 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
1841 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
1844 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1847 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
1851 /// Individual bit fields
1854 UINT32 Reserved1
:11;
1856 /// [Bit 11] Valid Enable range mask.
1860 /// [Bits 31:12] PhysMask SMRR address range mask.
1863 UINT32 Reserved2
:32;
1866 /// All bit fields as a 32-bit value
1870 /// All bit fields as a 64-bit value
1873 } MSR_IA32_SMRR_PHYSMASK_REGISTER
;
1877 DCA Capability (R). If CPUID.01H: ECX[18] = 1.
1879 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
1880 @param EAX Lower 32-bits of MSR value.
1881 @param EDX Upper 32-bits of MSR value.
1883 <b>Example usage</b>
1887 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
1890 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1894 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
1896 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
1897 @param EAX Lower 32-bits of MSR value.
1898 @param EDX Upper 32-bits of MSR value.
1900 <b>Example usage</b>
1904 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
1905 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
1908 #define MSR_IA32_CPU_DCA_CAP 0x000001F9
1912 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
1914 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
1915 @param EAX Lower 32-bits of MSR value.
1916 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
1917 @param EDX Upper 32-bits of MSR value.
1918 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
1920 <b>Example usage</b>
1922 MSR_IA32_DCA_0_CAP_REGISTER Msr;
1924 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
1925 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
1928 #define MSR_IA32_DCA_0_CAP 0x000001FA
1931 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
1935 /// Individual bit fields
1939 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
1940 /// defeatures are set.
1942 UINT32 DCA_ACTIVE
:1;
1944 /// [Bits 2:1] TRANSACTION.
1946 UINT32 TRANSACTION
:2;
1948 /// [Bits 6:3] DCA_TYPE.
1952 /// [Bits 10:7] DCA_QUEUE_SIZE.
1954 UINT32 DCA_QUEUE_SIZE
:4;
1957 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
1963 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
1968 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
1972 UINT32 Reserved5
:32;
1975 /// All bit fields as a 32-bit value
1979 /// All bit fields as a 64-bit value
1982 } MSR_IA32_DCA_0_CAP_REGISTER
;
1986 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
1987 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
1989 @param ECX MSR_IA32_MTRR_PHYSBASEn
1990 @param EAX Lower 32-bits of MSR value.
1991 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
1992 @param EDX Upper 32-bits of MSR value.
1993 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
1995 <b>Example usage</b>
1997 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
1999 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
2000 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
2004 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2005 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2006 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2007 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2008 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2009 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2010 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2011 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2012 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2013 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2017 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
2018 #MSR_IA32_MTRR_PHYSBASE9
2022 /// Individual bit fields
2026 /// [Bits 7:0] Type. Specifies memory type of the range.
2031 /// [Bits 31:12] PhysBase. MTRR physical Base Address.
2035 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
2036 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2037 /// maximum physical address range supported by the processor. It is
2038 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2039 /// leaf 80000008H, the processor supports 36-bit physical address size,
2040 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2042 UINT32 PhysBaseHi
:32;
2045 /// All bit fields as a 64-bit value
2048 } MSR_IA32_MTRR_PHYSBASE_REGISTER
;
2052 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
2053 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2055 @param ECX MSR_IA32_MTRR_PHYSMASKn
2056 @param EAX Lower 32-bits of MSR value.
2057 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2058 @param EDX Upper 32-bits of MSR value.
2059 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2061 <b>Example usage</b>
2063 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
2065 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
2066 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
2070 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2071 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2072 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2073 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2074 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2075 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2076 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2077 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2078 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2079 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2083 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
2084 #MSR_IA32_MTRR_PHYSMASK9
2088 /// Individual bit fields
2091 UINT32 Reserved1
:11;
2093 /// [Bit 11] Valid Enable range mask.
2097 /// [Bits 31:12] PhysMask. MTRR address range mask.
2101 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
2102 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2103 /// maximum physical address range supported by the processor. It is
2104 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2105 /// leaf 80000008H, the processor supports 36-bit physical address size,
2106 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2108 UINT32 PhysMaskHi
:32;
2111 /// All bit fields as a 64-bit value
2114 } MSR_IA32_MTRR_PHYSMASK_REGISTER
;
2118 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
2120 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
2121 @param EAX Lower 32-bits of MSR value.
2122 @param EDX Upper 32-bits of MSR value.
2124 <b>Example usage</b>
2128 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
2129 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
2132 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2136 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
2138 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
2139 @param EAX Lower 32-bits of MSR value.
2140 @param EDX Upper 32-bits of MSR value.
2142 <b>Example usage</b>
2146 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
2147 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
2150 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2154 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
2156 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
2157 @param EAX Lower 32-bits of MSR value.
2158 @param EDX Upper 32-bits of MSR value.
2160 <b>Example usage</b>
2164 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
2165 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
2168 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2172 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
2174 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
2175 @param EAX Lower 32-bits of MSR value.
2176 @param EDX Upper 32-bits of MSR value.
2178 <b>Example usage</b>
2182 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
2183 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
2186 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2190 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
2192 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
2193 @param EAX Lower 32-bits of MSR value.
2194 @param EDX Upper 32-bits of MSR value.
2196 <b>Example usage</b>
2200 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
2201 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
2204 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2208 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
2210 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
2211 @param EAX Lower 32-bits of MSR value.
2212 @param EDX Upper 32-bits of MSR value.
2214 <b>Example usage</b>
2218 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
2219 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
2222 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2226 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
2228 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
2229 @param EAX Lower 32-bits of MSR value.
2230 @param EDX Upper 32-bits of MSR value.
2232 <b>Example usage</b>
2236 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
2237 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
2240 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2244 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
2246 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
2247 @param EAX Lower 32-bits of MSR value.
2248 @param EDX Upper 32-bits of MSR value.
2250 <b>Example usage</b>
2254 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
2255 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
2258 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2262 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
2264 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
2265 @param EAX Lower 32-bits of MSR value.
2266 @param EDX Upper 32-bits of MSR value.
2268 <b>Example usage</b>
2272 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
2273 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
2276 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2280 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
2282 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
2283 @param EAX Lower 32-bits of MSR value.
2284 @param EDX Upper 32-bits of MSR value.
2286 <b>Example usage</b>
2290 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
2291 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
2294 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2298 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
2300 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
2301 @param EAX Lower 32-bits of MSR value.
2302 @param EDX Upper 32-bits of MSR value.
2304 <b>Example usage</b>
2308 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
2309 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
2312 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2316 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
2318 @param ECX MSR_IA32_PAT (0x00000277)
2319 @param EAX Lower 32-bits of MSR value.
2320 Described by the type MSR_IA32_PAT_REGISTER.
2321 @param EDX Upper 32-bits of MSR value.
2322 Described by the type MSR_IA32_PAT_REGISTER.
2324 <b>Example usage</b>
2326 MSR_IA32_PAT_REGISTER Msr;
2328 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
2329 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
2332 #define MSR_IA32_PAT 0x00000277
2335 MSR information returned for MSR index #MSR_IA32_PAT
2339 /// Individual bit fields
2348 /// [Bits 10:8] PA1.
2353 /// [Bits 18:16] PA2.
2358 /// [Bits 26:24] PA3.
2363 /// [Bits 34:32] PA4.
2368 /// [Bits 42:40] PA5.
2373 /// [Bits 50:48] PA6.
2378 /// [Bits 58:56] PA7.
2384 /// All bit fields as a 64-bit value
2387 } MSR_IA32_PAT_REGISTER
;
2391 Provides the programming interface to use corrected MC error signaling
2392 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
2394 @param ECX MSR_IA32_MCn_CTL2
2395 @param EAX Lower 32-bits of MSR value.
2396 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2397 @param EDX Upper 32-bits of MSR value.
2398 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2400 <b>Example usage</b>
2402 MSR_IA32_MC_CTL2_REGISTER Msr;
2404 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
2405 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
2409 #define MSR_IA32_MC0_CTL2 0x00000280
2410 #define MSR_IA32_MC1_CTL2 0x00000281
2411 #define MSR_IA32_MC2_CTL2 0x00000282
2412 #define MSR_IA32_MC3_CTL2 0x00000283
2413 #define MSR_IA32_MC4_CTL2 0x00000284
2414 #define MSR_IA32_MC5_CTL2 0x00000285
2415 #define MSR_IA32_MC6_CTL2 0x00000286
2416 #define MSR_IA32_MC7_CTL2 0x00000287
2417 #define MSR_IA32_MC8_CTL2 0x00000288
2418 #define MSR_IA32_MC9_CTL2 0x00000289
2419 #define MSR_IA32_MC10_CTL2 0x0000028A
2420 #define MSR_IA32_MC11_CTL2 0x0000028B
2421 #define MSR_IA32_MC12_CTL2 0x0000028C
2422 #define MSR_IA32_MC13_CTL2 0x0000028D
2423 #define MSR_IA32_MC14_CTL2 0x0000028E
2424 #define MSR_IA32_MC15_CTL2 0x0000028F
2425 #define MSR_IA32_MC16_CTL2 0x00000290
2426 #define MSR_IA32_MC17_CTL2 0x00000291
2427 #define MSR_IA32_MC18_CTL2 0x00000292
2428 #define MSR_IA32_MC19_CTL2 0x00000293
2429 #define MSR_IA32_MC20_CTL2 0x00000294
2430 #define MSR_IA32_MC21_CTL2 0x00000295
2431 #define MSR_IA32_MC22_CTL2 0x00000296
2432 #define MSR_IA32_MC23_CTL2 0x00000297
2433 #define MSR_IA32_MC24_CTL2 0x00000298
2434 #define MSR_IA32_MC25_CTL2 0x00000299
2435 #define MSR_IA32_MC26_CTL2 0x0000029A
2436 #define MSR_IA32_MC27_CTL2 0x0000029B
2437 #define MSR_IA32_MC28_CTL2 0x0000029C
2438 #define MSR_IA32_MC29_CTL2 0x0000029D
2439 #define MSR_IA32_MC30_CTL2 0x0000029E
2440 #define MSR_IA32_MC31_CTL2 0x0000029F
2444 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
2445 to #MSR_IA32_MC31_CTL2
2449 /// Individual bit fields
2453 /// [Bits 14:0] Corrected error count threshold.
2455 UINT32 CorrectedErrorCountThreshold
:15;
2456 UINT32 Reserved1
:15;
2458 /// [Bit 30] CMCI_EN.
2462 UINT32 Reserved3
:32;
2465 /// All bit fields as a 32-bit value
2469 /// All bit fields as a 64-bit value
2472 } MSR_IA32_MC_CTL2_REGISTER
;
2476 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
2478 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
2479 @param EAX Lower 32-bits of MSR value.
2480 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2481 @param EDX Upper 32-bits of MSR value.
2482 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2484 <b>Example usage</b>
2486 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
2488 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2489 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
2492 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2495 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
2499 /// Individual bit fields
2503 /// [Bits 2:0] Default Memory Type.
2508 /// [Bit 10] Fixed Range MTRR Enable.
2512 /// [Bit 11] MTRR Enable.
2515 UINT32 Reserved2
:20;
2516 UINT32 Reserved3
:32;
2519 /// All bit fields as a 32-bit value
2523 /// All bit fields as a 64-bit value
2526 } MSR_IA32_MTRR_DEF_TYPE_REGISTER
;
2530 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
2531 CPUID.0AH: EDX[4:0] > 0.
2533 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
2534 @param EAX Lower 32-bits of MSR value.
2535 @param EDX Upper 32-bits of MSR value.
2537 <b>Example usage</b>
2541 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
2542 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
2545 #define MSR_IA32_FIXED_CTR0 0x00000309
2549 Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.
2550 If CPUID.0AH: EDX[4:0] > 1.
2552 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
2553 @param EAX Lower 32-bits of MSR value.
2554 @param EDX Upper 32-bits of MSR value.
2556 <b>Example usage</b>
2560 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
2561 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
2564 #define MSR_IA32_FIXED_CTR1 0x0000030A
2568 Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.
2569 If CPUID.0AH: EDX[4:0] > 2.
2571 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
2572 @param EAX Lower 32-bits of MSR value.
2573 @param EDX Upper 32-bits of MSR value.
2575 <b>Example usage</b>
2579 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
2580 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
2583 #define MSR_IA32_FIXED_CTR2 0x0000030B
2587 RO. If CPUID.01H: ECX[15] = 1.
2589 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
2590 @param EAX Lower 32-bits of MSR value.
2591 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2592 @param EDX Upper 32-bits of MSR value.
2593 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2595 <b>Example usage</b>
2597 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
2599 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
2600 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
2603 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
2606 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
2610 /// Individual bit fields
2614 /// [Bits 5:0] LBR format.
2618 /// [Bit 6] PEBS Trap.
2622 /// [Bit 7] PEBSSaveArchRegs.
2624 UINT32 PEBS_ARCH_REG
:1;
2626 /// [Bits 11:8] PEBS Record Format.
2628 UINT32 PEBS_REC_FMT
:4;
2630 /// [Bit 12] 1: Freeze while SMM is supported.
2632 UINT32 SMM_FREEZE
:1;
2634 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
2637 UINT32 Reserved1
:18;
2638 UINT32 Reserved2
:32;
2641 /// All bit fields as a 32-bit value
2645 /// All bit fields as a 64-bit value
2648 } MSR_IA32_PERF_CAPABILITIES_REGISTER
;
2652 Fixed-Function Performance Counter Control (R/W) Counter increments while
2653 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
2654 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
2657 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
2658 @param EAX Lower 32-bits of MSR value.
2659 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2660 @param EDX Upper 32-bits of MSR value.
2661 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2663 <b>Example usage</b>
2665 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
2667 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
2668 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
2671 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2674 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
2678 /// Individual bit fields
2682 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
2686 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
2690 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
2691 /// event conditions occurring across all logical processors sharing a
2692 /// processor core. When set to 0, the counter only increments the
2693 /// associated event conditions occurring in the logical processor which
2694 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2696 UINT32 AnyThread0
:1;
2698 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
2702 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
2706 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
2710 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
2711 /// event conditions occurring across all logical processors sharing a
2712 /// processor core. When set to 0, the counter only increments the
2713 /// associated event conditions occurring in the logical processor which
2714 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2716 UINT32 AnyThread1
:1;
2718 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
2722 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
2726 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
2730 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
2731 /// event conditions occurring across all logical processors sharing a
2732 /// processor core. When set to 0, the counter only increments the
2733 /// associated event conditions occurring in the logical processor which
2734 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2736 UINT32 AnyThread2
:1;
2738 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
2741 UINT32 Reserved1
:20;
2742 UINT32 Reserved2
:32;
2745 /// All bit fields as a 32-bit value
2749 /// All bit fields as a 64-bit value
2752 } MSR_IA32_FIXED_CTR_CTRL_REGISTER
;
2756 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
2758 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
2759 @param EAX Lower 32-bits of MSR value.
2760 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2761 @param EDX Upper 32-bits of MSR value.
2762 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2764 <b>Example usage</b>
2766 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
2768 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
2771 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2774 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
2778 /// Individual bit fields
2782 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
2787 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
2792 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
2797 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
2801 UINT32 Reserved1
:28;
2803 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
2804 /// CPUID.0AH: EAX[7:0] > 1.
2806 UINT32 Ovf_FixedCtr0
:1;
2808 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
2809 /// CPUID.0AH: EAX[7:0] > 1.
2811 UINT32 Ovf_FixedCtr1
:1;
2813 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
2814 /// CPUID.0AH: EAX[7:0] > 1.
2816 UINT32 Ovf_FixedCtr2
:1;
2817 UINT32 Reserved2
:20;
2819 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
2820 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
2821 /// && IA32_RTIT_CTL.ToPA = 1.
2823 UINT32 Trace_ToPA_PMI
:1;
2826 /// [Bit 58] LBR_Frz: LBRs are frozen due to -
2827 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
2828 /// CPUID.0AH: EAX[7:0] > 3.
2832 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
2833 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
2834 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
2838 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
2839 /// include contributions from the direct or indirect operation intel SGX
2840 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
2844 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
2847 UINT32 Ovf_Uncore
:1;
2849 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
2854 /// [Bit 63] CondChgd: status bits of this register has changed. If
2855 /// CPUID.0AH: EAX[7:0] > 0.
2860 /// All bit fields as a 64-bit value
2863 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
;
2867 Global Performance Counter Control (R/W) Counter increments while the result
2868 of ANDing respective enable bit in this MSR with the corresponding OS or USR
2869 bits in the general-purpose or fixed counter control MSR is true. If
2870 CPUID.0AH: EAX[7:0] > 0.
2872 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
2873 @param EAX Lower 32-bits of MSR value.
2874 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
2875 @param EDX Upper 32-bits of MSR value.
2876 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
2878 <b>Example usage</b>
2880 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
2882 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
2883 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
2886 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
2889 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
2893 /// Individual bit fields
2897 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
2898 /// Enable bitmask. Only the first n-1 bits are valid.
2899 /// Bits n..31 are reserved.
2903 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
2904 /// Enable bitmask. Only the first n-1 bits are valid.
2905 /// Bits 31:n are reserved.
2907 UINT32 EN_FIXED_CTRn
:32;
2910 /// All bit fields as a 64-bit value
2913 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
;
2917 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
2918 0 && CPUID.0AH: EAX[7:0] <= 3.
2920 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
2921 @param EAX Lower 32-bits of MSR value.
2922 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
2923 @param EDX Upper 32-bits of MSR value.
2924 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
2926 <b>Example usage</b>
2928 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
2930 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
2931 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
2934 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
2937 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
2941 /// Individual bit fields
2945 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
2946 /// Clear bitmask. Only the first n-1 bits are valid.
2947 /// Bits 31:n are reserved.
2951 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
2952 /// If CPUID.0AH: EDX[4:0] > n.
2953 /// Clear bitmask. Only the first n-1 bits are valid.
2954 /// Bits 22:n are reserved.
2956 UINT32 Ovf_FIXED_CTRn
:23;
2958 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
2959 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
2961 UINT32 Trace_ToPA_PMI
:1;
2964 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
2965 /// Display Model 06_2EH.
2967 UINT32 Ovf_Uncore
:1;
2969 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
2973 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
2978 /// All bit fields as a 64-bit value
2981 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
2985 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
2988 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
2989 @param EAX Lower 32-bits of MSR value.
2990 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
2991 @param EDX Upper 32-bits of MSR value.
2992 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
2994 <b>Example usage</b>
2996 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
2998 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
2999 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
3002 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3005 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
3009 /// Individual bit fields
3013 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3014 /// Clear bitmask. Only the first n-1 bits are valid.
3015 /// Bits 31:n are reserved.
3019 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3020 /// If CPUID.0AH: EDX[4:0] > n.
3021 /// Clear bitmask. Only the first n-1 bits are valid.
3022 /// Bits 22:n are reserved.
3024 UINT32 Ovf_FIXED_CTRn
:23;
3026 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3027 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
3029 UINT32 Trace_ToPA_PMI
:1;
3032 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3036 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3040 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
3044 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3045 /// Display Model 06_2EH.
3047 UINT32 Ovf_Uncore
:1;
3049 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3053 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3058 /// All bit fields as a 64-bit value
3061 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
3065 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
3068 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
3069 @param EAX Lower 32-bits of MSR value.
3070 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3071 @param EDX Upper 32-bits of MSR value.
3072 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3074 <b>Example usage</b>
3076 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
3078 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
3079 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
3082 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3085 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
3089 /// Individual bit fields
3093 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
3094 /// Set bitmask. Only the first n-1 bits are valid.
3095 /// Bits 31:n are reserved.
3099 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
3100 /// If CPUID.0AH: EAX[7:0] > n.
3101 /// Set bitmask. Only the first n-1 bits are valid.
3102 /// Bits 22:n are reserved.
3104 UINT32 Ovf_FIXED_CTRn
:23;
3106 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
3108 UINT32 Trace_ToPA_PMI
:1;
3111 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3115 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3119 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
3123 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
3125 UINT32 Ovf_Uncore
:1;
3127 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
3133 /// All bit fields as a 64-bit value
3136 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
3140 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3143 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
3144 @param EAX Lower 32-bits of MSR value.
3145 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3146 @param EDX Upper 32-bits of MSR value.
3147 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3149 <b>Example usage</b>
3151 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
3153 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
3156 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3159 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
3163 /// Individual bit fields
3167 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
3168 /// Status bitmask. Only the first n-1 bits are valid.
3169 /// Bits 31:n are reserved.
3171 UINT32 IA32_PERFEVTSELn
:32;
3173 /// [Bits 62:32] IA32_FIXED_CTRn in use.
3174 /// If CPUID.0AH: EAX[7:0] > n.
3175 /// Status bitmask. Only the first n-1 bits are valid.
3176 /// Bits 30:n are reserved.
3178 UINT32 IA32_FIXED_CTRn
:31;
3180 /// [Bit 63] PMI in use.
3185 /// All bit fields as a 64-bit value
3188 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
;
3194 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
3195 @param EAX Lower 32-bits of MSR value.
3196 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3197 @param EDX Upper 32-bits of MSR value.
3198 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3200 <b>Example usage</b>
3202 MSR_IA32_PEBS_ENABLE_REGISTER Msr;
3204 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
3205 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
3208 #define MSR_IA32_PEBS_ENABLE 0x000003F1
3211 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
3215 /// Individual bit fields
3219 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
3220 /// Display Model 06_0FH.
3224 /// [Bits 3:1] Reserved or Model specific.
3227 UINT32 Reserved2
:28;
3229 /// [Bits 35:32] Reserved or Model specific.
3232 UINT32 Reserved4
:28;
3235 /// All bit fields as a 64-bit value
3238 } MSR_IA32_PEBS_ENABLE_REGISTER
;
3242 MCn_CTL. If IA32_MCG_CAP.CNT > n.
3244 @param ECX MSR_IA32_MCn_CTL
3245 @param EAX Lower 32-bits of MSR value.
3246 @param EDX Upper 32-bits of MSR value.
3248 <b>Example usage</b>
3252 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
3253 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
3257 #define MSR_IA32_MC0_CTL 0x00000400
3258 #define MSR_IA32_MC1_CTL 0x00000404
3259 #define MSR_IA32_MC2_CTL 0x00000408
3260 #define MSR_IA32_MC3_CTL 0x0000040C
3261 #define MSR_IA32_MC4_CTL 0x00000410
3262 #define MSR_IA32_MC5_CTL 0x00000414
3263 #define MSR_IA32_MC6_CTL 0x00000418
3264 #define MSR_IA32_MC7_CTL 0x0000041C
3265 #define MSR_IA32_MC8_CTL 0x00000420
3266 #define MSR_IA32_MC9_CTL 0x00000424
3267 #define MSR_IA32_MC10_CTL 0x00000428
3268 #define MSR_IA32_MC11_CTL 0x0000042C
3269 #define MSR_IA32_MC12_CTL 0x00000430
3270 #define MSR_IA32_MC13_CTL 0x00000434
3271 #define MSR_IA32_MC14_CTL 0x00000438
3272 #define MSR_IA32_MC15_CTL 0x0000043C
3273 #define MSR_IA32_MC16_CTL 0x00000440
3274 #define MSR_IA32_MC17_CTL 0x00000444
3275 #define MSR_IA32_MC18_CTL 0x00000448
3276 #define MSR_IA32_MC19_CTL 0x0000044C
3277 #define MSR_IA32_MC20_CTL 0x00000450
3278 #define MSR_IA32_MC21_CTL 0x00000454
3279 #define MSR_IA32_MC22_CTL 0x00000458
3280 #define MSR_IA32_MC23_CTL 0x0000045C
3281 #define MSR_IA32_MC24_CTL 0x00000460
3282 #define MSR_IA32_MC25_CTL 0x00000464
3283 #define MSR_IA32_MC26_CTL 0x00000468
3284 #define MSR_IA32_MC27_CTL 0x0000046C
3285 #define MSR_IA32_MC28_CTL 0x00000470
3290 MCn_STATUS. If IA32_MCG_CAP.CNT > n.
3292 @param ECX MSR_IA32_MCn_STATUS
3293 @param EAX Lower 32-bits of MSR value.
3294 @param EDX Upper 32-bits of MSR value.
3296 <b>Example usage</b>
3300 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
3301 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
3305 #define MSR_IA32_MC0_STATUS 0x00000401
3306 #define MSR_IA32_MC1_STATUS 0x00000405
3307 #define MSR_IA32_MC2_STATUS 0x00000409
3308 #define MSR_IA32_MC3_STATUS 0x0000040D
3309 #define MSR_IA32_MC4_STATUS 0x00000411
3310 #define MSR_IA32_MC5_STATUS 0x00000415
3311 #define MSR_IA32_MC6_STATUS 0x00000419
3312 #define MSR_IA32_MC7_STATUS 0x0000041D
3313 #define MSR_IA32_MC8_STATUS 0x00000421
3314 #define MSR_IA32_MC9_STATUS 0x00000425
3315 #define MSR_IA32_MC10_STATUS 0x00000429
3316 #define MSR_IA32_MC11_STATUS 0x0000042D
3317 #define MSR_IA32_MC12_STATUS 0x00000431
3318 #define MSR_IA32_MC13_STATUS 0x00000435
3319 #define MSR_IA32_MC14_STATUS 0x00000439
3320 #define MSR_IA32_MC15_STATUS 0x0000043D
3321 #define MSR_IA32_MC16_STATUS 0x00000441
3322 #define MSR_IA32_MC17_STATUS 0x00000445
3323 #define MSR_IA32_MC18_STATUS 0x00000449
3324 #define MSR_IA32_MC19_STATUS 0x0000044D
3325 #define MSR_IA32_MC20_STATUS 0x00000451
3326 #define MSR_IA32_MC21_STATUS 0x00000455
3327 #define MSR_IA32_MC22_STATUS 0x00000459
3328 #define MSR_IA32_MC23_STATUS 0x0000045D
3329 #define MSR_IA32_MC24_STATUS 0x00000461
3330 #define MSR_IA32_MC25_STATUS 0x00000465
3331 #define MSR_IA32_MC26_STATUS 0x00000469
3332 #define MSR_IA32_MC27_STATUS 0x0000046D
3333 #define MSR_IA32_MC28_STATUS 0x00000471
3338 MCn_ADDR. If IA32_MCG_CAP.CNT > n.
3340 @param ECX MSR_IA32_MCn_ADDR
3341 @param EAX Lower 32-bits of MSR value.
3342 @param EDX Upper 32-bits of MSR value.
3344 <b>Example usage</b>
3348 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
3349 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
3353 #define MSR_IA32_MC0_ADDR 0x00000402
3354 #define MSR_IA32_MC1_ADDR 0x00000406
3355 #define MSR_IA32_MC2_ADDR 0x0000040A
3356 #define MSR_IA32_MC3_ADDR 0x0000040E
3357 #define MSR_IA32_MC4_ADDR 0x00000412
3358 #define MSR_IA32_MC5_ADDR 0x00000416
3359 #define MSR_IA32_MC6_ADDR 0x0000041A
3360 #define MSR_IA32_MC7_ADDR 0x0000041E
3361 #define MSR_IA32_MC8_ADDR 0x00000422
3362 #define MSR_IA32_MC9_ADDR 0x00000426
3363 #define MSR_IA32_MC10_ADDR 0x0000042A
3364 #define MSR_IA32_MC11_ADDR 0x0000042E
3365 #define MSR_IA32_MC12_ADDR 0x00000432
3366 #define MSR_IA32_MC13_ADDR 0x00000436
3367 #define MSR_IA32_MC14_ADDR 0x0000043A
3368 #define MSR_IA32_MC15_ADDR 0x0000043E
3369 #define MSR_IA32_MC16_ADDR 0x00000442
3370 #define MSR_IA32_MC17_ADDR 0x00000446
3371 #define MSR_IA32_MC18_ADDR 0x0000044A
3372 #define MSR_IA32_MC19_ADDR 0x0000044E
3373 #define MSR_IA32_MC20_ADDR 0x00000452
3374 #define MSR_IA32_MC21_ADDR 0x00000456
3375 #define MSR_IA32_MC22_ADDR 0x0000045A
3376 #define MSR_IA32_MC23_ADDR 0x0000045E
3377 #define MSR_IA32_MC24_ADDR 0x00000462
3378 #define MSR_IA32_MC25_ADDR 0x00000466
3379 #define MSR_IA32_MC26_ADDR 0x0000046A
3380 #define MSR_IA32_MC27_ADDR 0x0000046E
3381 #define MSR_IA32_MC28_ADDR 0x00000472
3386 MCn_MISC. If IA32_MCG_CAP.CNT > n.
3388 @param ECX MSR_IA32_MCn_MISC
3389 @param EAX Lower 32-bits of MSR value.
3390 @param EDX Upper 32-bits of MSR value.
3392 <b>Example usage</b>
3396 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
3397 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
3401 #define MSR_IA32_MC0_MISC 0x00000403
3402 #define MSR_IA32_MC1_MISC 0x00000407
3403 #define MSR_IA32_MC2_MISC 0x0000040B
3404 #define MSR_IA32_MC3_MISC 0x0000040F
3405 #define MSR_IA32_MC4_MISC 0x00000413
3406 #define MSR_IA32_MC5_MISC 0x00000417
3407 #define MSR_IA32_MC6_MISC 0x0000041B
3408 #define MSR_IA32_MC7_MISC 0x0000041F
3409 #define MSR_IA32_MC8_MISC 0x00000423
3410 #define MSR_IA32_MC9_MISC 0x00000427
3411 #define MSR_IA32_MC10_MISC 0x0000042B
3412 #define MSR_IA32_MC11_MISC 0x0000042F
3413 #define MSR_IA32_MC12_MISC 0x00000433
3414 #define MSR_IA32_MC13_MISC 0x00000437
3415 #define MSR_IA32_MC14_MISC 0x0000043B
3416 #define MSR_IA32_MC15_MISC 0x0000043F
3417 #define MSR_IA32_MC16_MISC 0x00000443
3418 #define MSR_IA32_MC17_MISC 0x00000447
3419 #define MSR_IA32_MC18_MISC 0x0000044B
3420 #define MSR_IA32_MC19_MISC 0x0000044F
3421 #define MSR_IA32_MC20_MISC 0x00000453
3422 #define MSR_IA32_MC21_MISC 0x00000457
3423 #define MSR_IA32_MC22_MISC 0x0000045B
3424 #define MSR_IA32_MC23_MISC 0x0000045F
3425 #define MSR_IA32_MC24_MISC 0x00000463
3426 #define MSR_IA32_MC25_MISC 0x00000467
3427 #define MSR_IA32_MC26_MISC 0x0000046B
3428 #define MSR_IA32_MC27_MISC 0x0000046F
3429 #define MSR_IA32_MC28_MISC 0x00000473
3434 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
3435 VMX Information.". If CPUID.01H:ECX.[5] = 1.
3437 @param ECX MSR_IA32_VMX_BASIC (0x00000480)
3438 @param EAX Lower 32-bits of MSR value.
3439 @param EDX Upper 32-bits of MSR value.
3441 <b>Example usage</b>
3445 Msr = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
3448 #define MSR_IA32_VMX_BASIC 0x00000480
3452 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
3453 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
3455 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
3456 @param EAX Lower 32-bits of MSR value.
3457 @param EDX Upper 32-bits of MSR value.
3459 <b>Example usage</b>
3463 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
3466 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3470 Capability Reporting Register of Primary Processor-based VM-execution
3471 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3472 Controls.". If CPUID.01H:ECX.[5] = 1.
3474 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
3475 @param EAX Lower 32-bits of MSR value.
3476 @param EDX Upper 32-bits of MSR value.
3478 <b>Example usage</b>
3482 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
3485 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3489 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
3490 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
3492 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
3493 @param EAX Lower 32-bits of MSR value.
3494 @param EDX Upper 32-bits of MSR value.
3496 <b>Example usage</b>
3500 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
3503 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3507 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
3508 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
3510 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
3511 @param EAX Lower 32-bits of MSR value.
3512 @param EDX Upper 32-bits of MSR value.
3514 <b>Example usage</b>
3518 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
3521 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3525 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
3526 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
3528 @param ECX MSR_IA32_VMX_MISC (0x00000485)
3529 @param EAX Lower 32-bits of MSR value.
3530 @param EDX Upper 32-bits of MSR value.
3532 <b>Example usage</b>
3536 Msr = AsmReadMsr64 (MSR_IA32_VMX_MISC);
3539 #define MSR_IA32_VMX_MISC 0x00000485
3543 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
3544 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
3546 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
3547 @param EAX Lower 32-bits of MSR value.
3548 @param EDX Upper 32-bits of MSR value.
3550 <b>Example usage</b>
3554 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
3557 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
3561 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
3562 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
3564 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
3565 @param EAX Lower 32-bits of MSR value.
3566 @param EDX Upper 32-bits of MSR value.
3568 <b>Example usage</b>
3572 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
3575 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
3579 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
3580 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
3582 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
3583 @param EAX Lower 32-bits of MSR value.
3584 @param EDX Upper 32-bits of MSR value.
3586 <b>Example usage</b>
3590 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
3593 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
3597 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
3598 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
3600 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
3601 @param EAX Lower 32-bits of MSR value.
3602 @param EDX Upper 32-bits of MSR value.
3604 <b>Example usage</b>
3608 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
3611 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
3615 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
3616 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
3618 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
3619 @param EAX Lower 32-bits of MSR value.
3620 @param EDX Upper 32-bits of MSR value.
3622 <b>Example usage</b>
3626 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
3629 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
3633 Capability Reporting Register of Secondary Processor-based VM-execution
3634 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
3635 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
3637 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
3638 @param EAX Lower 32-bits of MSR value.
3639 @param EDX Upper 32-bits of MSR value.
3641 <b>Example usage</b>
3645 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
3648 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
3652 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
3653 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
3654 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
3656 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
3657 @param EAX Lower 32-bits of MSR value.
3658 @param EDX Upper 32-bits of MSR value.
3660 <b>Example usage</b>
3664 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
3667 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
3671 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
3672 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
3673 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3675 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
3676 @param EAX Lower 32-bits of MSR value.
3677 @param EDX Upper 32-bits of MSR value.
3679 <b>Example usage</b>
3683 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
3686 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
3690 Capability Reporting Register of Primary Processor-based VM-execution Flex
3691 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3692 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3694 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
3695 @param EAX Lower 32-bits of MSR value.
3696 @param EDX Upper 32-bits of MSR value.
3698 <b>Example usage</b>
3702 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
3705 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
3709 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
3710 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3712 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
3713 @param EAX Lower 32-bits of MSR value.
3714 @param EDX Upper 32-bits of MSR value.
3716 <b>Example usage</b>
3720 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
3723 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
3727 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
3728 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3730 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
3731 @param EAX Lower 32-bits of MSR value.
3732 @param EDX Upper 32-bits of MSR value.
3734 <b>Example usage</b>
3738 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
3741 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
3745 Capability Reporting Register of VMfunction Controls (R/O). If(
3746 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
3748 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
3749 @param EAX Lower 32-bits of MSR value.
3750 @param EDX Upper 32-bits of MSR value.
3752 <b>Example usage</b>
3756 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
3759 #define MSR_IA32_VMX_VMFUNC 0x00000491
3763 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
3764 IA32_PERF_CAPABILITIES[ 13] = 1.
3766 @param ECX MSR_IA32_A_PMCn
3767 @param EAX Lower 32-bits of MSR value.
3768 @param EDX Upper 32-bits of MSR value.
3770 <b>Example usage</b>
3774 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
3775 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
3779 #define MSR_IA32_A_PMC0 0x000004C1
3780 #define MSR_IA32_A_PMC1 0x000004C2
3781 #define MSR_IA32_A_PMC2 0x000004C3
3782 #define MSR_IA32_A_PMC3 0x000004C4
3783 #define MSR_IA32_A_PMC4 0x000004C5
3784 #define MSR_IA32_A_PMC5 0x000004C6
3785 #define MSR_IA32_A_PMC6 0x000004C7
3786 #define MSR_IA32_A_PMC7 0x000004C8
3791 (R/W). If IA32_MCG_CAP.LMCE_P =1.
3793 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
3794 @param EAX Lower 32-bits of MSR value.
3795 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
3796 @param EDX Upper 32-bits of MSR value.
3797 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
3799 <b>Example usage</b>
3801 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
3803 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
3804 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
3807 #define MSR_IA32_MCG_EXT_CTL 0x000004D0
3810 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
3814 /// Individual bit fields
3818 /// [Bit 0] LMCE_EN.
3821 UINT32 Reserved1
:31;
3822 UINT32 Reserved2
:32;
3825 /// All bit fields as a 32-bit value
3829 /// All bit fields as a 64-bit value
3832 } MSR_IA32_MCG_EXT_CTL_REGISTER
;
3836 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
3837 ECX=0H): EBX[2] = 1.
3839 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
3840 @param EAX Lower 32-bits of MSR value.
3841 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
3842 @param EDX Upper 32-bits of MSR value.
3843 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
3845 <b>Example usage</b>
3847 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
3849 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
3852 #define MSR_IA32_SGX_SVN_STATUS 0x00000500
3855 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
3859 /// Individual bit fields
3863 /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated
3864 /// Code Modules (ACMs)".
3867 UINT32 Reserved1
:15;
3869 /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with
3870 /// Authenticated Code Modules (ACMs)".
3872 UINT32 SGX_SVN_SINIT
:8;
3874 UINT32 Reserved3
:32;
3877 /// All bit fields as a 32-bit value
3881 /// All bit fields as a 64-bit value
3884 } MSR_IA32_SGX_SVN_STATUS_REGISTER
;
3888 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
3889 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
3892 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
3893 @param EAX Lower 32-bits of MSR value.
3894 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
3895 @param EDX Upper 32-bits of MSR value.
3896 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
3898 <b>Example usage</b>
3900 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
3902 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
3903 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
3906 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
3909 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
3913 /// Individual bit fields
3918 /// [Bits 31:7] Base physical address.
3922 /// [Bits 63:32] Base physical address.
3927 /// All bit fields as a 64-bit value
3930 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
;
3934 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
3935 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
3936 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
3938 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
3939 @param EAX Lower 32-bits of MSR value.
3940 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
3941 @param EDX Upper 32-bits of MSR value.
3942 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
3944 <b>Example usage</b>
3946 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
3948 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
3949 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
3952 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
3955 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
3959 /// Individual bit fields
3964 /// [Bits 31:7] MaskOrTableOffset.
3966 UINT32 MaskOrTableOffset
:25;
3968 /// [Bits 63:32] Output Offset.
3970 UINT32 OutputOffset
:32;
3973 /// All bit fields as a 64-bit value
3976 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
;
3980 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
3982 @param ECX MSR_IA32_RTIT_CTL (0x00000570)
3983 @param EAX Lower 32-bits of MSR value.
3984 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
3985 @param EDX Upper 32-bits of MSR value.
3986 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
3988 <b>Example usage</b>
3990 MSR_IA32_RTIT_CTL_REGISTER Msr;
3992 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
3993 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
3996 #define MSR_IA32_RTIT_CTL 0x00000570
3999 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
4003 /// Individual bit fields
4007 /// [Bit 0] TraceEn.
4011 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4024 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
4028 /// [Bit 7] CR3 filter.
4036 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4044 /// [Bit 11] DisRETC.
4049 /// [Bit 13] BranchEn.
4053 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4058 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4063 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4068 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
4072 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
4076 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
4080 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
4083 UINT32 Reserved6
:16;
4086 /// All bit fields as a 64-bit value
4089 } MSR_IA32_RTIT_CTL_REGISTER
;
4093 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4095 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
4096 @param EAX Lower 32-bits of MSR value.
4097 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4098 @param EDX Upper 32-bits of MSR value.
4099 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4101 <b>Example usage</b>
4103 MSR_IA32_RTIT_STATUS_REGISTER Msr;
4105 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
4106 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
4109 #define MSR_IA32_RTIT_STATUS 0x00000571
4112 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
4116 /// Individual bit fields
4120 /// [Bit 0] FilterEn, (writes ignored).
4121 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
4125 /// [Bit 1] ContexEn, (writes ignored).
4129 /// [Bit 2] TriggerEn, (writes ignored).
4138 /// [Bit 5] Stopped.
4141 UINT32 Reserved2
:26;
4143 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
4145 UINT32 PacketByteCnt
:17;
4146 UINT32 Reserved3
:15;
4149 /// All bit fields as a 64-bit value
4152 } MSR_IA32_RTIT_STATUS_REGISTER
;
4156 Trace Filter CR3 Match Register (R/W).
4157 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4159 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
4160 @param EAX Lower 32-bits of MSR value.
4161 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4162 @param EDX Upper 32-bits of MSR value.
4163 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4165 <b>Example usage</b>
4167 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
4169 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
4170 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
4173 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4176 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
4180 /// Individual bit fields
4185 /// [Bits 31:5] CR3[63:5] value to match.
4189 /// [Bits 63:32] CR3[63:5] value to match.
4194 /// All bit fields as a 64-bit value
4197 } MSR_IA32_RTIT_CR3_MATCH_REGISTER
;
4201 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4203 @param ECX MSR_IA32_RTIT_ADDRn_A
4204 @param EAX Lower 32-bits of MSR value.
4205 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4206 @param EDX Upper 32-bits of MSR value.
4207 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4209 <b>Example usage</b>
4211 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4213 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
4214 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
4218 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
4219 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
4220 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
4221 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
4226 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4228 @param ECX MSR_IA32_RTIT_ADDRn_B
4229 @param EAX Lower 32-bits of MSR value.
4230 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4231 @param EDX Upper 32-bits of MSR value.
4232 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4234 <b>Example usage</b>
4236 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4238 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
4239 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
4243 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
4244 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
4245 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
4246 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
4251 MSR information returned for MSR indexes
4252 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
4253 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
4257 /// Individual bit fields
4261 /// [Bits 31:0] Virtual Address.
4263 UINT32 VirtualAddress
:32;
4265 /// [Bits 47:32] Virtual Address.
4267 UINT32 VirtualAddressHi
:16;
4269 /// [Bits 63:48] SignExt_VA.
4271 UINT32 SignExt_VA
:16;
4274 /// All bit fields as a 64-bit value
4277 } MSR_IA32_RTIT_ADDR_REGISTER
;
4281 DS Save Area (R/W) Points to the linear address of the first byte of the DS
4282 buffer management area, which is used to manage the BTS and PEBS buffers.
4283 See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
4286 [Bits 31..0] The linear address of the first byte of the DS buffer
4287 management area, if not in IA-32e mode.
4289 [Bits 63..0] The linear address of the first byte of the DS buffer
4290 management area, if IA-32e mode is active.
4292 @param ECX MSR_IA32_DS_AREA (0x00000600)
4293 @param EAX Lower 32-bits of MSR value.
4294 Described by the type MSR_IA32_DS_AREA_REGISTER.
4295 @param EDX Upper 32-bits of MSR value.
4296 Described by the type MSR_IA32_DS_AREA_REGISTER.
4298 <b>Example usage</b>
4302 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
4303 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
4306 #define MSR_IA32_DS_AREA 0x00000600
4310 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
4313 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
4314 @param EAX Lower 32-bits of MSR value.
4315 @param EDX Upper 32-bits of MSR value.
4317 <b>Example usage</b>
4321 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
4322 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
4325 #define MSR_IA32_TSC_DEADLINE 0x000006E0
4329 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
4331 @param ECX MSR_IA32_PM_ENABLE (0x00000770)
4332 @param EAX Lower 32-bits of MSR value.
4333 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4334 @param EDX Upper 32-bits of MSR value.
4335 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4337 <b>Example usage</b>
4339 MSR_IA32_PM_ENABLE_REGISTER Msr;
4341 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
4342 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
4345 #define MSR_IA32_PM_ENABLE 0x00000770
4348 MSR information returned for MSR index #MSR_IA32_PM_ENABLE
4352 /// Individual bit fields
4356 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
4357 /// CPUID.06H:EAX.[7] = 1.
4359 UINT32 HWP_ENABLE
:1;
4360 UINT32 Reserved1
:31;
4361 UINT32 Reserved2
:32;
4364 /// All bit fields as a 32-bit value
4368 /// All bit fields as a 64-bit value
4371 } MSR_IA32_PM_ENABLE_REGISTER
;
4375 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
4377 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
4378 @param EAX Lower 32-bits of MSR value.
4379 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4380 @param EDX Upper 32-bits of MSR value.
4381 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4383 <b>Example usage</b>
4385 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
4387 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
4390 #define MSR_IA32_HWP_CAPABILITIES 0x00000771
4393 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
4397 /// Individual bit fields
4401 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
4402 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4404 UINT32 Highest_Performance
:8;
4406 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
4407 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4409 UINT32 Guaranteed_Performance
:8;
4411 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
4412 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4414 UINT32 Most_Efficient_Performance
:8;
4416 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
4417 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4419 UINT32 Lowest_Performance
:8;
4423 /// All bit fields as a 32-bit value
4427 /// All bit fields as a 64-bit value
4430 } MSR_IA32_HWP_CAPABILITIES_REGISTER
;
4434 Power Management Control Hints for All Logical Processors in a Package
4435 (R/W). If CPUID.06H:EAX.[11] = 1.
4437 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
4438 @param EAX Lower 32-bits of MSR value.
4439 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4440 @param EDX Upper 32-bits of MSR value.
4441 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4443 <b>Example usage</b>
4445 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
4447 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
4448 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
4451 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772
4454 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
4458 /// Individual bit fields
4462 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
4463 /// CPUID.06H:EAX.[11] = 1.
4465 UINT32 Minimum_Performance
:8;
4467 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
4468 /// CPUID.06H:EAX.[11] = 1.
4470 UINT32 Maximum_Performance
:8;
4472 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
4473 /// If CPUID.06H:EAX.[11] = 1.
4475 UINT32 Desired_Performance
:8;
4477 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
4478 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
4480 UINT32 Energy_Performance_Preference
:8;
4482 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
4483 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
4485 UINT32 Activity_Window
:10;
4489 /// All bit fields as a 64-bit value
4492 } MSR_IA32_HWP_REQUEST_PKG_REGISTER
;
4496 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
4498 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
4499 @param EAX Lower 32-bits of MSR value.
4500 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
4501 @param EDX Upper 32-bits of MSR value.
4502 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
4504 <b>Example usage</b>
4506 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
4508 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
4509 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
4512 #define MSR_IA32_HWP_INTERRUPT 0x00000773
4515 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
4519 /// Individual bit fields
4523 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
4524 /// Notifications". If CPUID.06H:EAX.[8] = 1.
4526 UINT32 EN_Guaranteed_Performance_Change
:1;
4528 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
4529 /// If CPUID.06H:EAX.[8] = 1.
4531 UINT32 EN_Excursion_Minimum
:1;
4532 UINT32 Reserved1
:30;
4533 UINT32 Reserved2
:32;
4536 /// All bit fields as a 32-bit value
4540 /// All bit fields as a 64-bit value
4543 } MSR_IA32_HWP_INTERRUPT_REGISTER
;
4547 Power Management Control Hints to a Logical Processor (R/W). If
4548 CPUID.06H:EAX.[7] = 1.
4550 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
4551 @param EAX Lower 32-bits of MSR value.
4552 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
4553 @param EDX Upper 32-bits of MSR value.
4554 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
4556 <b>Example usage</b>
4558 MSR_IA32_HWP_REQUEST_REGISTER Msr;
4560 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
4561 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
4564 #define MSR_IA32_HWP_REQUEST 0x00000774
4567 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
4571 /// Individual bit fields
4575 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
4576 /// CPUID.06H:EAX.[7] = 1.
4578 UINT32 Minimum_Performance
:8;
4580 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
4581 /// CPUID.06H:EAX.[7] = 1.
4583 UINT32 Maximum_Performance
:8;
4585 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
4586 /// If CPUID.06H:EAX.[7] = 1.
4588 UINT32 Desired_Performance
:8;
4590 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
4591 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
4593 UINT32 Energy_Performance_Preference
:8;
4595 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
4596 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
4598 UINT32 Activity_Window
:10;
4600 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
4601 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
4603 UINT32 Package_Control
:1;
4607 /// All bit fields as a 64-bit value
4610 } MSR_IA32_HWP_REQUEST_REGISTER
;
4614 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
4615 CPUID.06H:EAX.[7] = 1.
4617 @param ECX MSR_IA32_HWP_STATUS (0x00000777)
4618 @param EAX Lower 32-bits of MSR value.
4619 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
4620 @param EDX Upper 32-bits of MSR value.
4621 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
4623 <b>Example usage</b>
4625 MSR_IA32_HWP_STATUS_REGISTER Msr;
4627 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
4628 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
4631 #define MSR_IA32_HWP_STATUS 0x00000777
4634 MSR information returned for MSR index #MSR_IA32_HWP_STATUS
4638 /// Individual bit fields
4642 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
4643 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
4645 UINT32 Guaranteed_Performance_Change
:1;
4648 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
4649 /// Feedback". If CPUID.06H:EAX.[7] = 1.
4651 UINT32 Excursion_To_Minimum
:1;
4652 UINT32 Reserved2
:29;
4653 UINT32 Reserved3
:32;
4656 /// All bit fields as a 32-bit value
4660 /// All bit fields as a 64-bit value
4663 } MSR_IA32_HWP_STATUS_REGISTER
;
4667 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
4668 && IA32_APIC_BASE.[10] = 1.
4670 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
4671 @param EAX Lower 32-bits of MSR value.
4672 @param EDX Upper 32-bits of MSR value.
4674 <b>Example usage</b>
4678 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
4681 #define MSR_IA32_X2APIC_APICID 0x00000802
4685 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
4686 IA32_APIC_BASE.[10] = 1.
4688 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
4689 @param EAX Lower 32-bits of MSR value.
4690 @param EDX Upper 32-bits of MSR value.
4692 <b>Example usage</b>
4696 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
4699 #define MSR_IA32_X2APIC_VERSION 0x00000803
4703 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
4704 IA32_APIC_BASE.[10] = 1.
4706 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
4707 @param EAX Lower 32-bits of MSR value.
4708 @param EDX Upper 32-bits of MSR value.
4710 <b>Example usage</b>
4714 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
4715 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
4718 #define MSR_IA32_X2APIC_TPR 0x00000808
4722 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
4723 IA32_APIC_BASE.[10] = 1.
4725 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
4726 @param EAX Lower 32-bits of MSR value.
4727 @param EDX Upper 32-bits of MSR value.
4729 <b>Example usage</b>
4733 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
4736 #define MSR_IA32_X2APIC_PPR 0x0000080A
4740 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
4743 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
4744 @param EAX Lower 32-bits of MSR value.
4745 @param EDX Upper 32-bits of MSR value.
4747 <b>Example usage</b>
4752 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
4755 #define MSR_IA32_X2APIC_EOI 0x0000080B
4759 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
4760 IA32_APIC_BASE.[10] = 1.
4762 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
4763 @param EAX Lower 32-bits of MSR value.
4764 @param EDX Upper 32-bits of MSR value.
4766 <b>Example usage</b>
4770 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
4773 #define MSR_IA32_X2APIC_LDR 0x0000080D
4777 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
4778 && IA32_APIC_BASE.[10] = 1.
4780 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
4781 @param EAX Lower 32-bits of MSR value.
4782 @param EDX Upper 32-bits of MSR value.
4784 <b>Example usage</b>
4788 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
4789 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
4792 #define MSR_IA32_X2APIC_SIVR 0x0000080F
4796 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
4797 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
4799 @param ECX MSR_IA32_X2APIC_ISRn
4800 @param EAX Lower 32-bits of MSR value.
4801 @param EDX Upper 32-bits of MSR value.
4803 <b>Example usage</b>
4807 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
4811 #define MSR_IA32_X2APIC_ISR0 0x00000810
4812 #define MSR_IA32_X2APIC_ISR1 0x00000811
4813 #define MSR_IA32_X2APIC_ISR2 0x00000812
4814 #define MSR_IA32_X2APIC_ISR3 0x00000813
4815 #define MSR_IA32_X2APIC_ISR4 0x00000814
4816 #define MSR_IA32_X2APIC_ISR5 0x00000815
4817 #define MSR_IA32_X2APIC_ISR6 0x00000816
4818 #define MSR_IA32_X2APIC_ISR7 0x00000817
4823 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
4824 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
4826 @param ECX MSR_IA32_X2APIC_TMRn
4827 @param EAX Lower 32-bits of MSR value.
4828 @param EDX Upper 32-bits of MSR value.
4830 <b>Example usage</b>
4834 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
4838 #define MSR_IA32_X2APIC_TMR0 0x00000818
4839 #define MSR_IA32_X2APIC_TMR1 0x00000819
4840 #define MSR_IA32_X2APIC_TMR2 0x0000081A
4841 #define MSR_IA32_X2APIC_TMR3 0x0000081B
4842 #define MSR_IA32_X2APIC_TMR4 0x0000081C
4843 #define MSR_IA32_X2APIC_TMR5 0x0000081D
4844 #define MSR_IA32_X2APIC_TMR6 0x0000081E
4845 #define MSR_IA32_X2APIC_TMR7 0x0000081F
4850 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
4851 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
4853 @param ECX MSR_IA32_X2APIC_IRRn
4854 @param EAX Lower 32-bits of MSR value.
4855 @param EDX Upper 32-bits of MSR value.
4857 <b>Example usage</b>
4861 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
4865 #define MSR_IA32_X2APIC_IRR0 0x00000820
4866 #define MSR_IA32_X2APIC_IRR1 0x00000821
4867 #define MSR_IA32_X2APIC_IRR2 0x00000822
4868 #define MSR_IA32_X2APIC_IRR3 0x00000823
4869 #define MSR_IA32_X2APIC_IRR4 0x00000824
4870 #define MSR_IA32_X2APIC_IRR5 0x00000825
4871 #define MSR_IA32_X2APIC_IRR6 0x00000826
4872 #define MSR_IA32_X2APIC_IRR7 0x00000827
4877 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
4878 IA32_APIC_BASE.[10] = 1.
4880 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
4881 @param EAX Lower 32-bits of MSR value.
4882 @param EDX Upper 32-bits of MSR value.
4884 <b>Example usage</b>
4888 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
4889 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
4892 #define MSR_IA32_X2APIC_ESR 0x00000828
4896 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
4897 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
4899 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
4900 @param EAX Lower 32-bits of MSR value.
4901 @param EDX Upper 32-bits of MSR value.
4903 <b>Example usage</b>
4907 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
4908 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
4911 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
4915 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
4916 IA32_APIC_BASE.[10] = 1.
4918 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
4919 @param EAX Lower 32-bits of MSR value.
4920 @param EDX Upper 32-bits of MSR value.
4922 <b>Example usage</b>
4926 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
4927 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
4930 #define MSR_IA32_X2APIC_ICR 0x00000830
4934 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
4935 IA32_APIC_BASE.[10] = 1.
4937 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
4938 @param EAX Lower 32-bits of MSR value.
4939 @param EDX Upper 32-bits of MSR value.
4941 <b>Example usage</b>
4945 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
4946 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
4949 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
4953 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
4954 1 && IA32_APIC_BASE.[10] = 1.
4956 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
4957 @param EAX Lower 32-bits of MSR value.
4958 @param EDX Upper 32-bits of MSR value.
4960 <b>Example usage</b>
4964 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
4965 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
4968 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
4972 x2APIC LVT Performance Monitor Interrupt Register (R/W). If
4973 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
4975 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
4976 @param EAX Lower 32-bits of MSR value.
4977 @param EDX Upper 32-bits of MSR value.
4979 <b>Example usage</b>
4983 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
4984 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
4987 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834
4991 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
4992 IA32_APIC_BASE.[10] = 1.
4994 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
4995 @param EAX Lower 32-bits of MSR value.
4996 @param EDX Upper 32-bits of MSR value.
4998 <b>Example usage</b>
5002 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
5003 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
5006 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5010 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5011 IA32_APIC_BASE.[10] = 1.
5013 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
5014 @param EAX Lower 32-bits of MSR value.
5015 @param EDX Upper 32-bits of MSR value.
5017 <b>Example usage</b>
5021 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
5022 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
5025 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5029 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5030 IA32_APIC_BASE.[10] = 1.
5032 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
5033 @param EAX Lower 32-bits of MSR value.
5034 @param EDX Upper 32-bits of MSR value.
5036 <b>Example usage</b>
5040 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
5041 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
5044 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5048 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5049 IA32_APIC_BASE.[10] = 1.
5051 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
5052 @param EAX Lower 32-bits of MSR value.
5053 @param EDX Upper 32-bits of MSR value.
5055 <b>Example usage</b>
5059 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
5060 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
5063 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5067 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5068 IA32_APIC_BASE.[10] = 1.
5070 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
5071 @param EAX Lower 32-bits of MSR value.
5072 @param EDX Upper 32-bits of MSR value.
5074 <b>Example usage</b>
5078 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
5081 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5085 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5086 IA32_APIC_BASE.[10] = 1.
5088 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
5089 @param EAX Lower 32-bits of MSR value.
5090 @param EDX Upper 32-bits of MSR value.
5092 <b>Example usage</b>
5096 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
5097 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
5100 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5104 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
5105 IA32_APIC_BASE.[10] = 1.
5107 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
5108 @param EAX Lower 32-bits of MSR value.
5109 @param EDX Upper 32-bits of MSR value.
5111 <b>Example usage</b>
5116 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
5119 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5123 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
5125 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
5126 @param EAX Lower 32-bits of MSR value.
5127 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5128 @param EDX Upper 32-bits of MSR value.
5129 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5131 <b>Example usage</b>
5133 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
5135 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
5136 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
5139 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5142 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
5146 /// Individual bit fields
5150 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
5151 /// Default is 0. If CPUID.01H:ECX.[11] = 1.
5154 UINT32 Reserved1
:29;
5156 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
5157 /// lock bit is set automatically on the first SMI assertion even if not
5158 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
5162 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
5163 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
5165 UINT32 DebugOccurred
:1;
5166 UINT32 Reserved2
:32;
5169 /// All bit fields as a 32-bit value
5173 /// All bit fields as a 64-bit value
5176 } MSR_IA32_DEBUG_INTERFACE_REGISTER
;
5180 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
5182 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
5183 @param EAX Lower 32-bits of MSR value.
5184 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5185 @param EDX Upper 32-bits of MSR value.
5186 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5188 <b>Example usage</b>
5190 MSR_IA32_L3_QOS_CFG_REGISTER Msr;
5192 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
5193 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
5196 #define MSR_IA32_L3_QOS_CFG 0x00000C81
5199 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
5203 /// Individual bit fields
5207 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
5208 /// in Code and Data Prioritization (CDP) mode.
5211 UINT32 Reserved1
:31;
5212 UINT32 Reserved2
:32;
5215 /// All bit fields as a 32-bit value
5219 /// All bit fields as a 64-bit value
5222 } MSR_IA32_L3_QOS_CFG_REGISTER
;
5226 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
5229 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
5230 @param EAX Lower 32-bits of MSR value.
5231 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5232 @param EDX Upper 32-bits of MSR value.
5233 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5235 <b>Example usage</b>
5237 MSR_IA32_QM_EVTSEL_REGISTER Msr;
5239 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
5240 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
5243 #define MSR_IA32_QM_EVTSEL 0x00000C8D
5246 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
5250 /// Individual bit fields
5254 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
5260 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
5261 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
5262 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5264 UINT32 ResourceMonitoringID
:32;
5267 /// All bit fields as a 64-bit value
5270 } MSR_IA32_QM_EVTSEL_REGISTER
;
5274 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
5277 @param ECX MSR_IA32_QM_CTR (0x00000C8E)
5278 @param EAX Lower 32-bits of MSR value.
5279 Described by the type MSR_IA32_QM_CTR_REGISTER.
5280 @param EDX Upper 32-bits of MSR value.
5281 Described by the type MSR_IA32_QM_CTR_REGISTER.
5283 <b>Example usage</b>
5285 MSR_IA32_QM_CTR_REGISTER Msr;
5287 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
5290 #define MSR_IA32_QM_CTR 0x00000C8E
5293 MSR information returned for MSR index #MSR_IA32_QM_CTR
5297 /// Individual bit fields
5301 /// [Bits 31:0] Resource Monitored Data.
5303 UINT32 ResourceMonitoredData
:32;
5305 /// [Bits 61:32] Resource Monitored Data.
5307 UINT32 ResourceMonitoredDataHi
:30;
5309 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
5310 /// available or not monitored for this resource or RMID.
5312 UINT32 Unavailable
:1;
5314 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
5315 /// written to IA32_PQR_QM_EVTSEL.
5320 /// All bit fields as a 64-bit value
5323 } MSR_IA32_QM_CTR_REGISTER
;
5327 Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =
5330 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
5331 @param EAX Lower 32-bits of MSR value.
5332 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5333 @param EDX Upper 32-bits of MSR value.
5334 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5336 <b>Example usage</b>
5338 MSR_IA32_PQR_ASSOC_REGISTER Msr;
5340 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
5341 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
5344 #define MSR_IA32_PQR_ASSOC 0x00000C8F
5347 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
5351 /// Individual bit fields
5355 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
5356 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
5357 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5359 UINT32 ResourceMonitoringID
:32;
5361 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
5362 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
5363 /// ECX=0):EBX.[15] = 1 ).
5368 /// All bit fields as a 64-bit value
5371 } MSR_IA32_PQR_ASSOC_REGISTER
;
5375 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
5376 ECX=0H):EBX[14] = 1).
5378 @param ECX MSR_IA32_BNDCFGS (0x00000D90)
5379 @param EAX Lower 32-bits of MSR value.
5380 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5381 @param EDX Upper 32-bits of MSR value.
5382 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5384 <b>Example usage</b>
5386 MSR_IA32_BNDCFGS_REGISTER Msr;
5388 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
5389 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
5392 #define MSR_IA32_BNDCFGS 0x00000D90
5395 MSR information returned for MSR index #MSR_IA32_BNDCFGS
5399 /// Individual bit fields
5403 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
5407 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
5408 /// instructions in the absence of the BND prefix.
5410 UINT32 BNDPRESERVE
:1;
5413 /// [Bits 31:12] Base Address of Bound Directory.
5417 /// [Bits 63:32] Base Address of Bound Directory.
5422 /// All bit fields as a 64-bit value
5425 } MSR_IA32_BNDCFGS_REGISTER
;
5429 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
5431 @param ECX MSR_IA32_XSS (0x00000DA0)
5432 @param EAX Lower 32-bits of MSR value.
5433 Described by the type MSR_IA32_XSS_REGISTER.
5434 @param EDX Upper 32-bits of MSR value.
5435 Described by the type MSR_IA32_XSS_REGISTER.
5437 <b>Example usage</b>
5439 MSR_IA32_XSS_REGISTER Msr;
5441 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
5442 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
5445 #define MSR_IA32_XSS 0x00000DA0
5448 MSR information returned for MSR index #MSR_IA32_XSS
5452 /// Individual bit fields
5457 /// [Bit 8] Trace Packet Configuration State (R/W).
5459 UINT32 TracePacketConfigurationState
:1;
5460 UINT32 Reserved2
:23;
5461 UINT32 Reserved3
:32;
5464 /// All bit fields as a 32-bit value
5468 /// All bit fields as a 64-bit value
5471 } MSR_IA32_XSS_REGISTER
;
5475 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
5477 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
5478 @param EAX Lower 32-bits of MSR value.
5479 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
5480 @param EDX Upper 32-bits of MSR value.
5481 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
5483 <b>Example usage</b>
5485 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
5487 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
5488 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
5491 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0
5494 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
5498 /// Individual bit fields
5502 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
5503 /// logical processors in the package. See Section 14.5.2, "Package level
5504 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
5506 UINT32 HDC_Pkg_Enable
:1;
5507 UINT32 Reserved1
:31;
5508 UINT32 Reserved2
:32;
5511 /// All bit fields as a 32-bit value
5515 /// All bit fields as a 64-bit value
5518 } MSR_IA32_PKG_HDC_CTL_REGISTER
;
5522 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
5524 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
5525 @param EAX Lower 32-bits of MSR value.
5526 Described by the type MSR_IA32_PM_CTL1_REGISTER.
5527 @param EDX Upper 32-bits of MSR value.
5528 Described by the type MSR_IA32_PM_CTL1_REGISTER.
5530 <b>Example usage</b>
5532 MSR_IA32_PM_CTL1_REGISTER Msr;
5534 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
5535 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
5538 #define MSR_IA32_PM_CTL1 0x00000DB1
5541 MSR information returned for MSR index #MSR_IA32_PM_CTL1
5545 /// Individual bit fields
5549 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
5550 /// package level HDC control. See Section 14.5.3.
5551 /// If CPUID.06H:EAX.[13] = 1.
5553 UINT32 HDC_Allow_Block
:1;
5554 UINT32 Reserved1
:31;
5555 UINT32 Reserved2
:32;
5558 /// All bit fields as a 32-bit value
5562 /// All bit fields as a 64-bit value
5565 } MSR_IA32_PM_CTL1_REGISTER
;
5569 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
5570 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
5571 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
5573 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
5574 @param EAX Lower 32-bits of MSR value.
5575 @param EDX Upper 32-bits of MSR value.
5577 <b>Example usage</b>
5581 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
5584 #define MSR_IA32_THREAD_STALL 0x00000DB2
5588 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
5589 CPUID.80000001H:EDX.[2 9]).
5591 @param ECX MSR_IA32_EFER (0xC0000080)
5592 @param EAX Lower 32-bits of MSR value.
5593 Described by the type MSR_IA32_EFER_REGISTER.
5594 @param EDX Upper 32-bits of MSR value.
5595 Described by the type MSR_IA32_EFER_REGISTER.
5597 <b>Example usage</b>
5599 MSR_IA32_EFER_REGISTER Msr;
5601 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
5602 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
5605 #define MSR_IA32_EFER 0xC0000080
5608 MSR information returned for MSR index #MSR_IA32_EFER
5612 /// Individual bit fields
5616 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
5617 /// instructions in 64-bit mode.
5622 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
5628 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
5629 /// is active when set.
5633 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
5636 UINT32 Reserved3
:20;
5637 UINT32 Reserved4
:32;
5640 /// All bit fields as a 32-bit value
5644 /// All bit fields as a 64-bit value
5647 } MSR_IA32_EFER_REGISTER
;
5651 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
5653 @param ECX MSR_IA32_STAR (0xC0000081)
5654 @param EAX Lower 32-bits of MSR value.
5655 @param EDX Upper 32-bits of MSR value.
5657 <b>Example usage</b>
5661 Msr = AsmReadMsr64 (MSR_IA32_STAR);
5662 AsmWriteMsr64 (MSR_IA32_STAR, Msr);
5665 #define MSR_IA32_STAR 0xC0000081
5669 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
5671 @param ECX MSR_IA32_LSTAR (0xC0000082)
5672 @param EAX Lower 32-bits of MSR value.
5673 @param EDX Upper 32-bits of MSR value.
5675 <b>Example usage</b>
5679 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
5680 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
5683 #define MSR_IA32_LSTAR 0xC0000082
5687 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
5689 @param ECX MSR_IA32_FMASK (0xC0000084)
5690 @param EAX Lower 32-bits of MSR value.
5691 @param EDX Upper 32-bits of MSR value.
5693 <b>Example usage</b>
5697 Msr = AsmReadMsr64 (MSR_IA32_FMASK);
5698 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
5701 #define MSR_IA32_FMASK 0xC0000084
5705 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
5707 @param ECX MSR_IA32_FS_BASE (0xC0000100)
5708 @param EAX Lower 32-bits of MSR value.
5709 @param EDX Upper 32-bits of MSR value.
5711 <b>Example usage</b>
5715 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
5716 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
5719 #define MSR_IA32_FS_BASE 0xC0000100
5723 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
5725 @param ECX MSR_IA32_GS_BASE (0xC0000101)
5726 @param EAX Lower 32-bits of MSR value.
5727 @param EDX Upper 32-bits of MSR value.
5729 <b>Example usage</b>
5733 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
5734 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
5737 #define MSR_IA32_GS_BASE 0xC0000101
5741 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
5743 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
5744 @param EAX Lower 32-bits of MSR value.
5745 @param EDX Upper 32-bits of MSR value.
5747 <b>Example usage</b>
5751 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
5752 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
5755 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
5759 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
5761 @param ECX MSR_IA32_TSC_AUX (0xC0000103)
5762 @param EAX Lower 32-bits of MSR value.
5763 Described by the type MSR_IA32_TSC_AUX_REGISTER.
5764 @param EDX Upper 32-bits of MSR value.
5765 Described by the type MSR_IA32_TSC_AUX_REGISTER.
5767 <b>Example usage</b>
5769 MSR_IA32_TSC_AUX_REGISTER Msr;
5771 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
5772 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
5775 #define MSR_IA32_TSC_AUX 0xC0000103
5778 MSR information returned for MSR index #MSR_IA32_TSC_AUX
5782 /// Individual bit fields
5786 /// [Bits 31:0] AUX: Auxiliary signature of TSC.
5792 /// All bit fields as a 32-bit value
5796 /// All bit fields as a 64-bit value
5799 } MSR_IA32_TSC_AUX_REGISTER
;