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2 Coreboot PEI module include file.
4 Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
10 * This file is part of the libpayload project.
12 * Copyright (C) 2008 Advanced Micro Devices, Inc.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #ifndef _COREBOOT_PEI_H_INCLUDED_
39 #define _COREBOOT_PEI_H_INCLUDED_
41 #if defined (_MSC_VER)
42 #pragma warning( disable : 4200 )
45 #define DYN_CBMEM_ALIGN_SIZE (4096)
47 #define IMD_ENTRY_MAGIC (~0xC0389481)
48 #define CBMEM_ENTRY_MAGIC (~0xC0389479)
62 struct cbmem_entry entries
[0];
78 struct imd_entry entries
[0];
86 #define CB_HEADER_SIGNATURE 0x4F49424C
91 UINT32 header_checksum
;
93 UINT32 table_checksum
;
102 #define CB_TAG_UNUSED 0x0000
103 #define CB_TAG_MEMORY 0x0001
105 struct cb_memory_range
{
106 struct cbuint64 start
;
107 struct cbuint64 size
;
112 #define CB_MEM_RESERVED 2
113 #define CB_MEM_ACPI 3
115 #define CB_MEM_UNUSABLE 5
116 #define CB_MEM_VENDOR_RSVD 6
117 #define CB_MEM_TABLE 16
122 struct cb_memory_range map
[0];
125 #define CB_TAG_MAINBOARD 0x0003
127 struct cb_mainboard
{
131 UINT8 part_number_idx
;
135 #define CB_TAG_VERSION 0x0004
136 #define CB_TAG_EXTRA_VERSION 0x0005
137 #define CB_TAG_BUILD 0x0006
138 #define CB_TAG_COMPILE_TIME 0x0007
139 #define CB_TAG_COMPILE_BY 0x0008
140 #define CB_TAG_COMPILE_HOST 0x0009
141 #define CB_TAG_COMPILE_DOMAIN 0x000a
142 #define CB_TAG_COMPILER 0x000b
143 #define CB_TAG_LINKER 0x000c
144 #define CB_TAG_ASSEMBLER 0x000d
152 #define CB_TAG_SERIAL 0x000f
157 #define CB_SERIAL_TYPE_IO_MAPPED 1
158 #define CB_SERIAL_TYPE_MEMORY_MAPPED 2
164 // Crystal or input frequency to the chip containing the UART.
165 // Provide the board specific details to allow the payload to
166 // initialize the chip containing the UART and make independent
167 // decisions as to which dividers to select and their values
168 // to eventually arrive at the desired console baud-rate.
171 // UART PCI address: bus, device, function
172 // 1 << 31 - Valid bit, PCI UART in use
176 UINT32 uart_pci_addr
;
179 #define CB_TAG_CONSOLE 0x00010
187 #define CB_TAG_CONSOLE_SERIAL8250 0
188 #define CB_TAG_CONSOLE_VGA 1 // OBSOLETE
189 #define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
190 #define CB_TAG_CONSOLE_LOGBUF 3
191 #define CB_TAG_CONSOLE_SROM 4// OBSOLETE
192 #define CB_TAG_CONSOLE_EHCI 5
194 #define CB_TAG_FORWARD 0x00011
202 #define CB_TAG_FRAMEBUFFER 0x0012
203 struct cb_framebuffer
{
207 UINT64 physical_address
;
210 UINT32 bytes_per_line
;
211 UINT8 bits_per_pixel
;
214 UINT8 green_mask_pos
;
215 UINT8 green_mask_size
;
217 UINT8 blue_mask_size
;
218 UINT8 reserved_mask_pos
;
219 UINT8 reserved_mask_size
;
222 #define CB_TAG_VDAT 0x0015
225 UINT32 size
; /* size of the entire entry */
230 #define CB_TAG_TIMESTAMPS 0x0016
231 #define CB_TAG_CBMEM_CONSOLE 0x0017
232 #define CB_TAG_MRC_CACHE 0x0018
233 struct cb_cbmem_tab
{
241 #define MEM_RANGE_COUNT(_rec) \
242 (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
244 #define MEM_RANGE_PTR(_rec, _idx) \
245 (void *)(((UINT8 *) (_rec)) + sizeof(*(_rec)) \
246 + (sizeof((_rec)->map[0]) * (_idx)))
248 typedef struct cb_memory CB_MEMORY
;
250 #endif // _COREBOOT_PEI_H_INCLUDED_