1 /**************************************************************************;
4 ;* Intel Corporation - ACPI Reference Code for the Baytrail *;
5 ;* Family of Customer Reference Boards. *;
8 ;* Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved *;
10 ; This program and the accompanying materials are licensed and made available under
11 ; the terms and conditions of the BSD License that accompanies this distribution.
12 ; The full text of the license may be found at
13 ; http://opensource.org/licenses/bsd-license.php.
15 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 ;**************************************************************************/
26 // Define VLV ABASE I/O as an ACPI operating region. The base address
27 // can be found in Device 31, Registers 40-43h.
29 OperationRegion(PMIO, SystemIo, \PMBS, 0x46)
30 Field(PMIO, ByteAcc, NoLock, Preserve)
33 PWBS, 1, // Power Button Status
36 PMEB, 1, // PME_B0_STS
37 Offset(0x42), // General Purpose Control
41 Field(PMIO, ByteAcc, NoLock, WriteAsZeros)
43 Offset(0x20), // GPE0 Status
45 PSCI, 1, // PUNIT SCI Status
46 SCIS, 1 // GUNIT SCI Status
52 // Define a Memory Region that will allow access to the PMC
53 // Register Block. Note that in the Intel Reference Solution, the PMC
54 // will get fixed up dynamically during POST.
56 OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register
57 Field(PMCR,DWordAcc,Lock,Preserve)
59 Offset(0x00), // Function Disable Register
60 L10D, 1, // (0) LPIO1 DMA Disable
61 L11D, 1, // (1) LPIO1 PWM #1 Disable
62 L12D, 1, // (2) LPIO1 PWM #2 Disable
63 L13D, 1, // (3) LPIO1 HS-UART #1 Disable
64 L14D, 1, // (4) LPIO1 HS-UART #2 Disable
65 L15D, 1, // (5) LPIO1 SPI Disable
66 , 2, // (6:7) Reserved
67 SD1D, 1, // (8) SCC SDIO #1 Disable
68 SD2D, 1, // (9) SCC SDIO #2 Disable
69 SD3D, 1, // (10) SCC SDIO #3 Disable
71 HDAD, 1, // (12) Azalia Disable
72 LPED, 1, // (13) LPE Disable
73 OTGD, 1, // (14) USB OTG Disable
74 , 1, // (15) USH Disable
77 , 1, // (18) USB Disable
78 , 1, // (19) SEC Disable
79 RP1D, 1, // (20) Root Port 0 Disable
80 RP2D, 1, // (21) Root Port 1 Disable
81 RP3D, 1, // (22) Root Port 2 Disable
82 RP4D, 1, // (23) Root Port 3 Disable
83 L20D, 1, // (24) LPIO2 DMA Disable
84 L21D, 1, // (25) LPIO2 I2C #1 Disable
85 L22D, 1, // (26) LPIO2 I2C #2 Disable
86 L23D, 1, // (27) LPIO2 I2C #3 Disable
87 L24D, 1, // (28) LPIO2 I2C #4 Disable
88 L25D, 1, // (29) LPIO2 I2C #5 Disable
89 L26D, 1, // (30) LPIO2 I2C #6 Disable
90 L27D, 1 // (31) LPIO2 I2C #7 Disable
94 OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers
95 Field(CLKC,DWordAcc,Lock,Preserve)
97 Offset(0x00), // PLT_CLK_CTL_0
101 Offset(0x04), // PLT_CLK_CTL_1
105 Offset(0x08), // PLT_CLK_CTL_2
109 Offset(0x0C), // PLT_CLK_CTL_3
113 Offset(0x10), // PLT_CLK_CTL_4
117 Offset(0x14), // PLT_CLK_CTL_5
129 Name (_HID, "80860F28")
130 Name (_CID, "80860F28")
131 //Name (_CLS, Package (3) {0x04, 0x01, 0x00})
132 Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")
133 Name (_SUB, "80867270")
135 Name (_DEP, Package() {\_SB.I2C2.RTEK})
136 Name(_PR0,Package() {PLPE})
138 Method (_STA, 0x0, NotSerialized)
140 If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))
150 Method (_DIS, 0x0, NotSerialized)
152 //Add a dummy disable function
155 Name (RBUF, ResourceTemplate ()
157 Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO
158 Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space
159 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post
160 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
161 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}
162 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}
163 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}
164 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}
165 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
166 GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} // Audio jack interrupt
170 Method (_CRS, 0x0, NotSerialized)
172 CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
174 CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
176 CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
181 OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
182 Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
188 PowerResource(PLPE, 0, 0) // Power Resource for LPEA
192 Return (1) // Power Resource is always available.
197 And(PSAT, 0xfffffffC, PSAT)
198 OR(PSAT, 0X00000000, PSAT)
203 OR(PSAT, 0x00000003, PSAT)
204 OR(PSAT, 0X00000000, PSAT)
207 } // End "Low Power Engine Audio"
212 Name (_HID, "LPE0F28") // _HID: Hardware ID
213 Name (_CID, "LPE0F28") // _CID: Compatible ID
214 Name (_DDN, "Intel(R) SST Audio - LPE0F28") // _DDN: DOS Device Name
215 Name (_SUB, "80867270")
217 Name (_DEP, Package() {\_SB.I2C2.RTEK})
218 Name(_PR0,Package() {PLPE})
220 Method (_STA, 0x0, NotSerialized)
222 If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))
232 Method (_DIS, 0x0, NotSerialized)
234 //Add a dummy disable function
237 Name (RBUF, ResourceTemplate ()
239 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post
240 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)
241 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)
242 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)
243 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)
244 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
245 Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space
249 Method (_CRS, 0x0, NotSerialized)
251 CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
252 Add(LPE0, 0x140000, SHBA)
253 CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)
254 Add(LPE0, 0x144000, MBBA)
255 CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)
256 Add(LPE0, 0xC0000, IRBA)
257 CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)
258 Add(LPE0, 0x100000, DRBA)
259 CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
261 CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
266 OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
267 Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
273 PowerResource(PLPE, 0, 0) // Power Resource for LPEA
277 Return (1) // Power Resource is always available.
282 And(PSAT, 0xfffffffC, PSAT)
283 OR(PSAT, 0X00000000, PSAT)
288 OR(PSAT, 0x00000003, PSAT)
289 OR(PSAT, 0X00000000, PSAT)
295 Name (_ADR, Zero) // _ADR: Address
296 Name (_HID, "DMA0F28") // _HID: Hardware ID
297 Name (_CID, "DMA0F28") // _CID: Compatible ID
298 Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name
299 Name (_UID, One) // _UID: Unique ID
300 Name (RBUF, ResourceTemplate ()
302 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0) // LPE BASE + LPE DMA0 offset
303 Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM) // LPE BASE + LPE SHIM offset
304 Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
307 Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
309 CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)
310 Add(LPE0, 0x98000, D0BA)
311 CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
312 Add(LPE0, 0x140000, SHBA)
316 } // End "Low Power Engine Audio" for Android
323 // Serial ATA Host Controller - Device 19, Function 0
328 Name(_ADR,0x00130000)
330 // SATA Methods pulled in via SSDT.
333 OperationRegion(SATR, PCI_Config, 0x74,0x4)
334 Field(SATR,WordAcc,NoLock,Preserve)
336 Offset(0x00), // 0x74, PMCR
343 Method (_STA, 0x0, NotSerialized)
354 // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment
358 Name(_ADR,0x00100000)
359 OperationRegion(SDIO, PCI_Config, 0x84,0x4)
360 Field(SDIO,WordAcc,NoLock,Preserve)
362 Offset(0x00), // 0x84, PMCR
369 Method (_STA, 0x0, NotSerialized)
371 If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))
387 Name (_ADR, 0x00000008)
388 Method(_RMV, 0x0, NotSerialized)
396 // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment
400 Name(_ADR,0x00170000)
401 OperationRegion(SDIO, PCI_Config, 0x84,0x4)
402 Field(SDIO,WordAcc,NoLock,Preserve)
404 Offset(0x00), // 0x84, PMCR
411 Method (_STA, 0x0, NotSerialized)
413 If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))
429 Name (_ADR, 0x00000008)
430 Method(_RMV, 0x0, NotSerialized)
437 // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment
441 Name(_ADR,0x00120000)
443 Method (_STA, 0x0, NotSerialized)
446 // PCIM>> 0:ACPI mode 1:PCI mode
448 If (LEqual(PCIM, 0)) {
453 // If device is disabled.
465 Name (_ADR, 0x00000008)
466 Method(_RMV, 0x0, NotSerialized)
468 // SDRM = 0 non-removable;
479 // xHCI Controller - Device 20, Function 0
480 include("PchXhci.asl")
483 // High Definition Audio Controller - Device 27, Function 0
487 Name(_ADR, 0x001B0000)
488 include("PchAudio.asl")
490 Method (_STA, 0x0, NotSerialized)
502 } // end "High Definition Audio Controller"
511 Name(_ADR, 0x001C0000)
512 include("PchPcie.asl")
513 Name(_PRW, Package() {9, 4})
517 If(PICM) { Return(AR04) }// APIC mode
518 Return (PR04) // PIC Mode
520 } // end "PCIE Root Port #1"
527 Name(_ADR, 0x001C0001)
528 include("PchPcie.asl")
529 Name(_PRW, Package() {9, 4})
533 If(PICM) { Return(AR05) }// APIC mode
534 Return (PR05) // PIC Mode
537 } // end "PCIE Root Port #2"
544 Name(_ADR, 0x001C0002)
545 include("PchPcie.asl")
546 Name(_PRW, Package() {9, 4})
549 If(PICM) { Return(AR06) }// APIC mode
550 Return (PR06) // PIC Mode
553 } // end "PCIE Root Port #3"
560 Name(_ADR, 0x001C0003)
561 include("PchPcie.asl")
562 Name(_PRW, Package() {9, 4})
565 If(PICM) { Return(AR07) }// APIC mode
566 Return (PR07) // PIC Mode
569 } // end "PCIE Root Port #4"
575 // Dummy power resource for USB D3 cold support
577 PowerResource(USBC, 0, 0)
579 Method(_STA) { Return (0xF) }
585 // EHCI Controller - Device 29, Function 0
589 Name(_ADR, 0x001D0000)
590 Name(_DEP, Package(0x1)
594 include("PchEhci.asl")
595 Name(_PRW, Package() {0x0D, 4})
597 OperationRegion(USBR, PCI_Config, 0x54,0x4)
598 Field(USBR,WordAcc,NoLock,Preserve)
600 Offset(0x00), // 0x54, PMCR
607 Method (_STA, 0x0, NotSerialized)
609 If(LEqual(XHCI, 0)) //XHCI is not present. It means EHCI is there
618 Method (_RMV, 0, NotSerialized)
623 // Create a dummy PR3 method to indicate to the PCI driver
624 // that the device is capable of D3 cold
626 Method(_PR3, 0x0, NotSerialized)
628 return (Package() {\_SB.USBC})
631 } // end "EHCI Controller"
634 // SMBus Controller - Device 31, Function 3
638 Name(_ADR,0x001F0003)
639 Include("PchSmb.asl")
644 Name (_ADR, 0x001a0000) // Device 0x1a, Function 0
645 Name(_DEP, Package(0x1)
651 OperationRegion (PMEB, PCI_Config, 0x84, 0x04) //PMECTRLSTATUS
652 Field (PMEB, WordAcc, NoLock, Preserve)
655 PMEE, 1, //bit8 PMEENABLE
657 PMES, 1 //bit15 PMESTATUS
660 // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)
661 // Arg1 -- integer that contains target system state (0-4)
662 // Arg2 -- integer that contains the target device state
663 Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake
667 Method (_CRS, 0, NotSerialized)
669 Name (RBUF, ResourceTemplate ()
671 Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)
678 Return (ResourceTemplate() {})
683 If (LNotEqual(PAVP, 0))
691 } // End scope (\_SB.PCI0)