1 /**************************************************************************;
4 ;* Intel Corporation - ACPI Reference Code for the Baytrail *;
5 ;* Family of Customer Reference Boards. *;
8 ;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;
10 ; This program and the accompanying materials are licensed and made available under
11 ; the terms and conditions of the BSD License that accompanies this distribution.
12 ; The full text of the license may be found at
13 ; http://opensource.org/licenses/bsd-license.php.
15 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 ;**************************************************************************/
23 // Define various SMBus PCI Configuration Space Registers.
25 OperationRegion(SMBP,PCI_Config,0x40,0xC0)
26 Field(SMBP,DWordAcc,NoLock,Preserve)
32 // SMBus Send Byte - This function will write a single byte of
33 // data to a specific Slave Device per SMBus Send Byte Protocol.
36 // Return: Success = 1
39 Method(SSXB,2,Serialized)
41 OperationRegion(SMPB,PCI_Config,0x20,4)
42 Field(SMPB,DWordAcc,NoLock,Preserve)
48 // Define various SMBus IO Mapped Registers.
50 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
51 Field(SMBI,ByteAcc,NoLock,Preserve)
53 HSTS, 8, // 0 - Host Status Register
55 HCON, 8, // 2 - Host Control
56 HCOM, 8, // 3 - Host Command
57 TXSA, 8, // 4 - Transmit Slave Address
58 DAT0, 8, // 5 - Host Data 0
59 DAT1, 8, // 6 - Host Data 1
60 HBDR, 8, // 7 - Host Block Data
61 PECR, 8, // 8 - Packer Error Check
62 RXSA, 8, // 9 - Receive Slave Address
63 SDAT, 16, // A - Slave Data
66 // Step 1: Confirm the ICHx SMBus is ready to perform
74 // Step 2: Initiate a Send Byte.
76 Store(0,I2CE) // Ensure SMbus Mode.
77 Store(0xBF,HSTS) // Clear all but INUSE_STS.
78 Store(Arg0,TXSA) // Write Address in TXSA.
79 Store(Arg1,HCOM) // Data in HCOM.
81 // Set the SMBus Host control register to 0x48.
82 // Bit 7: = 0 = reserved
84 // Bit 5: = 0 = disregard, I2C related bit
85 // Bits 4:2: = 001 = Byte Protocol
86 // Bit 1: = 0 = Normal Function
87 // Bit 0: = 0 = Disable interrupt generation
91 // Step 3: Exit the Method correctly.
95 Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..
96 Return(1) // Return Success.
102 // SMBus Receive Byte - This function will write a single byte
103 // of data to a specific Slave Device per SMBus Receive Byte
106 // Return: Success = Byte-Size Value
107 // Failure = Word-Size Value = FFFFh.
109 Method(SRXB,1,Serialized)
111 OperationRegion(SMPB,PCI_Config,0x20,4)
112 Field(SMPB,DWordAcc,NoLock,Preserve)
118 // Define various SMBus IO Mapped Registers.
120 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
121 Field(SMBI,ByteAcc,NoLock,Preserve)
123 HSTS, 8, // 0 - Host Status Register
125 HCON, 8, // 2 - Host Control
126 HCOM, 8, // 3 - Host Command
127 TXSA, 8, // 4 - Transmit Slave Address
128 DAT0, 8, // 5 - Host Data 0
129 DAT1, 8, // 6 - Host Data 1
130 HBDR, 8, // 7 - Host Block Data
131 PECR, 8, // 8 - Packer Error Check
132 RXSA, 8, // 9 - Receive Slave Address
133 SDAT, 16, // A - Slave Data
135 // Step 1: Confirm the ICHx SMBus is ready to perform
143 // Step 2: Initiate a Receive Byte.
145 Store(0,I2CE) // Ensure SMbus Mode.
146 Store(0xBF,HSTS) // Clear all but INUSE_STS.
147 Store(Or(Arg0,1),TXSA) // Read Address in TXSA.
149 // Set the SMBus Host control register to 0x48.
150 // Bit 7: = 0 = reserved
151 // Bit 6: = 1 = start
152 // Bit 5: = 0 = disregard, I2C related bit
153 // Bits 4:2: = 001 = Byte Protocol
154 // Bit 1: = 0 = Normal Function
155 // Bit 0: = 0 = Disable interrupt generation
159 // Step 3: Exit the Method correctly.
163 Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..
164 Return(DAT0) // Return Success.
167 Return(0xFFFF) // Return Failure.
170 // SMBus Write Byte - This function will write a single byte
171 // of data to a specific Slave Device per SMBus Write Byte
176 // Return: Success = 1
179 Method(SWRB,3,Serialized)
181 OperationRegion(SMPB,PCI_Config,0x20,4)
182 Field(SMPB,DWordAcc,NoLock,Preserve)
188 // Define various SMBus IO Mapped Registers.
190 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
191 Field(SMBI,ByteAcc,NoLock,Preserve)
193 HSTS, 8, // 0 - Host Status Register
195 HCON, 8, // 2 - Host Control
196 HCOM, 8, // 3 - Host Command
197 TXSA, 8, // 4 - Transmit Slave Address
198 DAT0, 8, // 5 - Host Data 0
199 DAT1, 8, // 6 - Host Data 1
200 HBDR, 8, // 7 - Host Block Data
201 PECR, 8, // 8 - Packer Error Check
202 RXSA, 8, // 9 - Receive Slave Address
203 SDAT, 16, // A - Slave Data
205 // Step 1: Confirm the ICHx SMBus is ready to perform communication.
212 // Step 2: Initiate a Write Byte.
214 Store(0,I2CE) // Ensure SMbus Mode.
215 Store(0xBF,HSTS) // Clear all but INUSE_STS.
216 Store(Arg0,TXSA) // Write Address in TXSA.
217 Store(Arg1,HCOM) // Command in HCOM.
218 Store(Arg2,DAT0) // Data in DAT0.
220 // Set the SMBus Host control register to 0x48.
221 // Bit 7: = 0 = reserved
222 // Bit 6: = 1 = start
223 // Bit 5: = 0 = disregard, I2C related bit
224 // Bits 4:2: = 010 = Byte Data Protocol
225 // Bit 1: = 0 = Normal Function
226 // Bit 0: = 0 = Disable interrupt generation
230 // Step 3: Exit the Method correctly.
234 Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..
235 Return(1) // Return Success.
238 Return(0) // Return Failure.
241 // SMBus Read Byte - This function will read a single byte of data
242 // from a specific slave device per SMBus Read Byte Protocol.
245 // Return: Success = Byte-Size Value
246 // Failure = Word-Size Value
248 Method(SRDB,2,Serialized)
250 OperationRegion(SMPB,PCI_Config,0x20,4)
251 Field(SMPB,DWordAcc,NoLock,Preserve)
257 // Define various SMBus IO Mapped Registers.
259 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
260 Field(SMBI,ByteAcc,NoLock,Preserve)
262 HSTS, 8, // 0 - Host Status Register
264 HCON, 8, // 2 - Host Control
265 HCOM, 8, // 3 - Host Command
266 TXSA, 8, // 4 - Transmit Slave Address
267 DAT0, 8, // 5 - Host Data 0
268 DAT1, 8, // 6 - Host Data 1
269 HBDR, 8, // 7 - Host Block Data
270 PECR, 8, // 8 - Packer Error Check
271 RXSA, 8, // 9 - Receive Slave Address
272 SDAT, 16, // A - Slave Data
274 // Step 1: Confirm the ICHx SMBus is ready to perform communication.
281 // Step 2: Initiate a Read Byte.
283 Store(0,I2CE) // Ensure SMbus Mode.
284 Store(0xBF,HSTS) // Clear all but INUSE_STS.
285 Store(Or(Arg0,1),TXSA) // Read Address in TXSA.
286 Store(Arg1,HCOM) // Command in HCOM.
288 // Set the SMBus Host control register to 0x48.
289 // Bit 7: = 0 = reserved
290 // Bit 6: = 1 = start
291 // Bit 5: = 0 = disregard, I2C related bit
292 // Bits 4:2: = 010 = Byte Data Protocol
293 // Bit 1: = 0 = Normal Function
294 // Bit 0: = 0 = Disable interrupt generation
298 // Step 3: Exit the Method correctly.
302 Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..
303 Return(DAT0) // Return Success.
306 Return(0xFFFF) // Return Failure.
309 // SMBus Write Word - This function will write a single word
310 // of data to a specific Slave Device per SMBus Write Word
314 // Arg2 = Data (16 bits in size)
315 // Return: Success = 1
318 Method(SWRW,3,Serialized)
320 OperationRegion(SMPB,PCI_Config,0x20,4)
321 Field(SMPB,DWordAcc,NoLock,Preserve)
327 // Define various SMBus IO Mapped Registers.
329 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
330 Field(SMBI,ByteAcc,NoLock,Preserve)
332 HSTS, 8, // 0 - Host Status Register
334 HCON, 8, // 2 - Host Control
335 HCOM, 8, // 3 - Host Command
336 TXSA, 8, // 4 - Transmit Slave Address
337 DAT0, 8, // 5 - Host Data 0
338 DAT1, 8, // 6 - Host Data 1
339 HBDR, 8, // 7 - Host Block Data
340 PECR, 8, // 8 - Packer Error Check
341 RXSA, 8, // 9 - Receive Slave Address
342 SDAT, 16, // A - Slave Data
344 // Step 1: Confirm the ICHx SMBus is ready to perform communication.
351 // Step 2: Initiate a Write Word.
353 Store(0,I2CE) // Ensure SMbus Mode.
354 Store(0xBF,HSTS) // Clear all but INUSE_STS.
355 Store(Arg0,TXSA) // Write Address in TXSA.
356 Store(Arg1,HCOM) // Command in HCOM.
357 And(Arg2,0xFF,DAT1) // Low byte Data in DAT1.
358 And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0.
360 // Set the SMBus Host control register to 0x4C.
361 // Bit 7: = 0 = reserved
362 // Bit 6: = 1 = start
363 // Bit 5: = 0 = disregard, I2C related bit
364 // Bits 4:2: = 011 = Word Data Protocol
365 // Bit 1: = 0 = Normal Function
366 // Bit 0: = 0 = Disable interrupt generation
370 // Step 3: Exit the Method correctly.
374 Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.
375 Return(1) // Return Success.
378 Return(0) // Return Failure.
381 // SMBus Read Word - This function will read a single byte of data
382 // from a specific slave device per SMBus Read Word Protocol.
385 // Return: Success = Word-Size Value
386 // Failure = Dword-Size Value
388 Method(SRDW,2,Serialized)
390 OperationRegion(SMPB,PCI_Config,0x20,4)
391 Field(SMPB,DWordAcc,NoLock,Preserve)
397 // Define various SMBus IO Mapped Registers.
399 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
400 Field(SMBI,ByteAcc,NoLock,Preserve)
402 HSTS, 8, // 0 - Host Status Register
404 HCON, 8, // 2 - Host Control
405 HCOM, 8, // 3 - Host Command
406 TXSA, 8, // 4 - Transmit Slave Address
407 DAT0, 8, // 5 - Host Data 0
408 DAT1, 8, // 6 - Host Data 1
409 HBDR, 8, // 7 - Host Block Data
410 PECR, 8, // 8 - Packer Error Check
411 RXSA, 8, // 9 - Receive Slave Address
412 SDAT, 16, // A - Slave Data
414 // Step 1: Confirm the ICHx SMBus is ready to perform communication.
421 // Step 2: Initiate a Read Word.
423 Store(0,I2CE) // Ensure SMbus Mode.
424 Store(0xBF,HSTS) // Clear all but INUSE_STS.
425 Store(Or(Arg0,1),TXSA) // Read Address in TXSA.
426 Store(Arg1,HCOM) // Command in HCOM.
428 // Set the SMBus Host control register to 0x4C.
429 // Bit 7: = 0 = reserved
430 // Bit 6: = 1 = start
431 // Bit 5: = 0 = disregard, I2C related bit
432 // Bits 4:2: = 011 = Word Data Protocol
433 // Bit 1: = 0 = Normal Function
434 // Bit 0: = 0 = Disable interrupt generation
438 // Step 3: Exit the Method correctly.
442 Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.
443 Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success.
446 Return(0xFFFFFFFF) // Return Failure.
449 // SMBus Block Write - This function will write an entire block of data
450 // to a specific slave device per SMBus Block Write Protocol.
453 // Arg2 = Buffer of Data to Write
454 // Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write
455 // Return: Success = 1
458 Method(SBLW,4,Serialized)
460 OperationRegion(SMPB,PCI_Config,0x20,4)
461 Field(SMPB,DWordAcc,NoLock,Preserve)
467 // Define various SMBus IO Mapped Registers.
469 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
470 Field(SMBI,ByteAcc,NoLock,Preserve)
472 HSTS, 8, // 0 - Host Status Register
474 HCON, 8, // 2 - Host Control
475 HCOM, 8, // 3 - Host Command
476 TXSA, 8, // 4 - Transmit Slave Address
477 DAT0, 8, // 5 - Host Data 0
478 DAT1, 8, // 6 - Host Data 1
479 HBDR, 8, // 7 - Host Block Data
480 PECR, 8, // 8 - Packer Error Check
481 RXSA, 8, // 9 - Receive Slave Address
482 SDAT, 16, // A - Slave Data
484 // Step 1: Confirm the ICHx SMBus is ready to perform communication.
491 // Step 2: Initiate a Block Write.
493 Store(Arg3,I2CE) // Select the proper protocol.
494 Store(0xBF,HSTS) // Clear all but INUSE_STS.
495 Store(Arg0,TXSA) // Write Address in TXSA.
496 Store(Arg1,HCOM) // Command in HCOM.
497 Store(Sizeof(Arg2),DAT0) // Count in DAT0.
498 Store(0,Local1) // Init Pointer to Buffer.
499 Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register.
501 // Set the SMBus Host control register to 0x48.
502 // Bit 7: = 0 = reserved
503 // Bit 6: = 1 = start
504 // Bit 5: = 0 = disregard, I2C related bit
505 // Bits 4:2: = 101 = Block Protocol
506 // Bit 1: = 0 = Normal Function
507 // Bit 0: = 0 = Disable interrupt generation
511 // Step 3: Send the entire Block of Data.
513 While(LGreater(Sizeof(Arg2),Local1))
515 // Wait up to 200ms for Host Status to get set.
517 Store(4000,Local0) // 4000 * 50us = 200ms.
519 While(LAnd(LNot(And(HSTS,0x80)),Local0))
521 Decrement(Local0) // Decrement Count.
522 Stall(50) // Delay = 50us.
525 If(LNot(Local0)) // Timeout?
527 KILL() // Yes. Kill Communication.
528 Return(0) // Return failure.
531 Store(0x80,HSTS) // Clear Host Status.
532 Increment(Local1) // Point to Next Byte.
534 // Place next byte in HBDR if last byte has not been sent.
536 If(LGreater(Sizeof(Arg2),Local1))
538 Store(DerefOf(Index(Arg2,Local1)),HBDR)
542 // Step 4: Exit the Method correctly.
546 Or(HSTS,0xFF,HSTS) // Clear all status bits.
547 Return(1) // Return Success.
550 Return(0) // Return Failure.
553 // SMBus Block Read - This function will read a block of data from
554 // a specific slave device per SMBus Block Read Protocol.
557 // Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write
558 // Return: Success = Data Buffer (First Byte = length)
561 Method(SBLR,3,Serialized)
563 OperationRegion(SMPB,PCI_Config,0x20,4)
564 Field(SMPB,DWordAcc,NoLock,Preserve)
570 // Define various SMBus IO Mapped Registers.
572 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
573 Field(SMBI,ByteAcc,NoLock,Preserve)
575 HSTS, 8, // 0 - Host Status Register
577 HCON, 8, // 2 - Host Control
578 HCOM, 8, // 3 - Host Command
579 TXSA, 8, // 4 - Transmit Slave Address
580 DAT0, 8, // 5 - Host Data 0
581 DAT1, 8, // 6 - Host Data 1
582 HBDR, 8, // 7 - Host Block Data
583 PECR, 8, // 8 - Packer Error Check
584 RXSA, 8, // 9 - Receive Slave Address
585 SDAT, 16, // A - Slave Data
587 Name(TBUF, Buffer(256) {})
589 // Step 1: Confirm the ICHx SMBus is ready to perform communication.
596 // Step 2: Initiate a Block Read.
598 Store(Arg2,I2CE) // Select the proper protocol.
599 Store(0xBF,HSTS) // Clear all but INUSE_STS.
600 Store(Or(Arg0,1),TXSA) // Read Address in TXSA.
601 Store(Arg1,HCOM) // Command in HCOM.
603 // Set the SMBus Host control register to 0x48.
604 // Bit 7: = 0 = reserved
605 // Bit 6: = 1 = start
606 // Bit 5: = 0 = disregard, I2C related bit
607 // Bits 4:2: = 101 = Block Protocol
608 // Bit 1: = 0 = Normal Function
609 // Bit 0: = 0 = Disable interrupt generation
613 // Step 3: Wait up to 200ms to get the Data Count.
615 Store(4000,Local0) // 4000 * 50us = 200ms.
617 While(LAnd(LNot(And(HSTS,0x80)),Local0))
619 Decrement(Local0) // Decrement Count.
620 Stall(50) // Delay = 50us.
623 If(LNot(Local0)) // Timeout?
625 KILL() // Yes. Kill Communication.
626 Return(0) // Return failure.
629 Store(DAT0,Index(TBUF,0)) // Get the Data Count.
630 Store(0x80,HSTS) // Clear Host Status.
631 Store(1,Local1) // Local1 = Buffer Pointer.
633 // Step 4: Get the Block Data and store it.
635 While(LLess(Local1,DerefOf(Index(TBUF,0))))
637 // Wait up to 200ms for Host Status to get set.
639 Store(4000,Local0) // 4000 * 50us = 200ms.
641 While(LAnd(LNot(And(HSTS,0x80)),Local0))
643 Decrement(Local0) // Decrement Count.
644 Stall(50) // Delay = 50us.
647 If(LNot(Local0)) // Timeout?
649 KILL() // Yes. Kill Communication.
650 Return(0) // Return failure.
653 Store(HBDR,Index(TBUF,Local1)) // Place into Buffer.
654 Store(0x80,HSTS) // Clear Host Status.
658 // Step 5: Exit the Method correctly.
662 Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.
663 Return(TBUF) // Return Success.
666 Return(0) // Return Failure.
671 // Return: Success = 0
674 Method(STRT,0,Serialized)
676 OperationRegion(SMPB,PCI_Config,0x20,4)
677 Field(SMPB,DWordAcc,NoLock,Preserve)
683 // Define various SMBus IO Mapped Registers.
685 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
686 Field(SMBI,ByteAcc,NoLock,Preserve)
688 HSTS, 8, // 0 - Host Status Register
690 HCON, 8, // 2 - Host Control
691 HCOM, 8, // 3 - Host Command
692 TXSA, 8, // 4 - Transmit Slave Address
693 DAT0, 8, // 5 - Host Data 0
694 DAT1, 8, // 6 - Host Data 1
695 HBDR, 8, // 7 - Host Block Data
696 PECR, 8, // 8 - Packer Error Check
697 RXSA, 8, // 9 - Receive Slave Address
698 SDAT, 16, // A - Slave Data
700 // Wait up to 200ms to confirm the SMBus Semaphore has been
701 // released (In Use Status = 0). Note that the Sleep time may take
702 // longer as the This function will yield the Processor such that it
703 // may perform different tasks during the delay.
705 Store(200,Local0) // 200 * 1ms = 200ms.
709 If(And(HSTS,0x40)) // In Use Set?
711 Decrement(Local0) // Yes. Decrement Count.
712 Sleep(1) // Delay = 1ms.
713 If(LEqual(Local0,0)) // Count = 0?
715 Return(1) // Return failure.
720 Store(0,Local0) // In Use Clear. Continue.
724 // In Use Status = 0 during last read, which will make subsequent
725 // reads return In Use Status = 1 until software clears it. All
726 // software using ICHx SMBus should check this bit before initiating
727 // any SMBus communication.
729 // Wait up to 200ms to confirm the Host Interface is
730 // not processing a command.
732 Store(4000,Local0) // 4000 * 50us = 200ms.
736 If(And(HSTS,0x01)) // Host Busy Set?
738 Decrement(Local0) // Decrement Count.
739 Stall(50) // Delay = 50us.
740 If(LEqual(Local0,0)) // Count = 0?
742 KILL() // Yes. Kill Communication.
751 Return(1) // Timeout. Return failure.
754 // SMBus Completion Check
755 // Return: Success = 1
758 Method(COMP,0,Serialized)
760 OperationRegion(SMPB,PCI_Config,0x20,4)
761 Field(SMPB,DWordAcc,NoLock,Preserve)
767 // Define various SMBus IO Mapped Registers.
769 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
770 Field(SMBI,ByteAcc,NoLock,Preserve)
772 HSTS, 8, // 0 - Host Status Register
774 HCON, 8, // 2 - Host Control
775 HCOM, 8, // 3 - Host Command
776 TXSA, 8, // 4 - Transmit Slave Address
777 DAT0, 8, // 5 - Host Data 0
778 DAT1, 8, // 6 - Host Data 1
779 HBDR, 8, // 7 - Host Block Data
780 PECR, 8, // 8 - Packer Error Check
781 RXSA, 8, // 9 - Receive Slave Address
782 SDAT, 16, // A - Slave Data
784 // Wait for up to 200ms for the Completion Command
785 // Status to get set.
787 Store(4000,Local0) // 4000 * 50us = 200ms.
791 If(And(HSTS,0x02)) // Completion Status Set?
793 Return(1) // Yes. We are done.
797 Decrement(Local0) // Decrement Count.
798 Stall(50) // Delay 50us.
799 If(LEqual(Local0,0)) // Count = 0?
801 KILL() // Yes. Kill Communication.
806 Return(0) // Timeout. Return Failure.
809 // SMBus Kill Command
811 Method(KILL,0,Serialized)
813 OperationRegion(SMPB,PCI_Config,0x20,4)
814 Field(SMPB,DWordAcc,NoLock,Preserve)
820 // Define various SMBus IO Mapped Registers.
822 OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
823 Field(SMBI,ByteAcc,NoLock,Preserve)
825 HSTS, 8, // 0 - Host Status Register
827 HCON, 8, // 2 - Host Control
828 HCOM, 8, // 3 - Host Command
829 TXSA, 8, // 4 - Transmit Slave Address
830 DAT0, 8, // 5 - Host Data 0
831 DAT1, 8, // 6 - Host Data 1
832 HBDR, 8, // 7 - Host Block Data
833 PECR, 8, // 8 - Packer Error Check
834 RXSA, 8, // 9 - Receive Slave Address
835 SDAT, 16, // A - Slave Data
837 Or(HCON,0x02,HCON) // Yes. Send Kill command.
838 Or(HSTS,0xFF,HSTS) // Clear all status.