3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #ifndef _EFI_PCI_BUS_H_
18 #define _EFI_PCI_BUS_H_
22 #include <Protocol/LoadedImage.h>
23 #include <Protocol/PciHostBridgeResourceAllocation.h>
24 #include <Protocol/PciIo.h>
25 #include <Protocol/LoadFile2.h>
26 #include <Protocol/PciRootBridgeIo.h>
27 #include <Protocol/PciHotPlugRequest.h>
28 #include <Protocol/DevicePath.h>
29 #include <Protocol/PciPlatform.h>
30 #include <Protocol/PciHotPlugInit.h>
31 #include <Protocol/Decompress.h>
32 #include <Protocol/BusSpecificDriverOverride.h>
33 #include <Protocol/IncompatiblePciDeviceSupport.h>
34 #include <Protocol/PciOverride.h>
35 #include <Protocol/PciEnumerationComplete.h>
37 #include <Library/DebugLib.h>
38 #include <Library/UefiDriverEntryPoint.h>
39 #include <Library/BaseLib.h>
40 #include <Library/UefiLib.h>
41 #include <Library/BaseMemoryLib.h>
42 #include <Library/ReportStatusCodeLib.h>
43 #include <Library/MemoryAllocationLib.h>
44 #include <Library/UefiBootServicesTableLib.h>
45 #include <Library/DevicePathLib.h>
46 #include <Library/PcdLib.h>
47 #include <Library/PeCoffLib.h>
49 #include <IndustryStandard/Pci.h>
50 #include <IndustryStandard/PeImage.h>
51 #include <IndustryStandard/Acpi.h>
53 typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE
;
54 typedef struct _PCI_BAR PCI_BAR
;
56 #define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
57 #define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)
59 #define EFI_PCI_IOV_POLICY_ARI 0x0001
60 #define EFI_PCI_IOV_POLICY_SRIOV 0x0002
61 #define EFI_PCI_IOV_POLICY_MRIOV 0x0004
64 PciBarTypeUnknown
= 0,
77 #define VGABASE1 0x3B0
78 #define VGALIMIT1 0x3BB
80 #define VGABASE2 0x3C0
81 #define VGALIMIT2 0x3DF
84 #define ISALIMIT 0x3FF
100 // defined in PCI Card Specification, 8.0
102 #define PCI_CARD_MEMORY_BASE_0 0x1C
103 #define PCI_CARD_MEMORY_LIMIT_0 0x20
104 #define PCI_CARD_MEMORY_BASE_1 0x24
105 #define PCI_CARD_MEMORY_LIMIT_1 0x28
106 #define PCI_CARD_IO_BASE_0_LOWER 0x2C
107 #define PCI_CARD_IO_BASE_0_UPPER 0x2E
108 #define PCI_CARD_IO_LIMIT_0_LOWER 0x30
109 #define PCI_CARD_IO_LIMIT_0_UPPER 0x32
110 #define PCI_CARD_IO_BASE_1_LOWER 0x34
111 #define PCI_CARD_IO_BASE_1_UPPER 0x36
112 #define PCI_CARD_IO_LIMIT_1_LOWER 0x38
113 #define PCI_CARD_IO_LIMIT_1_UPPER 0x3A
114 #define PCI_CARD_BRIDGE_CONTROL 0x3E
116 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
117 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
121 #define PPB_IO_RANGE 2
122 #define PPB_MEM32_RANGE 3
123 #define PPB_PMEM32_RANGE 4
124 #define PPB_PMEM64_RANGE 5
125 #define PPB_MEM64_RANGE 0xFF
133 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001
134 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002
135 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004
136 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008
137 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
138 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020
139 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040
141 #define PCI_MAX_HOST_BRIDGE_NUM 0x0010
144 // Define option for attribute
146 #define EFI_SET_SUPPORTS 0
147 #define EFI_SET_ATTRIBUTES 1
149 #define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')
151 struct _PCI_IO_DEVICE
{
154 EFI_PCI_IO_PROTOCOL PciIo
;
157 EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride
;
158 EFI_DEVICE_PATH_PROTOCOL
*DevicePath
;
159 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*PciRootBridgeIo
;
160 EFI_LOAD_FILE2_PROTOCOL LoadFile2
;
163 // PCI configuration space header type
168 // Bus number, Device number, Function number
172 UINT8 FunctionNumber
;
175 // BAR for this PCI Device
177 PCI_BAR PciBar
[PCI_MAX_BAR
];
180 // The bridge device this pci device is subject to
182 PCI_IO_DEVICE
*Parent
;
185 // A linked list for children Pci Device if it is bridge device
187 LIST_ENTRY ChildList
;
190 // TRUE if the PCI bus driver creates the handle for this PCI device
195 // TRUE if the PCI bus driver successfully allocates the resource required by
201 // The attribute this PCI device currently set
206 // The attributes this PCI device actually supports
211 // The resource decode the bridge supports
216 // TRUE if the ROM image is from the PCI Option ROM BAR
221 // The OptionRom Size
226 // The OptionRom Size
231 // TRUE if all OpROM (in device or in platform specific position) have been processed
233 BOOLEAN AllOpRomProcessed
;
236 // TRUE if there is any EFI driver in the OptionRom
241 // A list tracking reserved resource on a bridge device
243 LIST_ENTRY ReservedResourceList
;
246 // A list tracking image handle of platform specific overriding driver
248 LIST_ENTRY OptionRomDriverList
;
250 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*ResourcePaddingDescriptors
;
251 EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes
;
258 UINT8 PciExpressCapabilityOffset
;
259 UINT32 AriCapabilityOffset
;
260 UINT32 SrIovCapabilityOffset
;
261 UINT32 MrIovCapabilityOffset
;
262 PCI_BAR VfPciBar
[PCI_MAX_BAR
];
263 UINT32 SystemPageSize
;
265 UINT16 ReservedBusNum
;
268 // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
269 // but some chipsets support non-standard I/O window alignments less than 4K.
270 // This field is used to support this case.
272 UINT16 BridgeIoAlignment
;
275 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
276 CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
278 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
279 CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
281 #define PCI_IO_DEVICE_FROM_LINK(a) \
282 CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
284 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
285 CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
292 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
*gEfiIncompatiblePciDeviceSupport
;
293 extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding
;
294 extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName
;
295 extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2
;
296 extern BOOLEAN gFullEnumeration
;
297 extern UINTN gPciHostBridgeNumber
;
298 extern EFI_HANDLE gPciHostBrigeHandles
[PCI_MAX_HOST_BRIDGE_NUM
];
299 extern UINT64 gAllOne
;
300 extern UINT64 gAllZero
;
301 extern EFI_PCI_PLATFORM_PROTOCOL
*gPciPlatformProtocol
;
302 extern EFI_PCI_OVERRIDE_PROTOCOL
*gPciOverrideProtocol
;
303 extern BOOLEAN mReserveIsaAliases
;
304 extern BOOLEAN mReserveVgaAliases
;
307 Macro that checks whether device is a GFX device.
309 @param _p Specified device.
311 @retval TRUE Device is a GFX device.
312 @retval FALSE Device is not a GFX device.
315 #define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
318 Test to see if this driver supports ControllerHandle. Any ControllerHandle
319 than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
321 @param This Protocol instance pointer.
322 @param Controller Handle of device to test.
323 @param RemainingDevicePath Optional parameter use to pick a specific child
326 @retval EFI_SUCCESS This driver supports this device.
327 @retval EFI_ALREADY_STARTED This driver is already running on this device.
328 @retval other This driver does not support this device.
333 PciBusDriverBindingSupported (
334 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
335 IN EFI_HANDLE Controller
,
336 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
340 Start this driver on ControllerHandle and enumerate Pci bus and start
341 all device under PCI bus.
343 @param This Protocol instance pointer.
344 @param Controller Handle of device to bind driver to.
345 @param RemainingDevicePath Optional parameter use to pick a specific child
348 @retval EFI_SUCCESS This driver is added to ControllerHandle.
349 @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.
350 @retval other This driver does not support this device.
355 PciBusDriverBindingStart (
356 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
357 IN EFI_HANDLE Controller
,
358 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
362 Stop this driver on ControllerHandle. Support stopping any child handles
363 created by this driver.
365 @param This Protocol instance pointer.
366 @param Controller Handle of device to stop driver on.
367 @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of
368 children is zero stop the entire bus driver.
369 @param ChildHandleBuffer List of Child Handles to Stop.
371 @retval EFI_SUCCESS This driver is removed ControllerHandle.
372 @retval other This driver was not removed from this device.
377 PciBusDriverBindingStop (
378 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
379 IN EFI_HANDLE Controller
,
380 IN UINTN NumberOfChildren
,
381 IN EFI_HANDLE
*ChildHandleBuffer