3 Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Do platform specific PEI stage initializations.
26 #include "PlatformEarlyInit.h"
29 #pragma GCC push_options
30 #pragma GCC optimize ("O0")
32 #pragma optimize ("", off)
37 static EFI_PEI_STALL_PPI mStallPpi
= {
42 static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi
= {
43 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
49 // The reserved SMBus addresses are defined in PlatformDxe.h file.
51 static UINT8 mSmbusRsvdAddresses
[] = PLATFORM_SMBUS_RSVD_ADDRESSES
;
52 static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi
= {
55 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES
,
59 static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi
= {
60 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
61 &gPeiSmbusPolicyPpiGuid
,
64 static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi
= {
69 static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi
= {
70 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
71 &gPeiSpeakerInterfacePpiGuid
,
75 static EFI_PEI_RESET_PPI mResetPpi
= { IchReset
};
78 static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi
= {
79 (EFI_PEI_FIND_FV_FINDFV
)FindFv
82 static EFI_PEI_PPI_DESCRIPTOR mPpiList
[] = {
84 EFI_PEI_PPI_DESCRIPTOR_PPI
,
85 &gEfiPeiMasterBootModePpiGuid
,
89 EFI_PEI_PPI_DESCRIPTOR_PPI
,
94 (EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
),
100 static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList
[] = {
102 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK
,
103 &gEfiEndOfPeiSignalPpiGuid
,
104 (EFI_PEIM_NOTIFY_ENTRY_POINT
)EndOfPeiPpiNotifyCallback
107 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
),
108 &gEfiPeiMemoryDiscoveredPpiGuid
,
109 (EFI_PEIM_NOTIFY_ENTRY_POINT
)MemoryDiscoveredPpiNotifyCallback
117 Parse the status registers for figuring out the wake-up event and save it into
118 an GUID HOB which will be referenced later. However, modification is required
119 to meet the chipset register definition and the practical hardware design. Thus,
120 this is just an example.
123 @param PeiServices pointer to the PEI Service Table
124 @param EFI_SUCCESS Always return Success
132 GetWakeupEventAndSaveToHob (
133 IN CONST EFI_PEI_SERVICES
**PeiServices
141 // Read the ACPI registers
143 Pm1Sts
= IoRead16 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_PM1_STS
);
144 Gpe0Sts
= IoRead32 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_GPE0a_STS
);
147 // Figure out the wake-up event
149 if ((Pm1Sts
& B_PCH_ACPI_PM1_STS_PWRBTN
) != 0) {
150 WakeEventData
= SMBIOS_WAKEUP_TYPE_POWER_SWITCH
;
151 } else if (((Pm1Sts
& B_PCH_ACPI_PM1_STS_WAK
) != 0)) {
152 WakeEventData
= SMBIOS_WAKEUP_TYPE_PCI_PME
;
153 } else if (Gpe0Sts
!= 0) {
154 WakeEventData
= SMBIOS_WAKEUP_TYPE_OTHERS
;
156 WakeEventData
= SMBIOS_WAKEUP_TYPE_UNKNOWN
;
159 DEBUG ((EFI_D_ERROR
, "ACPI Wake Status Register: %04x\n", Pm1Sts
));
160 DEBUG ((EFI_D_ERROR
, "ACPI Wake Event Data: %02x\n", WakeEventData
));
167 IN CONST EFI_PEI_SERVICES
**PeiServices
,
168 IN SYSTEM_CONFIGURATION
*SystemConfiguration
173 EFI_PEI_READ_ONLY_VARIABLE2_PPI
*Variable
;
175 VariableSize
= sizeof (SYSTEM_CONFIGURATION
);
176 ZeroMem (SystemConfiguration
, sizeof (SYSTEM_CONFIGURATION
));
178 Status
= (*PeiServices
)->LocatePpi (
180 &gEfiPeiReadOnlyVariable2PpiGuid
,
185 ASSERT_EFI_ERROR (Status
);
188 // Use normal setup default from NVRAM variable,
189 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
191 VariableSize
= sizeof(SYSTEM_CONFIGURATION
);
192 Status
= Variable
->GetVariable (
195 &gEfiSetupVariableGuid
,
200 if (EFI_ERROR (Status
) || VariableSize
!= sizeof(SYSTEM_CONFIGURATION
)) {
201 //The setup variable is corrupted
202 VariableSize
= sizeof(SYSTEM_CONFIGURATION
);
203 Status
= Variable
->GetVariable(
206 &gEfiSetupVariableGuid
,
211 ASSERT_EFI_ERROR (Status
);
218 IN CONST EFI_PEI_SERVICES
**PeiServices
,
219 IN SYSTEM_CONFIGURATION
*SystemConfiguration
223 EFI_PEI_PPI_DESCRIPTOR
*mVlvPolicyPpiDesc
;
224 VLV_POLICY_PPI
*mVlvPolicyPpi
;
226 Status
= (*PeiServices
)->AllocatePool(
228 sizeof (EFI_PEI_PPI_DESCRIPTOR
),
229 (void **)&mVlvPolicyPpiDesc
231 ASSERT_EFI_ERROR (Status
);
233 Status
= (*PeiServices
)->AllocatePool(
235 sizeof (VLV_POLICY_PPI
),
236 (void **)&mVlvPolicyPpi
238 ASSERT_EFI_ERROR (Status
);
243 (*PeiServices
)->SetMem ((VOID
*)mVlvPolicyPpi
, sizeof (VLV_POLICY_PPI
), 0);
244 mVlvPolicyPpiDesc
->Flags
= EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
;
245 mVlvPolicyPpiDesc
->Guid
= &gVlvPolicyPpiGuid
;
246 mVlvPolicyPpiDesc
->Ppi
= mVlvPolicyPpi
;
247 mVlvPolicyPpi
->GtConfig
.PrimaryDisplay
= SystemConfiguration
->PrimaryVideoAdaptor
;
248 mVlvPolicyPpi
->GtConfig
.IgdDvmt50PreAlloc
= SystemConfiguration
->IgdDvmt50PreAlloc
;
249 mVlvPolicyPpi
->GtConfig
.ApertureSize
= SystemConfiguration
->IgdApertureSize
;
250 mVlvPolicyPpi
->GtConfig
.GttSize
= SystemConfiguration
->GTTSize
;
251 if (SystemConfiguration
->PrimaryVideoAdaptor
!= 2) {
252 mVlvPolicyPpi
->GtConfig
.InternalGraphics
= SystemConfiguration
->Igd
;
254 mVlvPolicyPpi
->GtConfig
.InternalGraphics
= 0;
258 mVlvPolicyPpi
->GtConfig
.IgdTurboEn
= 1;
261 mVlvPolicyPpi
->PlatformData
.FastBoot
= SystemConfiguration
->FastBoot
;
262 mVlvPolicyPpi
->PlatformData
.DynSR
= 1;
263 DEBUG ((EFI_D_ERROR
, "Setup Option ISPEn: 0x%x\n", SystemConfiguration
->ISPEn
));
264 mVlvPolicyPpi
->ISPEn
= SystemConfiguration
->ISPEn
;
265 DEBUG ((EFI_D_ERROR
, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration
->ISPDevSel
));
266 mVlvPolicyPpi
->ISPPciDevConfig
= SystemConfiguration
->ISPDevSel
;
267 if (SystemConfiguration
->ISPEn
== 0) {
268 mVlvPolicyPpi
->ISPPciDevConfig
= 0;
269 DEBUG ((EFI_D_ERROR
, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi
->ISPPciDevConfig
));
271 Status
= (*PeiServices
)->InstallPpi(
275 ASSERT_EFI_ERROR (Status
);
283 IN SYSTEM_CONFIGURATION
*SystemConfiguration
287 DEBUG ((EFI_D_ERROR
, "ConfigureSoCGpio------------start\n"));
288 if (SystemConfiguration
->eMMCBootMode
== 1) {// Auto detection mode
289 DEBUG ((EFI_D_ERROR
, "Auto detection mode------------start\n"));
294 switch (PchStepping()) {
295 case PchA0
: // SOC A0 and A1
297 DEBUG ((EFI_D_ERROR
, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
298 SystemConfiguration
->LpsseMMCEnabled
= 1;
299 SystemConfiguration
->LpsseMMC45Enabled
= 0;
301 case PchB0
: // SOC B0 and later
303 DEBUG ((EFI_D_ERROR
, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
304 SystemConfiguration
->LpsseMMCEnabled
= 0;
305 SystemConfiguration
->LpsseMMC45Enabled
= 1;
308 } else if (SystemConfiguration
->eMMCBootMode
== 2) { // eMMC 4.41
309 DEBUG ((EFI_D_ERROR
, "Force to eMMC 4.41 GPIO Configuration\n"));
310 SystemConfiguration
->LpsseMMCEnabled
= 1;
311 SystemConfiguration
->LpsseMMC45Enabled
= 0;
312 } else if (SystemConfiguration
->eMMCBootMode
== 3) { // eMMC 4.5
313 DEBUG ((EFI_D_ERROR
, "Force to eMMC 4.5 GPIO Configuration\n"));
314 SystemConfiguration
->LpsseMMCEnabled
= 0;
315 SystemConfiguration
->LpsseMMC45Enabled
= 1;
317 } else { // Disable eMMC controllers
318 DEBUG ((EFI_D_ERROR
, "Disable eMMC GPIO controllers\n"));
319 SystemConfiguration
->LpsseMMCEnabled
= 0;
320 SystemConfiguration
->LpsseMMC45Enabled
= 0;
325 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
326 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
327 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
328 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
329 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
330 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
331 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
332 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
333 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
334 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
335 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
337 if (SystemConfiguration
->LpsseMMCEnabled
== 1) {
338 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03E0, 0x2003ED01); //EMMC 4.41
339 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0390, 0x2003EC81);
340 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03D0, 0x2003EC81);
341 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0400, 0x2003EC81);
342 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03B0, 0x2003EC81);
343 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0360, 0x2003EC81);
344 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0380, 0x2003EC81);
345 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03C0, 0x2003EC81);
346 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0370, 0x2003EC81);
347 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03F0, 0x2003EC81);
348 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0330, 0x2003ED01);
353 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
354 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
355 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
356 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
357 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
358 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
359 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
360 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
361 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
362 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
363 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
365 if (SystemConfiguration
->LpsseMMC45Enabled
== 1) {
366 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03E0, 0x2003ED03); // EMMC 4.5
367 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0390, 0x2003EC83);
368 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03D0, 0x2003EC83);
369 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0400, 0x2003EC83);
370 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03B0, 0x2003EC83);
371 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0360, 0x2003EC83);
372 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0380, 0x2003EC83);
373 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03C0, 0x2003EC83);
374 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0370, 0x2003EC83);
375 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03F0, 0x2003EC83);
376 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0330, 0x2003ED03);
381 // Change GPIOC_0 setting to allow MMIO access under Android.
383 IoWrite32 (GPIO_BASE_ADDRESS
+ R_PCH_GPIO_SC_USE_SEL
,
384 (IoRead32(GPIO_BASE_ADDRESS
+ R_PCH_GPIO_SC_USE_SEL
) & (UINT32
)~BIT0
));
385 DEBUG ((EFI_D_ERROR
, "ConfigureSoCGpio------------end\n"));
391 IN CONST EFI_PEI_SERVICES
**PeiServices
,
392 IN SYSTEM_CONFIGURATION
*SystemConfiguration
395 if (SystemConfiguration
->MeasuredBootEnable
) {
396 PcdSetBool (PcdMeasuredBootEnable
, TRUE
);
398 PcdSetBool (PcdMeasuredBootEnable
, FALSE
);
406 ConfigureLpssAndSccGpio (
407 IN SYSTEM_CONFIGURATION
*SystemConfiguration
,
408 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
411 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
412 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
413 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
414 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
416 DEBUG ((EFI_D_ERROR
, "ConfigureLpssAndSccGpio------------start\n"));
420 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
422 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
424 if (SystemConfiguration
->LpssPwm0Enabled
== 1) {
425 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00A0, 0x2003CD01);
426 } else if (SystemConfiguration
->LpssPwm0Enabled
== 0) {
427 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00A0, 0x2003CD00);
430 if (SystemConfiguration
->LpssPwm1Enabled
== 1) {
431 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00B0, 0x2003CC01);
432 } else if (SystemConfiguration
->LpssPwm1Enabled
== 0) {
433 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00B0, 0x2003CD00);
438 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
439 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
440 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
441 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
443 if (SystemConfiguration
->LpssHsuart0Enabled
== 1) {
444 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0020, 0x2003CC81); // uart1
445 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0010, 0x2003CC81);
446 if (SystemConfiguration
->LpssHsuart0FlowControlEnabled
== 0) {
447 DEBUG ((EFI_D_ERROR
, "LpssHsuart0FlowControlEnabled[0]\n"));
448 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0000, 0x2003CC80);
449 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0040, 0x2003CC80);
451 DEBUG ((EFI_D_ERROR
, "LpssHsuart0FlowControlEnabled[1]\n"));
452 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0000, 0x2003CC81);
453 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
455 } else if (SystemConfiguration
->LpssHsuart0Enabled
== 0) {
456 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0020, 0x2003CC80); // uart1
457 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0010, 0x2003CC80);
463 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
464 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
465 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
466 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
468 if (SystemConfiguration
->LpssHsuart1Enabled
== 1) {
469 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0060, 0x2003CC81);
470 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0070, 0x2003CC81);
472 if (SystemConfiguration
->LpssHsuart1FlowControlEnabled
== 0) {
473 DEBUG ((EFI_D_ERROR
, "LpssHsuart1FlowControlEnabled[0]\n"));
474 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0090, 0x2003CC80); // UART2_RTS_B
475 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0080, 0x2003CC80); // UART2_CTS_B
477 DEBUG ((EFI_D_ERROR
, "LpssHsuart1FlowControlEnabled[1]\n"));
478 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0090, 0x2003CC81); // uart2
479 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
481 } else if (SystemConfiguration
->LpssHsuart1Enabled
== 0) {
482 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0060, 0x2003CC80);
483 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0070, 0x2003CC80);
488 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
489 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
490 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
491 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
493 if (SystemConfiguration
->LpssSpiEnabled
== 1) {
494 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0110, 0x2003CC81); // SPI
495 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0100, 0x2003CD01);
496 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0130, 0x2003CC81);
497 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0120, 0x2003CC81);
498 } else if (SystemConfiguration
->LpssSpiEnabled
== 0) {
499 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0110, 0x2003cc80);
500 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0100, 0x2003cc80);
501 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0130, 0x2003cc80);
502 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0120, 0x2003cc80);
507 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
508 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
510 if (SystemConfiguration
->LpssI2C0Enabled
== 1) {
511 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0210, 0x2003C881);
512 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0200, 0x2003C881);
516 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
517 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
520 if (SystemConfiguration
->LpssI2C1Enabled
== 1) {
521 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01F0, 0x2003C881);
522 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01E0, 0x2003C881);
526 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
527 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
529 if (SystemConfiguration
->LpssI2C2Enabled
== 1) {
530 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01D0, 0x2003C881);
531 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01B0, 0x2003C881);
535 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
536 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
538 if (SystemConfiguration
->LpssI2C3Enabled
== 1) {
539 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0190, 0x2003C881);
540 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01C0, 0x2003C881);
544 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
545 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
547 if (SystemConfiguration
->LpssI2C4Enabled
== 1) {
548 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01A0, 0x2003C881);
549 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0170, 0x2003C881);
553 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
554 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
556 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
557 if (SystemConfiguration
->LpssI2C5Enabled
== 1) {
558 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0150, 0x2003C881);
559 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0140, 0x2003C881);
560 } else if(SystemConfiguration
->LpssI2C5Enabled
== 0) {
561 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0150, 0x2003C880);
562 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0140, 0x2003C880);
566 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
567 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
569 if (SystemConfiguration
->LpssI2C6Enabled
== 1) {
570 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0180, 0x2003C881);
571 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0160, 0x2003C881);
572 } else if (SystemConfiguration
->LpssI2C6Enabled
== 0) {
573 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0180, 0x2003C880);
574 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0160, 0x2003C880);
580 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
581 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
582 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
583 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
584 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
585 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
587 if (SystemConfiguration
->LpssSdioEnabled
== 1) {
588 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0320, 0x2003ED01);//SDIO
589 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0300, 0x2003EC81);
590 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0350, 0x2003EC81);
591 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02F0, 0x2003EC81);
592 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0340, 0x2003EC81);
593 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0310, 0x2003EC81);
598 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
599 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
600 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
601 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
602 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
603 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
604 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
605 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
606 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
607 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
609 if (SystemConfiguration
->LpssSdcardEnabled
== 1) {
610 if (!((PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD
&& PlatformInfo
->BoardRev
== PR11
) && (SystemConfiguration
->CfioPnpSettings
== 1))) {
611 MmioWrite32 (IO_BASE_ADDRESS
+ 0x05F0, 0x2003CD01);//SDCARD
612 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02B0, 0x2003CD01);
613 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02C0, 0x2003CC81);
614 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02E0, 0x2003CC81);
615 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0290, 0x2003CC81);
616 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02D0, 0x2003CC81);
617 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02A0, 0x2003CC81);
618 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0690, 0x2003CC81);
619 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
624 DEBUG ((EFI_D_ERROR
, "ConfigureLpssAndSccGpio------------end\n"));
630 IN SYSTEM_CONFIGURATION
*SystemConfiguration
633 DEBUG ((EFI_D_ERROR
, "ConfigureLpeGpio------------start\n"));
635 if (SystemConfiguration
->PchAzalia
== 0) {
636 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x220, (UINT32
)~(0x7), (UINT32
) (0x01));
637 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x250, (UINT32
)~(0x7), (UINT32
) (0x01));
638 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x240, (UINT32
)~(0x7), (UINT32
) (0x01));
639 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x260, (UINT32
)~(0x7), (UINT32
) (0x01));
640 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x270, (UINT32
)~(0x7), (UINT32
) (0x01));
641 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x230, (UINT32
)~(0x7), (UINT32
) (0x01));
642 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x280, (UINT32
)~(0x7), (UINT32
) (0x01));
643 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x540, (UINT32
)~(0x7), (UINT32
) (0x01));
646 DEBUG ((EFI_D_ERROR
, "ConfigureLpeGpio------------end\n"));
652 ConfigureSciSmiGpioRout (
653 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
)
657 GPI_Routing
= MmioRead32 (PMC_BASE_ADDRESS
+ R_PCH_PMC_GPI_ROUT
);
660 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
662 if(PlatformInfo
->BoardRev
== 3) {
663 GPI_Routing
= GPI_Routing
& 0xfffc3ffc;
664 GPI_Routing
= GPI_Routing
| 0x00024002;
668 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
671 GPI_Routing
= GPI_Routing
& 0x3fff3ffc;
672 GPI_Routing
= GPI_Routing
| 0x80004002;
674 MmioWrite32((PMC_BASE_ADDRESS
+ R_PCH_PMC_GPI_ROUT
), GPI_Routing
);
684 //Configure the platform clock for MIPI-CSI usage
687 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x6a0, (UINT32
)~(0x7), (UINT32
) (0x01));
692 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x570, (UINT32
)~(0x7), (UINT32
) (0x01));
697 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x5B0, (UINT32
)~(0x7), (UINT32
) (0x01));
710 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x338, (UINT32
)~(0x7), (UINT32
) (GPI
));
711 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x330, (UINT32
)~(0x187), (UINT32
) (0x101));
716 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x388, (UINT32
)~(0x7), (UINT32
) (GPI
));
717 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x380, (UINT32
)~(0x187), (UINT32
) (0x101));
722 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x368, (UINT32
)~(0x7), (UINT32
) (GPI
));
723 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x360, (UINT32
)~(0x187), (UINT32
) (0x101));
728 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x318, (UINT32
)~(0x7), (UINT32
) (GPI
));
729 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x310, (UINT32
)~(0x187), (UINT32
) (0x101));
734 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x378, (UINT32
)~(0x7), (UINT32
) (GPI
));
735 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x370, (UINT32
)~(0x187), (UINT32
) (0x101));
740 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x308, (UINT32
)~(0x7), (UINT32
) (GPI
));
741 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x300, (UINT32
)~(0x187), (UINT32
) (0x101));
746 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x398, (UINT32
)~(0x7), (UINT32
) (GPI
));
747 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x390, (UINT32
)~(0x187), (UINT32
) (0x101));
752 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x328, (UINT32
)~(0x7), (UINT32
) (GPI
));
753 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x320, (UINT32
)~(0x187), (UINT32
) (0x101));
758 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3a8, (UINT32
)~(0x7), (UINT32
) (GPI
));
759 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3a0, (UINT32
)~(0x187), (UINT32
) (0x101));
764 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x348, (UINT32
)~(0x7), (UINT32
) (GPI
));
765 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x340, (UINT32
)~(0x187), (UINT32
) (0x81));
770 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x358, (UINT32
)~(0x7), (UINT32
) (GPI
));
771 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x350, (UINT32
)~(0x187), (UINT32
) (0x101));
776 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3b8, (UINT32
)~(0x7), (UINT32
) (GPI
));
777 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3b0, (UINT32
)~(0x187), (UINT32
) (0x81));
782 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x288, (UINT32
)~(0x7), (UINT32
) (GPI
));
783 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x280, (UINT32
)~(0x187), (UINT32
) (0x101));
795 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x210, (UINT32
)~(0x0f000007), (UINT32
) (0x00));
796 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x1e0, (UINT32
)~(0x0f000007), (UINT32
) (0x00));
802 Platform specific initializations in stage1.
804 @param FfsHeader Pointer to the PEIM FFS file header.
805 @param PeiServices General purpose services available to every PEIM.
807 @retval EFI_SUCCESS Operation completed successfully.
808 @retval Otherwise Platform initialization failed.
812 PlatformEarlyInitEntry (
814 IN EFI_PEI_FILE_HANDLE FileHandle
,
815 IN CONST EFI_PEI_SERVICES
**PeiServices
819 SYSTEM_CONFIGURATION SystemConfiguration
;
820 EFI_PLATFORM_INFO_HOB
*PlatformInfo
;
821 EFI_PEI_HOB_POINTERS Hob
;
822 EFI_PLATFORM_CPU_INFO PlatformCpuInfo
;
823 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
*DescriptorBlock
;
824 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
*NewDescriptorBlock
;
832 // Make sure base and size of the SMRAM region is aligned
834 Hob
.Raw
= GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid
);
835 if (Hob
.Raw
!= NULL
) {
836 DescriptorBlock
= GET_GUID_HOB_DATA (Hob
.Raw
);
837 DEBUG ((DEBUG_INFO
, "SMM PEI SMRAM Memory Reserved HOB\n"));
838 for (Index
= 0; Index
< DescriptorBlock
->NumberOfSmmReservedRegions
; Index
++) {
839 DEBUG((DEBUG_INFO
, " SMRAM Descriptor[%02x]: Start=%016lx Size=%016lx State=%02x\n",
841 DescriptorBlock
->Descriptor
[Index
].PhysicalStart
,
842 DescriptorBlock
->Descriptor
[Index
].PhysicalSize
,
843 DescriptorBlock
->Descriptor
[Index
].RegionState
848 // Find the largest usable range of SMRAM between 1MB and 4GB
850 for (Index
= 0, MaxIndex
= 0, Size
= 0; Index
< DescriptorBlock
->NumberOfSmmReservedRegions
; Index
++) {
852 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
854 if ((DescriptorBlock
->Descriptor
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
858 // Skip any SMRAM region below 1MB
860 if (DescriptorBlock
->Descriptor
[Index
].CpuStart
< BASE_1MB
) {
864 // Skip any SMRAM region that is above 4GB or crosses the 4GB boundary
866 if ((DescriptorBlock
->Descriptor
[Index
].CpuStart
+ DescriptorBlock
->Descriptor
[Index
].PhysicalSize
) >= BASE_4GB
) {
870 // Cache the largest SMRAM region index
872 if (DescriptorBlock
->Descriptor
[Index
].PhysicalSize
>= DescriptorBlock
->Descriptor
[MaxIndex
].PhysicalSize
) {
878 // Find the extent of the contiguous SMRAM region that surrounds the largest usable SMRAM range
880 Base
= DescriptorBlock
->Descriptor
[MaxIndex
].CpuStart
;
881 Size
= DescriptorBlock
->Descriptor
[MaxIndex
].PhysicalSize
;
882 for (Index
= 0; Index
< DescriptorBlock
->NumberOfSmmReservedRegions
; Index
++) {
883 if (DescriptorBlock
->Descriptor
[Index
].CpuStart
< Base
&&
884 Base
== (DescriptorBlock
->Descriptor
[Index
].CpuStart
+ DescriptorBlock
->Descriptor
[Index
].PhysicalSize
)) {
885 Base
= DescriptorBlock
->Descriptor
[Index
].CpuStart
;
886 Size
+= DescriptorBlock
->Descriptor
[Index
].PhysicalSize
;
887 } else if ((Base
+ Size
) == DescriptorBlock
->Descriptor
[Index
].CpuStart
) {
888 Size
+= DescriptorBlock
->Descriptor
[Index
].PhysicalSize
;
893 // Round SMRAM region up to nearest power of 2 that is at least 4KB
895 NewSize
= MAX (LShiftU64 (1, HighBitSet64 (Size
- 1) + 1), SIZE_4KB
);
896 if ((Base
& ~(NewSize
- 1)) != Base
) {
898 // SMRAM region Base Address has smaller alignment than SMRAM region Size
899 // This is not compatible with SMRR settings
901 DEBUG((DEBUG_ERROR
, "ERROR: SMRAM Region Size has larger alignment than SMRAM Region Base\n"));
902 DEBUG((DEBUG_ERROR
, " SMRAM Region Base=%016lx Size=%016lx\n", Base
, NewSize
));
904 } else if (Size
!= NewSize
) {
906 // See if the size difference can be added to an adjacent descriptor that is already allocated
908 for (Index
= 0; Index
< DescriptorBlock
->NumberOfSmmReservedRegions
; Index
++) {
909 if ((DescriptorBlock
->Descriptor
[Index
].CpuStart
+ DescriptorBlock
->Descriptor
[Index
].PhysicalSize
) == (Base
+ Size
)) {
910 if (((DescriptorBlock
->Descriptor
[Index
].RegionState
) & EFI_ALLOCATED
) != 0) {
911 DescriptorBlock
->Descriptor
[Index
].PhysicalSize
+= (NewSize
- Size
);
918 if (Size
!= NewSize
) {
920 // Add an allocated descriptor to the SMM PEI SMRAM Memory Reserved HOB to accomodate the larger size.
922 Index
= DescriptorBlock
->NumberOfSmmReservedRegions
;
923 NewDescriptorBlock
= (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
*)BuildGuidHob (
924 &gEfiSmmPeiSmramMemoryReserveGuid
,
925 sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
) + ((Index
+ 1) * sizeof (EFI_SMRAM_DESCRIPTOR
))
927 ASSERT (NewDescriptorBlock
!= NULL
);
930 // Copy old EFI_SMRAM_HOB_DESCRIPTOR_BLOCK to new allocated region
935 sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK
) + (Index
* sizeof (EFI_SMRAM_DESCRIPTOR
))
939 // Make sure last descriptor in NewDescriptorBlock contains last descriptor from DescriptorBlock
942 &NewDescriptorBlock
->Descriptor
[Index
],
943 &NewDescriptorBlock
->Descriptor
[Index
- 1],
944 sizeof (EFI_SMRAM_DESCRIPTOR
)
948 // Fill next to last descriptor with an allocated descriptor that aligns the total size of SMRAM
950 NewDescriptorBlock
->Descriptor
[Index
- 1].CpuStart
= Base
+ Size
;
951 NewDescriptorBlock
->Descriptor
[Index
- 1].PhysicalStart
= Base
+ Size
;
952 NewDescriptorBlock
->Descriptor
[Index
- 1].PhysicalSize
= NewSize
- Size
;
953 NewDescriptorBlock
->Descriptor
[Index
- 1].RegionState
= DescriptorBlock
->Descriptor
[MaxIndex
].RegionState
| EFI_ALLOCATED
;
954 NewDescriptorBlock
->NumberOfSmmReservedRegions
++;
957 // Invalidate the original gEfiSmmPeiSmramMemoryReserveGuid HOB
959 ZeroMem (&Hob
.Guid
->Name
, sizeof (&Hob
.Guid
->Name
));
962 Hob
.Raw
= GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid
);
963 DescriptorBlock
= GET_GUID_HOB_DATA (Hob
.Raw
);
964 DEBUG ((DEBUG_INFO
, "SMM PEI SMRAM Memory Reserved HOB - Updated\n"));
965 for (Index
= 0; Index
< DescriptorBlock
->NumberOfSmmReservedRegions
; Index
++) {
966 DEBUG((DEBUG_INFO
, " SMRAM Descriptor[%02x]: Start=%016lx Size=%016lx State=%02x\n",
968 DescriptorBlock
->Descriptor
[Index
].PhysicalStart
,
969 DescriptorBlock
->Descriptor
[Index
].PhysicalSize
,
970 DescriptorBlock
->Descriptor
[Index
].RegionState
977 // Initialize SmbusPolicy PPI
979 Status
= (*PeiServices
)->InstallPpi(PeiServices
, &mInstallSmbusPolicyPpi
);
980 ASSERT_EFI_ERROR (Status
);
983 // Initialize Stall PPIs
985 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mInstallStallPpi
);
986 ASSERT_EFI_ERROR (Status
);
989 // Initialize platform PPIs
991 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mInstallSpeakerInterfacePpi
);
992 ASSERT_EFI_ERROR (Status
);
995 // Variable initialization
997 ZeroMem(&PlatformCpuInfo
, sizeof(EFI_PLATFORM_CPU_INFO
));
1000 // Set the some PCI and chipset range as UC
1001 // And align to 1M at leaset
1003 Hob
.Raw
= GetFirstGuidHob (&gEfiPlatformInfoGuid
);
1004 ASSERT (Hob
.Raw
!= NULL
);
1005 PlatformInfo
= GET_GUID_HOB_DATA(Hob
.Raw
);
1008 // Initialize PlatformInfo HOB
1010 MultiPlatformInfoInit(PeiServices
, PlatformInfo
);
1013 // Do basic MCH init
1015 MchInit (PeiServices
);
1018 // Set the new boot mode
1020 Status
= UpdateBootMode (PeiServices
, PlatformInfo
);
1021 ASSERT_EFI_ERROR (Status
);
1023 SetPlatformBootMode (PeiServices
, PlatformInfo
);
1026 // Get setup variable. This can only be done after BootMode is updated
1028 GetSetupVariable (PeiServices
, &SystemConfiguration
);
1030 CheckOsSelection(PeiServices
, &SystemConfiguration
);
1033 // Update PlatformInfo HOB according to setup variable
1035 PlatformInfoUpdate(PeiServices
, PlatformInfo
, &SystemConfiguration
);
1037 InitializePlatform (PeiServices
, PlatformInfo
, &SystemConfiguration
);
1040 // Initialize VlvPolicy PPI
1042 Status
= VlvPolicyInit (PeiServices
, &SystemConfiguration
);
1043 ASSERT_EFI_ERROR (Status
);
1046 // Soc specific GPIO setting
1048 ConfigureSoCGpio(&SystemConfiguration
);
1051 // Baylake Board specific.
1053 if (PlatformInfo
->BoardId
== BOARD_ID_BL_RVP
||
1054 PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD
||
1055 PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD8
||
1056 PlatformInfo
->BoardId
== BOARD_ID_BL_RVP_DDR3L
||
1057 PlatformInfo
->BoardId
== BOARD_ID_BL_STHI
||
1058 PlatformInfo
->BoardId
== BOARD_ID_BB_RVP
||
1059 PlatformInfo
->BoardId
== BOARD_ID_BS_RVP
||
1060 PlatformInfo
->BoardId
== BOARD_ID_MINNOW2
||
1061 PlatformInfo
->BoardId
== BOARD_ID_MINNOW2_TURBOT
||
1062 PlatformInfo
->BoardId
== BOARD_ID_CVH
) {
1063 ConfigureLpssAndSccGpio(&SystemConfiguration
, PlatformInfo
);
1070 // Alpine Valley and Bayley Bay board specific
1072 ConfigureLpeGpio(&SystemConfiguration
);
1075 // Bayley Bay Board specific.
1077 ConfigureSciSmiGpioRout(PlatformInfo
);
1078 if (SystemConfiguration
.LpssI2C3Enabled
== 1) {
1084 // Do basic CPU init
1086 Status
= PlatformCpuInit (PeiServices
, &SystemConfiguration
, &PlatformCpuInfo
);
1089 // Perform basic SSA related platform initialization
1091 PlatformSsaInit (&SystemConfiguration
,PeiServices
);
1095 // Do basic PCH init
1097 Status
= PlatformPchInit (&SystemConfiguration
, PeiServices
, PlatformInfo
->PlatformType
);
1098 ASSERT_EFI_ERROR (Status
);
1101 // Initialize platform PPIs
1103 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mPpiList
[0]);
1104 ASSERT_EFI_ERROR (Status
);
1106 if (PlatformInfo
->BoardId
!= BOARD_ID_CVH
) {
1107 InstallPlatformClocksNotify (PeiServices
);
1108 InstallPlatformSysCtrlGPIONotify(PeiServices
);
1112 // Initialize platform PPIs
1114 Status
= (*PeiServices
)->NotifyPpi(PeiServices
, &mNotifyList
[0]);
1115 ASSERT_EFI_ERROR (Status
);
1118 // Initialize Measured Boot
1120 Status
= MeasuredBootInit (PeiServices
, &SystemConfiguration
);
1121 ASSERT_EFI_ERROR (Status
);
1128 Return the mainblockcompact Fv.
1130 @param FvNumber Our enumeration of the firmware volumes we care about.
1132 @param FvAddress Base Address of the memory containing the firmware volume
1135 @retval EFI_NOT_FOUND
1141 IN EFI_PEI_FIND_FV_PPI
*This
,
1142 IN CONST EFI_PEI_SERVICES
**PeiServices
,
1143 IN OUT UINT8
*FvNumber
,
1144 OUT EFI_FIRMWARE_VOLUME_HEADER
**FVAddress
1148 // At present, we only have one Fv to search
1150 if (*FvNumber
== 0) {
1152 *FVAddress
= (EFI_FIRMWARE_VOLUME_HEADER
*)(UINTN
)FixedPcdGet32 (PcdFlashFvMainBase
);
1155 else if (*FvNumber
== 1) {
1157 *FVAddress
= (EFI_FIRMWARE_VOLUME_HEADER
*)(UINTN
)FixedPcdGet32 (PcdFlashFvRecovery2Base
);
1160 else { // Not the one Fv we care about
1161 return EFI_NOT_FOUND
;
1168 IN CONST EFI_PEI_SERVICES
**PeiServices
1171 // MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
1190 // If we get here we need to mark it as a failure.
1192 return EFI_UNSUPPORTED
;
1197 #pragma GCC pop_options
1199 #pragma optimize ("", on)