3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Do platform specific PEI stage initializations.
26 #include "PlatformEarlyInit.h"
29 #pragma GCC push_options
30 #pragma GCC optimize ("O0")
32 #pragma optimize ("", off)
37 static EFI_PEI_STALL_PPI mStallPpi
= {
42 static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi
= {
43 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
49 // The reserved SMBus addresses are defined in PlatformDxe.h file.
51 static UINT8 mSmbusRsvdAddresses
[] = PLATFORM_SMBUS_RSVD_ADDRESSES
;
52 static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi
= {
55 PLATFORM_NUM_SMBUS_RSVD_ADDRESSES
,
59 static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi
= {
60 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
61 &gPeiSmbusPolicyPpiGuid
,
64 static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi
= {
69 static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi
= {
70 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
71 &gPeiSpeakerInterfacePpiGuid
,
75 static EFI_PEI_RESET_PPI mResetPpi
= { IchReset
};
78 static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi
= {
79 (EFI_PEI_FIND_FV_FINDFV
)FindFv
82 static EFI_PEI_PPI_DESCRIPTOR mPpiList
[] = {
84 EFI_PEI_PPI_DESCRIPTOR_PPI
,
85 &gEfiPeiMasterBootModePpiGuid
,
89 EFI_PEI_PPI_DESCRIPTOR_PPI
,
94 (EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
),
100 static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList
[] = {
102 EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK
,
103 &gEfiEndOfPeiSignalPpiGuid
,
104 (EFI_PEIM_NOTIFY_ENTRY_POINT
)EndOfPeiPpiNotifyCallback
107 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
),
108 &gEfiPeiMemoryDiscoveredPpiGuid
,
109 (EFI_PEIM_NOTIFY_ENTRY_POINT
)MemoryDiscoveredPpiNotifyCallback
117 Parse the status registers for figuring out the wake-up event and save it into
118 an GUID HOB which will be referenced later. However, modification is required
119 to meet the chipset register definition and the practical hardware design. Thus,
120 this is just an example.
123 @param PeiServices pointer to the PEI Service Table
124 @param EFI_SUCCESS Always return Success
132 GetWakeupEventAndSaveToHob (
133 IN CONST EFI_PEI_SERVICES
**PeiServices
141 // Read the ACPI registers
143 Pm1Sts
= IoRead16 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_PM1_STS
);
144 Gpe0Sts
= IoRead32 (ACPI_BASE_ADDRESS
+ R_PCH_ACPI_GPE0a_STS
);
147 // Figure out the wake-up event
149 if ((Pm1Sts
& B_PCH_ACPI_PM1_STS_PWRBTN
) != 0) {
150 WakeEventData
= SMBIOS_WAKEUP_TYPE_POWER_SWITCH
;
151 } else if (((Pm1Sts
& B_PCH_ACPI_PM1_STS_WAK
) != 0)) {
152 WakeEventData
= SMBIOS_WAKEUP_TYPE_PCI_PME
;
153 } else if (Gpe0Sts
!= 0) {
154 WakeEventData
= SMBIOS_WAKEUP_TYPE_OTHERS
;
156 WakeEventData
= SMBIOS_WAKEUP_TYPE_UNKNOWN
;
159 DEBUG ((EFI_D_ERROR
, "ACPI Wake Status Register: %04x\n", Pm1Sts
));
166 IN CONST EFI_PEI_SERVICES
**PeiServices
,
167 IN SYSTEM_CONFIGURATION
*SystemConfiguration
172 EFI_PEI_READ_ONLY_VARIABLE2_PPI
*Variable
;
174 VariableSize
= sizeof (SYSTEM_CONFIGURATION
);
175 ZeroMem (SystemConfiguration
, sizeof (SYSTEM_CONFIGURATION
));
177 Status
= (*PeiServices
)->LocatePpi (
179 &gEfiPeiReadOnlyVariable2PpiGuid
,
184 ASSERT_EFI_ERROR (Status
);
187 // Use normal setup default from NVRAM variable,
188 // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
190 VariableSize
= sizeof(SYSTEM_CONFIGURATION
);
191 Status
= Variable
->GetVariable (
194 &gEfiSetupVariableGuid
,
199 ASSERT_EFI_ERROR(Status
);
205 IN CONST EFI_PEI_SERVICES
**PeiServices
,
206 IN SYSTEM_CONFIGURATION
*SystemConfiguration
210 EFI_PEI_PPI_DESCRIPTOR
*mVlvPolicyPpiDesc
;
211 VLV_POLICY_PPI
*mVlvPolicyPpi
;
213 Status
= (*PeiServices
)->AllocatePool(
215 sizeof (EFI_PEI_PPI_DESCRIPTOR
),
216 (void **)&mVlvPolicyPpiDesc
218 ASSERT_EFI_ERROR (Status
);
220 Status
= (*PeiServices
)->AllocatePool(
222 sizeof (VLV_POLICY_PPI
),
223 (void **)&mVlvPolicyPpi
225 ASSERT_EFI_ERROR (Status
);
230 (*PeiServices
)->SetMem ((VOID
*)mVlvPolicyPpi
, sizeof (VLV_POLICY_PPI
), 0);
231 mVlvPolicyPpiDesc
->Flags
= EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
;
232 mVlvPolicyPpiDesc
->Guid
= &gVlvPolicyPpiGuid
;
233 mVlvPolicyPpiDesc
->Ppi
= mVlvPolicyPpi
;
234 mVlvPolicyPpi
->GtConfig
.PrimaryDisplay
= SystemConfiguration
->PrimaryVideoAdaptor
;
235 mVlvPolicyPpi
->GtConfig
.IgdDvmt50PreAlloc
= SystemConfiguration
->IgdDvmt50PreAlloc
;
236 mVlvPolicyPpi
->GtConfig
.ApertureSize
= SystemConfiguration
->IgdApertureSize
;
237 mVlvPolicyPpi
->GtConfig
.GttSize
= SystemConfiguration
->GTTSize
;
238 if (SystemConfiguration
->PrimaryVideoAdaptor
!= 2) {
239 mVlvPolicyPpi
->GtConfig
.InternalGraphics
= SystemConfiguration
->Igd
;
241 mVlvPolicyPpi
->GtConfig
.InternalGraphics
= 0;
245 mVlvPolicyPpi
->GtConfig
.IgdTurboEn
= 1;
248 mVlvPolicyPpi
->PlatformData
.FastBoot
= SystemConfiguration
->FastBoot
;
249 mVlvPolicyPpi
->PlatformData
.DynSR
= 1;
250 DEBUG ((EFI_D_ERROR
, "Setup Option ISPEn: 0x%x\n", SystemConfiguration
->ISPEn
));
251 mVlvPolicyPpi
->ISPEn
= SystemConfiguration
->ISPEn
;
252 DEBUG ((EFI_D_ERROR
, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration
->ISPDevSel
));
253 mVlvPolicyPpi
->ISPPciDevConfig
= SystemConfiguration
->ISPDevSel
;
254 if (SystemConfiguration
->ISPEn
== 0) {
255 mVlvPolicyPpi
->ISPPciDevConfig
= 0;
256 DEBUG ((EFI_D_ERROR
, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi
->ISPPciDevConfig
));
258 Status
= (*PeiServices
)->InstallPpi(
262 ASSERT_EFI_ERROR (Status
);
270 IN SYSTEM_CONFIGURATION
*SystemConfiguration
274 DEBUG ((EFI_D_ERROR
, "ConfigureSoCGpio------------start\n"));
275 if (SystemConfiguration
->eMMCBootMode
== 1) {// Auto detection mode
276 DEBUG ((EFI_D_ERROR
, "Auto detection mode------------start\n"));
281 switch (PchStepping()) {
282 case PchA0
: // SOC A0 and A1
284 DEBUG ((EFI_D_ERROR
, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
285 SystemConfiguration
->LpsseMMCEnabled
= 1;
286 SystemConfiguration
->LpsseMMC45Enabled
= 0;
288 case PchB0
: // SOC B0 and later
290 DEBUG ((EFI_D_ERROR
, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
291 SystemConfiguration
->LpsseMMCEnabled
= 0;
292 SystemConfiguration
->LpsseMMC45Enabled
= 1;
295 } else if (SystemConfiguration
->eMMCBootMode
== 2) { // eMMC 4.41
296 DEBUG ((EFI_D_ERROR
, "Force to eMMC 4.41 GPIO Configuration\n"));
297 SystemConfiguration
->LpsseMMCEnabled
= 1;
298 SystemConfiguration
->LpsseMMC45Enabled
= 0;
299 } else if (SystemConfiguration
->eMMCBootMode
== 3) { // eMMC 4.5
300 DEBUG ((EFI_D_ERROR
, "Force to eMMC 4.5 GPIO Configuration\n"));
301 SystemConfiguration
->LpsseMMCEnabled
= 0;
302 SystemConfiguration
->LpsseMMC45Enabled
= 1;
304 } else { // Disable eMMC controllers
305 DEBUG ((EFI_D_ERROR
, "Disable eMMC GPIO controllers\n"));
306 SystemConfiguration
->LpsseMMCEnabled
= 0;
307 SystemConfiguration
->LpsseMMC45Enabled
= 0;
312 SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
313 SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
314 SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
315 SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
316 SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
317 SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
318 MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
319 MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
320 MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
321 MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
322 MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
324 if (SystemConfiguration
->LpsseMMCEnabled
== 1) {
325 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03E0, 0x2003ED01); //EMMC 4.41
326 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0390, 0x2003EC81);
327 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03D0, 0x2003EC81);
328 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0400, 0x2003EC81);
329 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03B0, 0x2003EC81);
330 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0360, 0x2003EC81);
331 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0380, 0x2003EC81);
332 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03C0, 0x2003EC81);
333 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0370, 0x2003EC81);
334 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03F0, 0x2003EC81);
335 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0330, 0x2003ED01);
340 SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
341 SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
342 SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
343 SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
344 SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
345 SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
346 MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
347 MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
348 MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
349 MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
350 MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
352 if (SystemConfiguration
->LpsseMMC45Enabled
== 1) {
353 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03E0, 0x2003ED03); // EMMC 4.5
354 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0390, 0x2003EC83);
355 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03D0, 0x2003EC83);
356 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0400, 0x2003EC83);
357 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03B0, 0x2003EC83);
358 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0360, 0x2003EC83);
359 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0380, 0x2003EC83);
360 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03C0, 0x2003EC83);
361 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0370, 0x2003EC83);
362 MmioWrite32 (IO_BASE_ADDRESS
+ 0x03F0, 0x2003EC83);
363 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0330, 0x2003ED03);
368 // Change GPIOC_0 setting to allow MMIO access under Android.
370 IoWrite32 (GPIO_BASE_ADDRESS
+ R_PCH_GPIO_SC_USE_SEL
,
371 (IoRead32(GPIO_BASE_ADDRESS
+ R_PCH_GPIO_SC_USE_SEL
) & (UINT32
)~BIT0
));
372 DEBUG ((EFI_D_ERROR
, "ConfigureSoCGpio------------end\n"));
378 IN CONST EFI_PEI_SERVICES
**PeiServices
,
379 IN SYSTEM_CONFIGURATION
*SystemConfiguration
382 if (SystemConfiguration
->MeasuredBootEnable
) {
383 PcdSetBool (PcdMeasuredBootEnable
, TRUE
);
385 PcdSetBool (PcdMeasuredBootEnable
, FALSE
);
393 ConfigureLpssAndSccGpio (
394 IN SYSTEM_CONFIGURATION
*SystemConfiguration
,
395 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
398 /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
399 GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
400 GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
401 GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
403 DEBUG ((EFI_D_ERROR
, "ConfigureLpssAndSccGpio------------start\n"));
407 PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
409 PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
411 if (SystemConfiguration
->LpssPwm0Enabled
== 1) {
412 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00A0, 0x2003CD01);
413 } else if (SystemConfiguration
->LpssPwm0Enabled
== 0) {
414 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00A0, 0x2003CD00);
417 if (SystemConfiguration
->LpssPwm1Enabled
== 1) {
418 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00B0, 0x2003CC01);
419 } else if (SystemConfiguration
->LpssPwm1Enabled
== 0) {
420 MmioWrite32 (IO_BASE_ADDRESS
+ 0x00B0, 0x2003CD00);
425 UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
426 UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
427 UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
428 UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
430 if (SystemConfiguration
->LpssHsuart0Enabled
== 1) {
431 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0020, 0x2003CC81); // uart1
432 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0010, 0x2003CC81);
433 if (SystemConfiguration
->LpssHsuart0FlowControlEnabled
== 0) {
434 DEBUG ((EFI_D_ERROR
, "LpssHsuart0FlowControlEnabled[0]\n"));
435 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0000, 0x2003CC80);
436 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0040, 0x2003CC80);
438 DEBUG ((EFI_D_ERROR
, "LpssHsuart0FlowControlEnabled[1]\n"));
439 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0000, 0x2003CC81);
440 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
442 } else if (SystemConfiguration
->LpssHsuart0Enabled
== 0) {
443 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0020, 0x2003CC80); // uart1
444 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0010, 0x2003CC80);
450 UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
451 UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
452 UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
453 UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
455 if (SystemConfiguration
->LpssHsuart1Enabled
== 1) {
456 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0060, 0x2003CC81);
457 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0070, 0x2003CC81);
459 if (SystemConfiguration
->LpssHsuart1FlowControlEnabled
== 0) {
460 DEBUG ((EFI_D_ERROR
, "LpssHsuart1FlowControlEnabled[0]\n"));
461 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0090, 0x2003CC80); // UART2_RTS_B
462 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0080, 0x2003CC80); // UART2_CTS_B
464 DEBUG ((EFI_D_ERROR
, "LpssHsuart1FlowControlEnabled[1]\n"));
465 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0090, 0x2003CC81); // uart2
466 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
468 } else if (SystemConfiguration
->LpssHsuart1Enabled
== 0) {
469 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0060, 0x2003CC80);
470 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0070, 0x2003CC80);
475 SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
476 SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
477 SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
478 SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
480 if (SystemConfiguration
->LpssSpiEnabled
== 1) {
481 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0110, 0x2003CC81); // SPI
482 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0100, 0x2003CD01);
483 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0130, 0x2003CC81);
484 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0120, 0x2003CC81);
485 } else if (SystemConfiguration
->LpssSpiEnabled
== 0) {
486 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0110, 0x2003cc80);
487 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0100, 0x2003cc80);
488 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0130, 0x2003cc80);
489 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0120, 0x2003cc80);
494 I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
495 I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
497 if (SystemConfiguration
->LpssI2C0Enabled
== 1) {
498 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0210, 0x2003C881);
499 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0200, 0x2003C881);
503 I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
504 I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
507 if (SystemConfiguration
->LpssI2C1Enabled
== 1) {
508 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01F0, 0x2003C881);
509 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01E0, 0x2003C881);
513 I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
514 I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
516 if (SystemConfiguration
->LpssI2C2Enabled
== 1) {
517 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01D0, 0x2003C881);
518 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01B0, 0x2003C881);
522 I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
523 I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
525 if (SystemConfiguration
->LpssI2C3Enabled
== 1) {
526 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0190, 0x2003C881);
527 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01C0, 0x2003C881);
531 I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
532 I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
534 if (SystemConfiguration
->LpssI2C4Enabled
== 1) {
535 MmioWrite32 (IO_BASE_ADDRESS
+ 0x01A0, 0x2003C881);
536 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0170, 0x2003C881);
540 I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
541 I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
543 //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
544 if (SystemConfiguration
->LpssI2C5Enabled
== 1) {
545 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0150, 0x2003C881);
546 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0140, 0x2003C881);
547 } else if(SystemConfiguration
->LpssI2C5Enabled
== 0) {
548 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0150, 0x2003C880);
549 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0140, 0x2003C880);
553 I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
554 I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
556 if (SystemConfiguration
->LpssI2C6Enabled
== 1) {
557 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0180, 0x2003C881);
558 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0160, 0x2003C881);
559 } else if (SystemConfiguration
->LpssI2C6Enabled
== 0) {
560 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0180, 0x2003C880);
561 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0160, 0x2003C880);
567 SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
568 SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
569 SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
570 SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
571 SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
572 SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
574 if (SystemConfiguration
->LpssSdioEnabled
== 1) {
575 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0320, 0x2003ED01);//SDIO
576 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0300, 0x2003EC81);
577 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0350, 0x2003EC81);
578 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02F0, 0x2003EC81);
579 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0340, 0x2003EC81);
580 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0310, 0x2003EC81);
585 SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
586 SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
587 SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
588 SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
589 SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
590 SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
591 SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
592 SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
593 SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
594 SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
596 if (SystemConfiguration
->LpssSdcardEnabled
== 1) {
597 if (!((PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD
&& PlatformInfo
->BoardRev
== PR11
) && (SystemConfiguration
->CfioPnpSettings
== 1))) {
598 MmioWrite32 (IO_BASE_ADDRESS
+ 0x05F0, 0x2003CD01);//SDCARD
599 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02B0, 0x2003CD01);
600 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02C0, 0x2003CC81);
601 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02E0, 0x2003CC81);
602 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0290, 0x2003CC81);
603 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02D0, 0x2003CC81);
604 MmioWrite32 (IO_BASE_ADDRESS
+ 0x02A0, 0x2003CC81);
605 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0690, 0x2003CC81);
606 MmioWrite32 (IO_BASE_ADDRESS
+ 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
611 DEBUG ((EFI_D_ERROR
, "ConfigureLpssAndSccGpio------------end\n"));
617 IN SYSTEM_CONFIGURATION
*SystemConfiguration
620 DEBUG ((EFI_D_ERROR
, "ConfigureLpeGpio------------start\n"));
622 if (SystemConfiguration
->PchAzalia
== 0) {
623 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x220, (UINT32
)~(0x7), (UINT32
) (0x01));
624 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x250, (UINT32
)~(0x7), (UINT32
) (0x01));
625 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x240, (UINT32
)~(0x7), (UINT32
) (0x01));
626 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x260, (UINT32
)~(0x7), (UINT32
) (0x01));
627 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x270, (UINT32
)~(0x7), (UINT32
) (0x01));
628 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x230, (UINT32
)~(0x7), (UINT32
) (0x01));
629 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x280, (UINT32
)~(0x7), (UINT32
) (0x01));
630 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x540, (UINT32
)~(0x7), (UINT32
) (0x01));
633 DEBUG ((EFI_D_ERROR
, "ConfigureLpeGpio------------end\n"));
639 ConfigureSciSmiGpioRout (
640 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
)
644 GPI_Routing
= MmioRead32 (PMC_BASE_ADDRESS
+ R_PCH_PMC_GPI_ROUT
);
647 // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
649 if(PlatformInfo
->BoardRev
== 3) {
650 GPI_Routing
= GPI_Routing
& 0xfffc3ffc;
651 GPI_Routing
= GPI_Routing
| 0x00024002;
655 // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
658 GPI_Routing
= GPI_Routing
& 0x3fff3ffc;
659 GPI_Routing
= GPI_Routing
| 0x80004002;
661 MmioWrite32((PMC_BASE_ADDRESS
+ R_PCH_PMC_GPI_ROUT
), GPI_Routing
);
671 //Configure the platform clock for MIPI-CSI usage
674 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x6a0, (UINT32
)~(0x7), (UINT32
) (0x01));
679 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x570, (UINT32
)~(0x7), (UINT32
) (0x01));
684 MmioAndThenOr32 (IO_BASE_ADDRESS
+ 0x5B0, (UINT32
)~(0x7), (UINT32
) (0x01));
697 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x338, (UINT32
)~(0x7), (UINT32
) (GPI
));
698 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x330, (UINT32
)~(0x187), (UINT32
) (0x101));
703 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x388, (UINT32
)~(0x7), (UINT32
) (GPI
));
704 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x380, (UINT32
)~(0x187), (UINT32
) (0x101));
709 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x368, (UINT32
)~(0x7), (UINT32
) (GPI
));
710 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x360, (UINT32
)~(0x187), (UINT32
) (0x101));
715 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x318, (UINT32
)~(0x7), (UINT32
) (GPI
));
716 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x310, (UINT32
)~(0x187), (UINT32
) (0x101));
721 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x378, (UINT32
)~(0x7), (UINT32
) (GPI
));
722 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x370, (UINT32
)~(0x187), (UINT32
) (0x101));
727 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x308, (UINT32
)~(0x7), (UINT32
) (GPI
));
728 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x300, (UINT32
)~(0x187), (UINT32
) (0x101));
733 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x398, (UINT32
)~(0x7), (UINT32
) (GPI
));
734 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x390, (UINT32
)~(0x187), (UINT32
) (0x101));
739 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x328, (UINT32
)~(0x7), (UINT32
) (GPI
));
740 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x320, (UINT32
)~(0x187), (UINT32
) (0x101));
745 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3a8, (UINT32
)~(0x7), (UINT32
) (GPI
));
746 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3a0, (UINT32
)~(0x187), (UINT32
) (0x101));
751 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x348, (UINT32
)~(0x7), (UINT32
) (GPI
));
752 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x340, (UINT32
)~(0x187), (UINT32
) (0x81));
757 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x358, (UINT32
)~(0x7), (UINT32
) (GPI
));
758 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x350, (UINT32
)~(0x187), (UINT32
) (0x101));
763 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3b8, (UINT32
)~(0x7), (UINT32
) (GPI
));
764 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x3b0, (UINT32
)~(0x187), (UINT32
) (0x81));
769 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x288, (UINT32
)~(0x7), (UINT32
) (GPI
));
770 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x280, (UINT32
)~(0x187), (UINT32
) (0x101));
782 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x210, (UINT32
)~(0x0f000007), (UINT32
) (0x00));
783 MmioAndThenOr32 (IO_BASE_ADDRESS
+ GPIO_SSUS_OFFSET
+ 0x1e0, (UINT32
)~(0x0f000007), (UINT32
) (0x00));
789 Platform specific initializations in stage1.
791 @param FfsHeader Pointer to the PEIM FFS file header.
792 @param PeiServices General purpose services available to every PEIM.
794 @retval EFI_SUCCESS Operation completed successfully.
795 @retval Otherwise Platform initialization failed.
799 PlatformEarlyInitEntry (
801 IN EFI_PEI_FILE_HANDLE FileHandle
,
802 IN CONST EFI_PEI_SERVICES
**PeiServices
806 SYSTEM_CONFIGURATION SystemConfiguration
;
807 EFI_PLATFORM_INFO_HOB
*PlatformInfo
;
808 EFI_PEI_HOB_POINTERS Hob
;
809 EFI_PLATFORM_CPU_INFO PlatformCpuInfo
;
812 // Initialize SmbusPolicy PPI
814 Status
= (*PeiServices
)->InstallPpi(PeiServices
, &mInstallSmbusPolicyPpi
);
815 ASSERT_EFI_ERROR (Status
);
818 // Initialize Stall PPIs
820 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mInstallStallPpi
);
821 ASSERT_EFI_ERROR (Status
);
824 // Initialize platform PPIs
826 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mInstallSpeakerInterfacePpi
);
827 ASSERT_EFI_ERROR (Status
);
830 // Variable initialization
832 ZeroMem(&PlatformCpuInfo
, sizeof(EFI_PLATFORM_CPU_INFO
));
835 // Set the some PCI and chipset range as UC
836 // And align to 1M at leaset
838 Hob
.Raw
= GetFirstGuidHob (&gEfiPlatformInfoGuid
);
839 ASSERT (Hob
.Raw
!= NULL
);
840 PlatformInfo
= GET_GUID_HOB_DATA(Hob
.Raw
);
843 // Initialize PlatformInfo HOB
845 MultiPlatformInfoInit(PeiServices
, PlatformInfo
);
850 MchInit (PeiServices
);
853 // Set the new boot mode
855 Status
= UpdateBootMode (PeiServices
, PlatformInfo
);
856 ASSERT_EFI_ERROR (Status
);
858 SetPlatformBootMode (PeiServices
, PlatformInfo
);
861 // Get setup variable. This can only be done after BootMode is updated
863 GetSetupVariable (PeiServices
, &SystemConfiguration
);
865 CheckOsSelection(PeiServices
, &SystemConfiguration
);
868 // Update PlatformInfo HOB according to setup variable
870 PlatformInfoUpdate(PeiServices
, PlatformInfo
, &SystemConfiguration
);
872 InitializePlatform (PeiServices
, PlatformInfo
, &SystemConfiguration
);
875 // Initialize VlvPolicy PPI
877 Status
= VlvPolicyInit (PeiServices
, &SystemConfiguration
);
878 ASSERT_EFI_ERROR (Status
);
881 // Soc specific GPIO setting
883 ConfigureSoCGpio(&SystemConfiguration
);
886 // Baylake Board specific.
888 if (PlatformInfo
->BoardId
== BOARD_ID_BL_RVP
||
889 PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD
||
890 PlatformInfo
->BoardId
== BOARD_ID_BL_FFRD8
||
891 PlatformInfo
->BoardId
== BOARD_ID_BL_RVP_DDR3L
||
892 PlatformInfo
->BoardId
== BOARD_ID_BL_STHI
||
893 PlatformInfo
->BoardId
== BOARD_ID_BB_RVP
||
894 PlatformInfo
->BoardId
== BOARD_ID_BS_RVP
||
895 PlatformInfo
->BoardId
== BOARD_ID_MINNOW2
||
896 PlatformInfo
->BoardId
== BOARD_ID_CVH
) {
897 ConfigureLpssAndSccGpio(&SystemConfiguration
, PlatformInfo
);
904 // Alpine Valley and Bayley Bay board specific
906 ConfigureLpeGpio(&SystemConfiguration
);
909 // Bayley Bay Board specific.
911 ConfigureSciSmiGpioRout(PlatformInfo
);
912 if (SystemConfiguration
.LpssI2C3Enabled
== 1) {
920 Status
= PlatformCpuInit (PeiServices
, &SystemConfiguration
, &PlatformCpuInfo
);
923 // Perform basic SSA related platform initialization
925 PlatformSsaInit (&SystemConfiguration
,PeiServices
);
931 Status
= PlatformPchInit (&SystemConfiguration
, PeiServices
, PlatformInfo
->PlatformType
);
932 ASSERT_EFI_ERROR (Status
);
935 // Initialize platform PPIs
937 Status
= (*PeiServices
)->InstallPpi (PeiServices
, &mPpiList
[0]);
938 ASSERT_EFI_ERROR (Status
);
940 if (PlatformInfo
->BoardId
!= BOARD_ID_CVH
) {
941 InstallPlatformClocksNotify (PeiServices
);
942 InstallPlatformSysCtrlGPIONotify(PeiServices
);
946 // Initialize platform PPIs
948 Status
= (*PeiServices
)->NotifyPpi(PeiServices
, &mNotifyList
[0]);
949 ASSERT_EFI_ERROR (Status
);
952 // Initialize Measured Boot
954 Status
= MeasuredBootInit (PeiServices
, &SystemConfiguration
);
955 ASSERT_EFI_ERROR (Status
);
962 Return the mainblockcompact Fv.
964 @param FvNumber Our enumeration of the firmware volumes we care about.
966 @param FvAddress Base Address of the memory containing the firmware volume
969 @retval EFI_NOT_FOUND
975 IN EFI_PEI_FIND_FV_PPI
*This
,
976 IN CONST EFI_PEI_SERVICES
**PeiServices
,
977 IN OUT UINT8
*FvNumber
,
978 OUT EFI_FIRMWARE_VOLUME_HEADER
**FVAddress
982 // At present, we only have one Fv to search
984 if (*FvNumber
== 0) {
986 *FVAddress
= (EFI_FIRMWARE_VOLUME_HEADER
*)(UINTN
)FixedPcdGet32 (PcdFlashFvMainBase
);
989 else if (*FvNumber
== 1) {
991 *FVAddress
= (EFI_FIRMWARE_VOLUME_HEADER
*)(UINTN
)FixedPcdGet32 (PcdFlashFvRecovery2Base
);
994 else { // Not the one Fv we care about
995 return EFI_NOT_FOUND
;
1002 IN CONST EFI_PEI_SERVICES
**PeiServices
1005 // MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
1024 // If we get here we need to mark it as a failure.
1026 return EFI_UNSUPPORTED
;
1031 #pragma GCC pop_options
1033 #pragma optimize ("", on)