1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KEEPINITRD
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_CUSTOM_GPIO_H
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_USE_MEMTEST
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select ARCH_WANT_LD_ORPHAN_WARN
41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42 select BUILDTIME_TABLE_SORT if MMU
43 select CLONE_BACKWARDS
44 select CPU_PM if SUSPEND || CPU_IDLE
45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46 select DMA_DECLARE_COHERENT
47 select DMA_GLOBAL_POOL if !MMU
49 select DMA_REMAP if MMU
51 select EDAC_ATOMIC_SCRUB
52 select GENERIC_ALLOCATOR
53 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
54 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
55 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
56 select GENERIC_IRQ_IPI if SMP
57 select GENERIC_CPU_AUTOPROBE
58 select GENERIC_EARLY_IOREMAP
59 select GENERIC_IDLE_POLL_SETUP
60 select GENERIC_IRQ_PROBE
61 select GENERIC_IRQ_SHOW
62 select GENERIC_IRQ_SHOW_LEVEL
63 select GENERIC_LIB_DEVMEM_IS_ALLOWED
64 select GENERIC_PCI_IOMAP
65 select GENERIC_SCHED_CLOCK
66 select GENERIC_SMP_IDLE_THREAD
67 select HANDLE_DOMAIN_IRQ
68 select HARDIRQS_SW_RESEND
69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
72 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
73 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
74 select HAVE_ARCH_MMAP_RND_BITS if MMU
75 select HAVE_ARCH_PFN_VALID
76 select HAVE_ARCH_SECCOMP
77 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
78 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
79 select HAVE_ARCH_TRACEHOOK
80 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
81 select HAVE_ARM_SMCCC if CPU_V7
82 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
83 select HAVE_CONTEXT_TRACKING
84 select HAVE_C_RECORDMCOUNT
85 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
86 select HAVE_DMA_CONTIGUOUS if MMU
87 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
88 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
89 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
90 select HAVE_EXIT_THREAD
91 select HAVE_FAST_GUP if ARM_LPAE
92 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
93 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
94 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
95 select HAVE_GCC_PLUGINS
96 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
97 select HAVE_IRQ_TIME_ACCOUNTING
98 select HAVE_KERNEL_GZIP
99 select HAVE_KERNEL_LZ4
100 select HAVE_KERNEL_LZMA
101 select HAVE_KERNEL_LZO
102 select HAVE_KERNEL_XZ
103 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
104 select HAVE_KRETPROBES if HAVE_KPROBES
105 select HAVE_MOD_ARCH_SPECIFIC
107 select HAVE_OPTPROBES if !THUMB2_KERNEL
108 select HAVE_PERF_EVENTS
109 select HAVE_PERF_REGS
110 select HAVE_PERF_USER_STACK_DUMP
111 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
112 select HAVE_REGS_AND_STACK_ACCESS_API
114 select HAVE_STACKPROTECTOR
115 select HAVE_SYSCALL_TRACEPOINTS
117 select HAVE_VIRT_CPU_ACCOUNTING_GEN
118 select IRQ_FORCED_THREADING
119 select MODULES_USE_ELF_REL
120 select NEED_DMA_MAP_STATE
121 select OF_EARLY_FLATTREE if OF
123 select OLD_SIGSUSPEND3
124 select PCI_SYSCALL if PCI
125 select PERF_USE_VMALLOC
128 select SYS_SUPPORTS_APM_EMULATION
129 # Above selects are sorted alphabetically; please add new ones
130 # according to that. Thanks.
132 The ARM series is a line of low-power-consumption RISC chip designs
133 licensed by ARM Ltd and targeted at embedded applications and
134 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
135 manufactured, but legacy ARM-based PC hardware remains popular in
136 Europe. There is an ARM Linux project with a web page at
137 <http://www.arm.linux.org.uk/>.
139 config ARM_HAS_SG_CHAIN
142 config ARM_DMA_USE_IOMMU
144 select ARM_HAS_SG_CHAIN
145 select NEED_SG_DMA_LENGTH
149 config ARM_DMA_IOMMU_ALIGNMENT
150 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
154 DMA mapping framework by default aligns all buffers to the smallest
155 PAGE_SIZE order which is greater than or equal to the requested buffer
156 size. This works well for buffers up to a few hundreds kilobytes, but
157 for larger buffers it just a waste of address space. Drivers which has
158 relatively small addressing window (like 64Mib) might run out of
159 virtual space with just a few allocations.
161 With this parameter you can specify the maximum PAGE_SIZE order for
162 DMA IOMMU buffers. Larger buffers will be aligned only to this
163 specified order. The order is expressed as a power of two multiplied
168 config SYS_SUPPORTS_APM_EMULATION
173 select GENERIC_ALLOCATOR
184 config STACKTRACE_SUPPORT
188 config LOCKDEP_SUPPORT
192 config TRACE_IRQFLAGS_SUPPORT
196 config ARCH_HAS_ILOG2_U32
199 config ARCH_HAS_ILOG2_U64
202 config ARCH_HAS_BANDGAP
205 config FIX_EARLYCON_MEM
208 config GENERIC_HWEIGHT
212 config GENERIC_CALIBRATE_DELAY
216 config ARCH_MAY_HAVE_PC_FDC
219 config ARCH_SUPPORTS_UPROBES
222 config ARCH_HAS_DMA_SET_COHERENT_MASK
225 config GENERIC_ISA_DMA
231 config NEED_RET_TO_USER
237 config ARM_PATCH_PHYS_VIRT
238 bool "Patch physical to virtual translations at runtime" if EMBEDDED
240 depends on !XIP_KERNEL && MMU
242 Patch phys-to-virt and virt-to-phys translation functions at
243 boot and module load time according to the position of the
244 kernel in system memory.
246 This can only be used with non-XIP MMU kernels where the base
247 of physical memory is at a 2 MiB boundary.
249 Only disable this option if you know that you do not require
250 this feature (eg, building a kernel for a single machine) and
251 you need to shrink the kernel to the minimal size.
253 config NEED_MACH_IO_H
256 Select this when mach/io.h is required to provide special
257 definitions for this platform. The need for mach/io.h should
258 be avoided when possible.
260 config NEED_MACH_MEMORY_H
263 Select this when mach/memory.h is required to provide special
264 definitions for this platform. The need for mach/memory.h should
265 be avoided when possible.
268 hex "Physical address of main memory" if MMU
269 depends on !ARM_PATCH_PHYS_VIRT
270 default DRAM_BASE if !MMU
271 default 0x00000000 if ARCH_FOOTBRIDGE
272 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
273 default 0x20000000 if ARCH_S5PV210
274 default 0xc0000000 if ARCH_SA1100
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 config PGTABLE_LEVELS
285 default 3 if ARM_LPAE
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
297 config ARCH_MMAP_RND_BITS_MIN
300 config ARCH_MMAP_RND_BITS_MAX
301 default 14 if PAGE_OFFSET=0x40000000
302 default 15 if PAGE_OFFSET=0x80000000
306 # The "ARM system type" choice list is ordered alphabetically by option
307 # text. Please add new entries in the option alphabetic order.
310 prompt "ARM system type"
311 default ARM_SINGLE_ARMV7M if !MMU
312 default ARCH_MULTIPLATFORM if MMU
314 config ARCH_MULTIPLATFORM
315 bool "Allow multiple platforms to be selected"
317 select ARCH_FLATMEM_ENABLE
318 select ARCH_SPARSEMEM_ENABLE
319 select ARCH_SELECT_MEMORY_MODEL
320 select ARM_HAS_SG_CHAIN
321 select ARM_PATCH_PHYS_VIRT
325 select GENERIC_IRQ_MULTI_HANDLER
327 select PCI_DOMAINS_GENERIC if PCI
331 config ARM_SINGLE_ARMV7M
332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
345 select ARCH_SPARSEMEM_ENABLE
347 imply ARM_PATCH_PHYS_VIRT
349 select GENERIC_IRQ_MULTI_HANDLER
354 select HAVE_LEGACY_CLK
356 This enables support for the Cirrus EP93xx series of CPUs.
358 config ARCH_FOOTBRIDGE
362 select NEED_MACH_IO_H if !MMU
363 select NEED_MACH_MEMORY_H
365 Support for systems based on the DC21285 companion chip
366 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
374 select NEED_RET_TO_USER
378 Support for Intel's 80219 and IOP32X (XScale) family of
384 select ARCH_HAS_DMA_SET_COHERENT_MASK
385 select ARCH_SUPPORTS_BIG_ENDIAN
387 select DMABOUNCE if PCI
388 select GENERIC_IRQ_MULTI_HANDLER
394 # With the new PCI driver this is not needed
395 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
396 select USB_EHCI_BIG_ENDIAN_DESC
397 select USB_EHCI_BIG_ENDIAN_MMIO
399 Support for Intel's IXP4XX (XScale) family of processors.
404 select GENERIC_IRQ_MULTI_HANDLER
410 select PLAT_ORION_LEGACY
412 select PM_GENERIC_DOMAINS if PM
414 Support for the Marvell Dove SoC 88AP510
417 bool "PXA2xx/PXA3xx-based"
420 select ARM_CPU_SUSPEND if PM
426 select CPU_XSCALE if !CPU_XSC3
427 select GENERIC_IRQ_MULTI_HANDLER
434 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
440 select ARCH_MAY_HAVE_PC_FDC
441 select ARCH_SPARSEMEM_ENABLE
442 select ARM_HAS_SG_CHAIN
445 select HAVE_PATA_PLATFORM
447 select LEGACY_TIMER_TICK
448 select NEED_MACH_IO_H
449 select NEED_MACH_MEMORY_H
452 On the Acorn Risc-PC, Linux can support the internal IDE disk and
453 CD-ROM interface, serial and parallel port, and the floppy drive.
458 select ARCH_SPARSEMEM_ENABLE
461 select TIMER_OF if OF
465 select GENERIC_IRQ_MULTI_HANDLER
469 select NEED_MACH_MEMORY_H
472 Support for StrongARM 11x0 based boards.
475 bool "Samsung S3C24XX SoCs"
477 select CLKSRC_SAMSUNG_PWM
480 select GENERIC_IRQ_MULTI_HANDLER
481 select HAVE_S3C2410_I2C if I2C
482 select HAVE_S3C_RTC if RTC_CLASS
483 select NEED_MACH_IO_H
484 select S3C2410_WATCHDOG
489 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
490 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
491 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
492 Samsung SMDK2410 development board (and derivatives).
499 select GENERIC_IRQ_CHIP
500 select GENERIC_IRQ_MULTI_HANDLER
502 select HAVE_LEGACY_CLK
504 select NEED_MACH_IO_H if PCCARD
505 select NEED_MACH_MEMORY_H
508 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
512 menu "Multiple platform selection"
513 depends on ARCH_MULTIPLATFORM
515 comment "CPU Core family selection"
518 bool "ARMv4 based platforms (FA526)"
519 depends on !ARCH_MULTI_V6_V7
520 select ARCH_MULTI_V4_V5
523 config ARCH_MULTI_V4T
524 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
525 depends on !ARCH_MULTI_V6_V7
526 select ARCH_MULTI_V4_V5
527 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
528 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
529 CPU_ARM925T || CPU_ARM940T)
532 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
533 depends on !ARCH_MULTI_V6_V7
534 select ARCH_MULTI_V4_V5
535 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
536 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
537 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
539 config ARCH_MULTI_V4_V5
543 bool "ARMv6 based platforms (ARM11)"
544 select ARCH_MULTI_V6_V7
548 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
550 select ARCH_MULTI_V6_V7
554 config ARCH_MULTI_V6_V7
556 select MIGHT_HAVE_CACHE_L2X0
558 config ARCH_MULTI_CPU_AUTO
559 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
565 bool "Dummy Virtual Machine"
566 depends on ARCH_MULTI_V7
569 select ARM_GIC_V2M if PCI
571 select ARM_GIC_V3_ITS if PCI
573 select HAVE_ARM_ARCH_TIMER
574 select ARCH_SUPPORTS_BIG_ENDIAN
577 # This is sorted alphabetically by mach-* pathname. However, plat-*
578 # Kconfigs may be included either alphabetically (according to the
579 # plat- suffix) or along side the corresponding mach-* source.
581 source "arch/arm/mach-actions/Kconfig"
583 source "arch/arm/mach-alpine/Kconfig"
585 source "arch/arm/mach-artpec/Kconfig"
587 source "arch/arm/mach-asm9260/Kconfig"
589 source "arch/arm/mach-aspeed/Kconfig"
591 source "arch/arm/mach-at91/Kconfig"
593 source "arch/arm/mach-axxia/Kconfig"
595 source "arch/arm/mach-bcm/Kconfig"
597 source "arch/arm/mach-berlin/Kconfig"
599 source "arch/arm/mach-clps711x/Kconfig"
601 source "arch/arm/mach-cns3xxx/Kconfig"
603 source "arch/arm/mach-davinci/Kconfig"
605 source "arch/arm/mach-digicolor/Kconfig"
607 source "arch/arm/mach-dove/Kconfig"
609 source "arch/arm/mach-ep93xx/Kconfig"
611 source "arch/arm/mach-exynos/Kconfig"
613 source "arch/arm/mach-footbridge/Kconfig"
615 source "arch/arm/mach-gemini/Kconfig"
617 source "arch/arm/mach-highbank/Kconfig"
619 source "arch/arm/mach-hisi/Kconfig"
621 source "arch/arm/mach-imx/Kconfig"
623 source "arch/arm/mach-integrator/Kconfig"
625 source "arch/arm/mach-iop32x/Kconfig"
627 source "arch/arm/mach-ixp4xx/Kconfig"
629 source "arch/arm/mach-keystone/Kconfig"
631 source "arch/arm/mach-lpc32xx/Kconfig"
633 source "arch/arm/mach-mediatek/Kconfig"
635 source "arch/arm/mach-meson/Kconfig"
637 source "arch/arm/mach-milbeaut/Kconfig"
639 source "arch/arm/mach-mmp/Kconfig"
641 source "arch/arm/mach-moxart/Kconfig"
643 source "arch/arm/mach-mstar/Kconfig"
645 source "arch/arm/mach-mv78xx0/Kconfig"
647 source "arch/arm/mach-mvebu/Kconfig"
649 source "arch/arm/mach-mxs/Kconfig"
651 source "arch/arm/mach-nomadik/Kconfig"
653 source "arch/arm/mach-npcm/Kconfig"
655 source "arch/arm/mach-nspire/Kconfig"
657 source "arch/arm/plat-omap/Kconfig"
659 source "arch/arm/mach-omap1/Kconfig"
661 source "arch/arm/mach-omap2/Kconfig"
663 source "arch/arm/mach-orion5x/Kconfig"
665 source "arch/arm/mach-oxnas/Kconfig"
667 source "arch/arm/mach-pxa/Kconfig"
668 source "arch/arm/plat-pxa/Kconfig"
670 source "arch/arm/mach-qcom/Kconfig"
672 source "arch/arm/mach-rda/Kconfig"
674 source "arch/arm/mach-realtek/Kconfig"
676 source "arch/arm/mach-realview/Kconfig"
678 source "arch/arm/mach-rockchip/Kconfig"
680 source "arch/arm/mach-s3c/Kconfig"
682 source "arch/arm/mach-s5pv210/Kconfig"
684 source "arch/arm/mach-sa1100/Kconfig"
686 source "arch/arm/mach-shmobile/Kconfig"
688 source "arch/arm/mach-socfpga/Kconfig"
690 source "arch/arm/mach-spear/Kconfig"
692 source "arch/arm/mach-sti/Kconfig"
694 source "arch/arm/mach-stm32/Kconfig"
696 source "arch/arm/mach-sunxi/Kconfig"
698 source "arch/arm/mach-tegra/Kconfig"
700 source "arch/arm/mach-uniphier/Kconfig"
702 source "arch/arm/mach-ux500/Kconfig"
704 source "arch/arm/mach-versatile/Kconfig"
706 source "arch/arm/mach-vexpress/Kconfig"
708 source "arch/arm/mach-vt8500/Kconfig"
710 source "arch/arm/mach-zynq/Kconfig"
712 # ARMv7-M architecture
714 bool "NXP LPC18xx/LPC43xx"
715 depends on ARM_SINGLE_ARMV7M
716 select ARCH_HAS_RESET_CONTROLLER
718 select CLKSRC_LPC32XX
721 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
722 high performance microcontrollers.
725 bool "ARM MPS2 platform"
726 depends on ARM_SINGLE_ARMV7M
730 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
731 with a range of available cores like Cortex-M3/M4/M7.
733 Please, note that depends which Application Note is used memory map
734 for the platform may vary, so adjustment of RAM base might be needed.
736 # Definitions to make life easier
747 select GENERIC_IRQ_CHIP
750 config PLAT_ORION_LEGACY
757 config PLAT_VERSATILE
760 source "arch/arm/mm/Kconfig"
763 bool "Enable iWMMXt support"
764 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
765 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
767 Enable support for iWMMXt context switching at run time if
768 running on a CPU that supports it.
771 source "arch/arm/Kconfig-nommu"
774 config PJ4B_ERRATA_4742
775 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
776 depends on CPU_PJ4B && MACH_ARMADA_370
779 When coming out of either a Wait for Interrupt (WFI) or a Wait for
780 Event (WFE) IDLE states, a specific timing sensitivity exists between
781 the retiring WFI/WFE instructions and the newly issued subsequent
782 instructions. This sensitivity can result in a CPU hang scenario.
784 The software must insert either a Data Synchronization Barrier (DSB)
785 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
788 config ARM_ERRATA_326103
789 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
792 Executing a SWP instruction to read-only memory does not set bit 11
793 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
794 treat the access as a read, preventing a COW from occurring and
795 causing the faulting task to livelock.
797 config ARM_ERRATA_411920
798 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
799 depends on CPU_V6 || CPU_V6K
801 Invalidation of the Instruction Cache operation can
802 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
803 It does not affect the MPCore. This option enables the ARM Ltd.
804 recommended workaround.
806 config ARM_ERRATA_430973
807 bool "ARM errata: Stale prediction on replaced interworking branch"
810 This option enables the workaround for the 430973 Cortex-A8
811 r1p* erratum. If a code sequence containing an ARM/Thumb
812 interworking branch is replaced with another code sequence at the
813 same virtual address, whether due to self-modifying code or virtual
814 to physical address re-mapping, Cortex-A8 does not recover from the
815 stale interworking branch prediction. This results in Cortex-A8
816 executing the new code sequence in the incorrect ARM or Thumb state.
817 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
818 and also flushes the branch target cache at every context switch.
819 Note that setting specific bits in the ACTLR register may not be
820 available in non-secure mode.
822 config ARM_ERRATA_458693
823 bool "ARM errata: Processor deadlock when a false hazard is created"
825 depends on !ARCH_MULTIPLATFORM
827 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
828 erratum. For very specific sequences of memory operations, it is
829 possible for a hazard condition intended for a cache line to instead
830 be incorrectly associated with a different cache line. This false
831 hazard might then cause a processor deadlock. The workaround enables
832 the L1 caching of the NEON accesses and disables the PLD instruction
833 in the ACTLR register. Note that setting specific bits in the ACTLR
834 register may not be available in non-secure mode.
836 config ARM_ERRATA_460075
837 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
839 depends on !ARCH_MULTIPLATFORM
841 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
842 erratum. Any asynchronous access to the L2 cache may encounter a
843 situation in which recent store transactions to the L2 cache are lost
844 and overwritten with stale memory contents from external memory. The
845 workaround disables the write-allocate mode for the L2 cache via the
846 ACTLR register. Note that setting specific bits in the ACTLR register
847 may not be available in non-secure mode.
849 config ARM_ERRATA_742230
850 bool "ARM errata: DMB operation may be faulty"
851 depends on CPU_V7 && SMP
852 depends on !ARCH_MULTIPLATFORM
854 This option enables the workaround for the 742230 Cortex-A9
855 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
856 between two write operations may not ensure the correct visibility
857 ordering of the two writes. This workaround sets a specific bit in
858 the diagnostic register of the Cortex-A9 which causes the DMB
859 instruction to behave as a DSB, ensuring the correct behaviour of
862 config ARM_ERRATA_742231
863 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
864 depends on CPU_V7 && SMP
865 depends on !ARCH_MULTIPLATFORM
867 This option enables the workaround for the 742231 Cortex-A9
868 (r2p0..r2p2) erratum. Under certain conditions, specific to the
869 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
870 accessing some data located in the same cache line, may get corrupted
871 data due to bad handling of the address hazard when the line gets
872 replaced from one of the CPUs at the same time as another CPU is
873 accessing it. This workaround sets specific bits in the diagnostic
874 register of the Cortex-A9 which reduces the linefill issuing
875 capabilities of the processor.
877 config ARM_ERRATA_643719
878 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
879 depends on CPU_V7 && SMP
882 This option enables the workaround for the 643719 Cortex-A9 (prior to
883 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
884 register returns zero when it should return one. The workaround
885 corrects this value, ensuring cache maintenance operations which use
886 it behave as intended and avoiding data corruption.
888 config ARM_ERRATA_720789
889 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
892 This option enables the workaround for the 720789 Cortex-A9 (prior to
893 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
894 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
895 As a consequence of this erratum, some TLB entries which should be
896 invalidated are not, resulting in an incoherency in the system page
897 tables. The workaround changes the TLB flushing routines to invalidate
898 entries regardless of the ASID.
900 config ARM_ERRATA_743622
901 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
903 depends on !ARCH_MULTIPLATFORM
905 This option enables the workaround for the 743622 Cortex-A9
906 (r2p*) erratum. Under very rare conditions, a faulty
907 optimisation in the Cortex-A9 Store Buffer may lead to data
908 corruption. This workaround sets a specific bit in the diagnostic
909 register of the Cortex-A9 which disables the Store Buffer
910 optimisation, preventing the defect from occurring. This has no
911 visible impact on the overall performance or power consumption of the
914 config ARM_ERRATA_751472
915 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
917 depends on !ARCH_MULTIPLATFORM
919 This option enables the workaround for the 751472 Cortex-A9 (prior
920 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
921 completion of a following broadcasted operation if the second
922 operation is received by a CPU before the ICIALLUIS has completed,
923 potentially leading to corrupted entries in the cache or TLB.
925 config ARM_ERRATA_754322
926 bool "ARM errata: possible faulty MMU translations following an ASID switch"
929 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
930 r3p*) erratum. A speculative memory access may cause a page table walk
931 which starts prior to an ASID switch but completes afterwards. This
932 can populate the micro-TLB with a stale entry which may be hit with
933 the new ASID. This workaround places two dsb instructions in the mm
934 switching code so that no page table walks can cross the ASID switch.
936 config ARM_ERRATA_754327
937 bool "ARM errata: no automatic Store Buffer drain"
938 depends on CPU_V7 && SMP
940 This option enables the workaround for the 754327 Cortex-A9 (prior to
941 r2p0) erratum. The Store Buffer does not have any automatic draining
942 mechanism and therefore a livelock may occur if an external agent
943 continuously polls a memory location waiting to observe an update.
944 This workaround defines cpu_relax() as smp_mb(), preventing correctly
945 written polling loops from denying visibility of updates to memory.
947 config ARM_ERRATA_364296
948 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
951 This options enables the workaround for the 364296 ARM1136
952 r0p2 erratum (possible cache data corruption with
953 hit-under-miss enabled). It sets the undocumented bit 31 in
954 the auxiliary control register and the FI bit in the control
955 register, thus disabling hit-under-miss without putting the
956 processor into full low interrupt latency mode. ARM11MPCore
959 config ARM_ERRATA_764369
960 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
961 depends on CPU_V7 && SMP
963 This option enables the workaround for erratum 764369
964 affecting Cortex-A9 MPCore with two or more processors (all
965 current revisions). Under certain timing circumstances, a data
966 cache line maintenance operation by MVA targeting an Inner
967 Shareable memory region may fail to proceed up to either the
968 Point of Coherency or to the Point of Unification of the
969 system. This workaround adds a DSB instruction before the
970 relevant cache maintenance functions and sets a specific bit
971 in the diagnostic control register of the SCU.
973 config ARM_ERRATA_775420
974 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
977 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
978 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
979 operation aborts with MMU exception, it might cause the processor
980 to deadlock. This workaround puts DSB before executing ISB if
981 an abort may occur on cache maintenance.
983 config ARM_ERRATA_798181
984 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
985 depends on CPU_V7 && SMP
987 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
988 adequately shooting down all use of the old entries. This
989 option enables the Linux kernel workaround for this erratum
990 which sends an IPI to the CPUs that are running the same ASID
991 as the one being invalidated.
993 config ARM_ERRATA_773022
994 bool "ARM errata: incorrect instructions may be executed from loop buffer"
997 This option enables the workaround for the 773022 Cortex-A15
998 (up to r0p4) erratum. In certain rare sequences of code, the
999 loop buffer may deliver incorrect instructions. This
1000 workaround disables the loop buffer to avoid the erratum.
1002 config ARM_ERRATA_818325_852422
1003 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1006 This option enables the workaround for:
1007 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1008 instruction might deadlock. Fixed in r0p1.
1009 - Cortex-A12 852422: Execution of a sequence of instructions might
1010 lead to either a data corruption or a CPU deadlock. Not fixed in
1011 any Cortex-A12 cores yet.
1012 This workaround for all both errata involves setting bit[12] of the
1013 Feature Register. This bit disables an optimisation applied to a
1014 sequence of 2 instructions that use opposing condition codes.
1016 config ARM_ERRATA_821420
1017 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1020 This option enables the workaround for the 821420 Cortex-A12
1021 (all revs) erratum. In very rare timing conditions, a sequence
1022 of VMOV to Core registers instructions, for which the second
1023 one is in the shadow of a branch or abort, can lead to a
1024 deadlock when the VMOV instructions are issued out-of-order.
1026 config ARM_ERRATA_825619
1027 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1030 This option enables the workaround for the 825619 Cortex-A12
1031 (all revs) erratum. Within rare timing constraints, executing a
1032 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1033 and Device/Strongly-Ordered loads and stores might cause deadlock
1035 config ARM_ERRATA_857271
1036 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1039 This option enables the workaround for the 857271 Cortex-A12
1040 (all revs) erratum. Under very rare timing conditions, the CPU might
1041 hang. The workaround is expected to have a < 1% performance impact.
1043 config ARM_ERRATA_852421
1044 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1047 This option enables the workaround for the 852421 Cortex-A17
1048 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1049 execution of a DMB ST instruction might fail to properly order
1050 stores from GroupA and stores from GroupB.
1052 config ARM_ERRATA_852423
1053 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1056 This option enables the workaround for:
1057 - Cortex-A17 852423: Execution of a sequence of instructions might
1058 lead to either a data corruption or a CPU deadlock. Not fixed in
1059 any Cortex-A17 cores yet.
1060 This is identical to Cortex-A12 erratum 852422. It is a separate
1061 config option from the A12 erratum due to the way errata are checked
1064 config ARM_ERRATA_857272
1065 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1068 This option enables the workaround for the 857272 Cortex-A17 erratum.
1069 This erratum is not known to be fixed in any A17 revision.
1070 This is identical to Cortex-A12 erratum 857271. It is a separate
1071 config option from the A12 erratum due to the way errata are checked
1076 source "arch/arm/common/Kconfig"
1083 Find out whether you have ISA slots on your motherboard. ISA is the
1084 name of a bus system, i.e. the way the CPU talks to the other stuff
1085 inside your box. Other bus systems are PCI, EISA, MicroChannel
1086 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1087 newer boards don't support it. If you have ISA, say Y, otherwise N.
1089 # Select ISA DMA controller support
1094 # Select ISA DMA interface
1098 config PCI_NANOENGINE
1099 bool "BSE nanoEngine PCI support"
1100 depends on SA1100_NANOENGINE
1102 Enable PCI on the BSE nanoEngine board.
1104 config ARM_ERRATA_814220
1105 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1108 The v7 ARM states that all cache and branch predictor maintenance
1109 operations that do not specify an address execute, relative to
1110 each other, in program order.
1111 However, because of this erratum, an L2 set/way cache maintenance
1112 operation can overtake an L1 set/way cache maintenance operation.
1113 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1118 menu "Kernel Features"
1123 This option should be selected by machines which have an SMP-
1126 The only effect of this option is to make the SMP-related
1127 options available to the user for configuration.
1130 bool "Symmetric Multi-Processing"
1131 depends on CPU_V6K || CPU_V7
1133 depends on MMU || ARM_MPU
1136 This enables support for systems with more than one CPU. If you have
1137 a system with only one CPU, say N. If you have a system with more
1138 than one CPU, say Y.
1140 If you say N here, the kernel will run on uni- and multiprocessor
1141 machines, but will use only one CPU of a multiprocessor machine. If
1142 you say Y here, the kernel will run on many, but not all,
1143 uniprocessor machines. On a uniprocessor machine, the kernel
1144 will run faster if you say N here.
1146 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1147 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1148 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1150 If you don't know what to do here, say N.
1153 bool "Allow booting SMP kernel on uniprocessor systems"
1154 depends on SMP && !XIP_KERNEL && MMU
1157 SMP kernels contain instructions which fail on non-SMP processors.
1158 Enabling this option allows the kernel to modify itself to make
1159 these instructions safe. Disabling it allows about 1K of space
1162 If you don't know what to do here, say Y.
1164 config ARM_CPU_TOPOLOGY
1165 bool "Support cpu topology definition"
1166 depends on SMP && CPU_V7
1169 Support ARM cpu topology definition. The MPIDR register defines
1170 affinity between processors which is then used to describe the cpu
1171 topology of an ARM System.
1174 bool "Multi-core scheduler support"
1175 depends on ARM_CPU_TOPOLOGY
1177 Multi-core scheduler support improves the CPU scheduler's decision
1178 making when dealing with multi-core CPU chips at a cost of slightly
1179 increased overhead in some places. If unsure say N here.
1182 bool "SMT scheduler support"
1183 depends on ARM_CPU_TOPOLOGY
1185 Improves the CPU scheduler's decision making when dealing with
1186 MultiThreading at a cost of slightly increased overhead in some
1187 places. If unsure say N here.
1192 This option enables support for the ARM snoop control unit
1194 config HAVE_ARM_ARCH_TIMER
1195 bool "Architected timer support"
1197 select ARM_ARCH_TIMER
1199 This option enables support for the ARM architected timer
1204 This options enables support for the ARM timer and watchdog unit
1207 bool "Multi-Cluster Power Management"
1208 depends on CPU_V7 && SMP
1210 This option provides the common power management infrastructure
1211 for (multi-)cluster based systems, such as big.LITTLE based
1214 config MCPM_QUAD_CLUSTER
1218 To avoid wasting resources unnecessarily, MCPM only supports up
1219 to 2 clusters by default.
1220 Platforms with 3 or 4 clusters that use MCPM must select this
1221 option to allow the additional clusters to be managed.
1224 bool "big.LITTLE support (Experimental)"
1225 depends on CPU_V7 && SMP
1228 This option enables support selections for the big.LITTLE
1229 system architecture.
1232 bool "big.LITTLE switcher support"
1233 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1236 The big.LITTLE "switcher" provides the core functionality to
1237 transparently handle transition between a cluster of A15's
1238 and a cluster of A7's in a big.LITTLE system.
1240 config BL_SWITCHER_DUMMY_IF
1241 tristate "Simple big.LITTLE switcher user interface"
1242 depends on BL_SWITCHER && DEBUG_KERNEL
1244 This is a simple and dummy char dev interface to control
1245 the big.LITTLE switcher core code. It is meant for
1246 debugging purposes only.
1249 prompt "Memory split"
1253 Select the desired split between kernel and user memory.
1255 If you are not absolutely sure what you are doing, leave this
1259 bool "3G/1G user/kernel split"
1260 config VMSPLIT_3G_OPT
1261 depends on !ARM_LPAE
1262 bool "3G/1G user/kernel split (for full 1G low memory)"
1264 bool "2G/2G user/kernel split"
1266 bool "1G/3G user/kernel split"
1271 default PHYS_OFFSET if !MMU
1272 default 0x40000000 if VMSPLIT_1G
1273 default 0x80000000 if VMSPLIT_2G
1274 default 0xB0000000 if VMSPLIT_3G_OPT
1277 config KASAN_SHADOW_OFFSET
1280 default 0x1f000000 if PAGE_OFFSET=0x40000000
1281 default 0x5f000000 if PAGE_OFFSET=0x80000000
1282 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1283 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1287 int "Maximum number of CPUs (2-32)"
1288 range 2 16 if DEBUG_KMAP_LOCAL
1289 range 2 32 if !DEBUG_KMAP_LOCAL
1293 The maximum number of CPUs that the kernel can support.
1294 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1295 debugging is enabled, which uses half of the per-CPU fixmap
1296 slots as guard regions.
1299 bool "Support for hot-pluggable CPUs"
1301 select GENERIC_IRQ_MIGRATION
1303 Say Y here to experiment with turning CPUs off and on. CPUs
1304 can be controlled through /sys/devices/system/cpu.
1307 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1308 depends on HAVE_ARM_SMCCC
1311 Say Y here if you want Linux to communicate with system firmware
1312 implementing the PSCI specification for CPU-centric power
1313 management operations described in ARM document number ARM DEN
1314 0022A ("Power State Coordination Interface System Software on
1317 # The GPIO number here must be sorted by descending number. In case of
1318 # a multiplatform kernel, we just want the highest value required by the
1319 # selected platforms.
1322 default 2048 if ARCH_INTEL_SOCFPGA
1323 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1324 ARCH_ZYNQ || ARCH_ASPEED
1325 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1326 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1327 default 416 if ARCH_SUNXI
1328 default 392 if ARCH_U8500
1329 default 352 if ARCH_VT8500
1330 default 288 if ARCH_ROCKCHIP
1331 default 264 if MACH_H4700
1334 Maximum number of GPIOs in the system.
1336 If unsure, leave the default value.
1340 default 128 if SOC_AT91RM9200
1344 depends on HZ_FIXED = 0
1345 prompt "Timer frequency"
1369 default HZ_FIXED if HZ_FIXED != 0
1370 default 100 if HZ_100
1371 default 200 if HZ_200
1372 default 250 if HZ_250
1373 default 300 if HZ_300
1374 default 500 if HZ_500
1378 def_bool HIGH_RES_TIMERS
1380 config THUMB2_KERNEL
1381 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1382 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1383 default y if CPU_THUMBONLY
1386 By enabling this option, the kernel will be compiled in
1391 config ARM_PATCH_IDIV
1392 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1393 depends on CPU_32v7 && !XIP_KERNEL
1396 The ARM compiler inserts calls to __aeabi_idiv() and
1397 __aeabi_uidiv() when it needs to perform division on signed
1398 and unsigned integers. Some v7 CPUs have support for the sdiv
1399 and udiv instructions that can be used to implement those
1402 Enabling this option allows the kernel to modify itself to
1403 replace the first two instructions of these library functions
1404 with the sdiv or udiv plus "bx lr" instructions when the CPU
1405 it is running on supports them. Typically this will be faster
1406 and less power intensive than running the original library
1407 code to do integer division.
1410 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1411 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1412 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1414 This option allows for the kernel to be compiled using the latest
1415 ARM ABI (aka EABI). This is only useful if you are using a user
1416 space environment that is also compiled with EABI.
1418 Since there are major incompatibilities between the legacy ABI and
1419 EABI, especially with regard to structure member alignment, this
1420 option also changes the kernel syscall calling convention to
1421 disambiguate both ABIs and allow for backward compatibility support
1422 (selected with CONFIG_OABI_COMPAT).
1424 To use this you need GCC version 4.0.0 or later.
1427 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1428 depends on AEABI && !THUMB2_KERNEL
1430 This option preserves the old syscall interface along with the
1431 new (ARM EABI) one. It also provides a compatibility layer to
1432 intercept syscalls that have structure arguments which layout
1433 in memory differs between the legacy ABI and the new ARM EABI
1434 (only for non "thumb" binaries). This option adds a tiny
1435 overhead to all syscalls and produces a slightly larger kernel.
1437 The seccomp filter system will not be available when this is
1438 selected, since there is no way yet to sensibly distinguish
1439 between calling conventions during filtering.
1441 If you know you'll be using only pure EABI user space then you
1442 can say N here. If this option is not selected and you attempt
1443 to execute a legacy ABI binary then the result will be
1444 UNPREDICTABLE (in fact it can be predicted that it won't work
1445 at all). If in doubt say N.
1447 config ARCH_SELECT_MEMORY_MODEL
1450 config ARCH_FLATMEM_ENABLE
1453 config ARCH_SPARSEMEM_ENABLE
1455 select SPARSEMEM_STATIC if SPARSEMEM
1458 bool "High Memory Support"
1462 The address space of ARM processors is only 4 Gigabytes large
1463 and it has to accommodate user address space, kernel address
1464 space as well as some memory mapped IO. That means that, if you
1465 have a large amount of physical memory and/or IO, not all of the
1466 memory can be "permanently mapped" by the kernel. The physical
1467 memory that is not permanently mapped is called "high memory".
1469 Depending on the selected kernel/user memory split, minimum
1470 vmalloc space and actual amount of RAM, you may not need this
1471 option which should result in a slightly faster kernel.
1476 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1480 The VM uses one page of physical memory for each page table.
1481 For systems with a lot of processes, this can use a lot of
1482 precious low memory, eventually leading to low memory being
1483 consumed by page tables. Setting this option will allow
1484 user-space 2nd level page tables to reside in high memory.
1486 config CPU_SW_DOMAIN_PAN
1487 bool "Enable use of CPU domains to implement privileged no-access"
1488 depends on MMU && !ARM_LPAE
1491 Increase kernel security by ensuring that normal kernel accesses
1492 are unable to access userspace addresses. This can help prevent
1493 use-after-free bugs becoming an exploitable privilege escalation
1494 by ensuring that magic values (such as LIST_POISON) will always
1495 fault when dereferenced.
1497 CPUs with low-vector mappings use a best-efforts implementation.
1498 Their lower 1MB needs to remain accessible for the vectors, but
1499 the remainder of userspace will become appropriately inaccessible.
1501 config HW_PERF_EVENTS
1505 config ARCH_WANT_GENERAL_HUGETLB
1508 config ARM_MODULE_PLTS
1509 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1513 Allocate PLTs when loading modules so that jumps and calls whose
1514 targets are too far away for their relative offsets to be encoded
1515 in the instructions themselves can be bounced via veneers in the
1516 module's PLT. This allows modules to be allocated in the generic
1517 vmalloc area after the dedicated module memory area has been
1518 exhausted. The modules will use slightly more memory, but after
1519 rounding up to page size, the actual memory footprint is usually
1522 Disabling this is usually safe for small single-platform
1523 configurations. If unsure, say y.
1525 config FORCE_MAX_ZONEORDER
1526 int "Maximum zone order"
1527 default "12" if SOC_AM33XX
1528 default "9" if SA1111
1531 The kernel memory allocator divides physically contiguous memory
1532 blocks into "zones", where each zone is a power of two number of
1533 pages. This option selects the largest power of two that the kernel
1534 keeps in the memory allocator. If you need to allocate very large
1535 blocks of physically contiguous memory, then you may need to
1536 increase this value.
1538 This config option is actually maximum order plus one. For example,
1539 a value of 11 means that the largest free memory block is 2^10 pages.
1541 config ALIGNMENT_TRAP
1542 def_bool CPU_CP15_MMU
1543 select HAVE_PROC_CPU if PROC_FS
1545 ARM processors cannot fetch/store information which is not
1546 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1547 address divisible by 4. On 32-bit ARM processors, these non-aligned
1548 fetch/store instructions will be emulated in software if you say
1549 here, which has a severe performance impact. This is necessary for
1550 correct operation of some network protocols. With an IP-only
1551 configuration it is safe to say N, otherwise say Y.
1553 config UACCESS_WITH_MEMCPY
1554 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1556 default y if CPU_FEROCEON
1558 Implement faster copy_to_user and clear_user methods for CPU
1559 cores where a 8-word STM instruction give significantly higher
1560 memory write throughput than a sequence of individual 32bit stores.
1562 A possible side effect is a slight increase in scheduling latency
1563 between threads sharing the same address space if they invoke
1564 such copy operations with large buffers.
1566 However, if the CPU data cache is using a write-allocate mode,
1567 this option is unlikely to provide any performance gain.
1570 bool "Enable paravirtualization code"
1572 This changes the kernel so it can modify itself when it is run
1573 under a hypervisor, potentially improving performance significantly
1574 over full virtualization.
1576 config PARAVIRT_TIME_ACCOUNTING
1577 bool "Paravirtual steal time accounting"
1580 Select this option to enable fine granularity task steal time
1581 accounting. Time spent executing other tasks in parallel with
1582 the current vCPU is discounted from the vCPU power. To account for
1583 that, there can be a small performance impact.
1585 If in doubt, say N here.
1592 bool "Xen guest support on ARM"
1593 depends on ARM && AEABI && OF
1594 depends on CPU_V7 && !CPU_V6
1595 depends on !GENERIC_ATOMIC64
1597 select ARCH_DMA_ADDR_T_64BIT
1603 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1605 config STACKPROTECTOR_PER_TASK
1606 bool "Use a unique stack canary value for each task"
1607 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1608 select GCC_PLUGIN_ARM_SSP_PER_TASK
1611 Due to the fact that GCC uses an ordinary symbol reference from
1612 which to load the value of the stack canary, this value can only
1613 change at reboot time on SMP systems, and all tasks running in the
1614 kernel's address space are forced to use the same canary value for
1615 the entire duration that the system is up.
1617 Enable this option to switch to a different method that uses a
1618 different canary value for each task.
1625 bool "Flattened Device Tree support"
1629 Include support for flattened device tree machine descriptions.
1632 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1635 This is the traditional way of passing data to the kernel at boot
1636 time. If you are solely relying on the flattened device tree (or
1637 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1638 to remove ATAGS support from your kernel binary. If unsure,
1641 config DEPRECATED_PARAM_STRUCT
1642 bool "Provide old way to pass kernel parameters"
1645 This was deprecated in 2001 and announced to live on for 5 years.
1646 Some old boot loaders still use this way.
1648 # Compressed boot loader in ROM. Yes, we really want to ask about
1649 # TEXT and BSS so we preserve their values in the config files.
1650 config ZBOOT_ROM_TEXT
1651 hex "Compressed ROM boot loader base address"
1654 The physical address at which the ROM-able zImage is to be
1655 placed in the target. Platforms which normally make use of
1656 ROM-able zImage formats normally set this to a suitable
1657 value in their defconfig file.
1659 If ZBOOT_ROM is not enabled, this has no effect.
1661 config ZBOOT_ROM_BSS
1662 hex "Compressed ROM boot loader BSS address"
1665 The base address of an area of read/write memory in the target
1666 for the ROM-able zImage which must be available while the
1667 decompressor is running. It must be large enough to hold the
1668 entire decompressed kernel plus an additional 128 KiB.
1669 Platforms which normally make use of ROM-able zImage formats
1670 normally set this to a suitable value in their defconfig file.
1672 If ZBOOT_ROM is not enabled, this has no effect.
1675 bool "Compressed boot loader in ROM/flash"
1676 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1677 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1679 Say Y here if you intend to execute your compressed kernel image
1680 (zImage) directly from ROM or flash. If unsure, say N.
1682 config ARM_APPENDED_DTB
1683 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1686 With this option, the boot code will look for a device tree binary
1687 (DTB) appended to zImage
1688 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1690 This is meant as a backward compatibility convenience for those
1691 systems with a bootloader that can't be upgraded to accommodate
1692 the documented boot protocol using a device tree.
1694 Beware that there is very little in terms of protection against
1695 this option being confused by leftover garbage in memory that might
1696 look like a DTB header after a reboot if no actual DTB is appended
1697 to zImage. Do not leave this option active in a production kernel
1698 if you don't intend to always append a DTB. Proper passing of the
1699 location into r2 of a bootloader provided DTB is always preferable
1702 config ARM_ATAG_DTB_COMPAT
1703 bool "Supplement the appended DTB with traditional ATAG information"
1704 depends on ARM_APPENDED_DTB
1706 Some old bootloaders can't be updated to a DTB capable one, yet
1707 they provide ATAGs with memory configuration, the ramdisk address,
1708 the kernel cmdline string, etc. Such information is dynamically
1709 provided by the bootloader and can't always be stored in a static
1710 DTB. To allow a device tree enabled kernel to be used with such
1711 bootloaders, this option allows zImage to extract the information
1712 from the ATAG list and store it at run time into the appended DTB.
1715 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1716 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1718 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1719 bool "Use bootloader kernel arguments if available"
1721 Uses the command-line options passed by the boot loader instead of
1722 the device tree bootargs property. If the boot loader doesn't provide
1723 any, the device tree bootargs property will be used.
1725 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1726 bool "Extend with bootloader kernel arguments"
1728 The command-line arguments provided by the boot loader will be
1729 appended to the the device tree bootargs property.
1734 string "Default kernel command string"
1737 On some architectures (e.g. CATS), there is currently no way
1738 for the boot loader to pass arguments to the kernel. For these
1739 architectures, you should supply some command-line options at build
1740 time by entering them here. As a minimum, you should specify the
1741 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1744 prompt "Kernel command line type" if CMDLINE != ""
1745 default CMDLINE_FROM_BOOTLOADER
1748 config CMDLINE_FROM_BOOTLOADER
1749 bool "Use bootloader kernel arguments if available"
1751 Uses the command-line options passed by the boot loader. If
1752 the boot loader doesn't provide any, the default kernel command
1753 string provided in CMDLINE will be used.
1755 config CMDLINE_EXTEND
1756 bool "Extend bootloader kernel arguments"
1758 The command-line arguments provided by the boot loader will be
1759 appended to the default kernel command string.
1761 config CMDLINE_FORCE
1762 bool "Always use the default kernel command string"
1764 Always use the default kernel command string, even if the boot
1765 loader passes other arguments to the kernel.
1766 This is useful if you cannot or don't want to change the
1767 command-line options your boot loader passes to the kernel.
1771 bool "Kernel Execute-In-Place from ROM"
1772 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1774 Execute-In-Place allows the kernel to run from non-volatile storage
1775 directly addressable by the CPU, such as NOR flash. This saves RAM
1776 space since the text section of the kernel is not loaded from flash
1777 to RAM. Read-write sections, such as the data section and stack,
1778 are still copied to RAM. The XIP kernel is not compressed since
1779 it has to run directly from flash, so it will take more space to
1780 store it. The flash address used to link the kernel object files,
1781 and for storing it, is configuration dependent. Therefore, if you
1782 say Y here, you must know the proper physical address where to
1783 store the kernel image depending on your own flash memory usage.
1785 Also note that the make target becomes "make xipImage" rather than
1786 "make zImage" or "make Image". The final kernel binary to put in
1787 ROM memory will be arch/arm/boot/xipImage.
1791 config XIP_PHYS_ADDR
1792 hex "XIP Kernel Physical Location"
1793 depends on XIP_KERNEL
1794 default "0x00080000"
1796 This is the physical address in your flash memory the kernel will
1797 be linked for and stored to. This address is dependent on your
1800 config XIP_DEFLATED_DATA
1801 bool "Store kernel .data section compressed in ROM"
1802 depends on XIP_KERNEL
1805 Before the kernel is actually executed, its .data section has to be
1806 copied to RAM from ROM. This option allows for storing that data
1807 in compressed form and decompressed to RAM rather than merely being
1808 copied, saving some precious ROM space. A possible drawback is a
1809 slightly longer boot delay.
1812 bool "Kexec system call (EXPERIMENTAL)"
1813 depends on (!SMP || PM_SLEEP_SMP)
1817 kexec is a system call that implements the ability to shutdown your
1818 current kernel, and to start another kernel. It is like a reboot
1819 but it is independent of the system firmware. And like a reboot
1820 you can start any kernel with it, not just Linux.
1822 It is an ongoing process to be certain the hardware in a machine
1823 is properly shutdown, so do not be surprised if this code does not
1824 initially work for you.
1827 bool "Export atags in procfs"
1828 depends on ATAGS && KEXEC
1831 Should the atags used to boot the kernel be exported in an "atags"
1832 file in procfs. Useful with kexec.
1835 bool "Build kdump crash kernel (EXPERIMENTAL)"
1837 Generate crash dump after being started by kexec. This should
1838 be normally only set in special crash dump kernels which are
1839 loaded in the main kernel with kexec-tools into a specially
1840 reserved region and then later executed after a crash by
1841 kdump/kexec. The crash dump kernel must be compiled to a
1842 memory address not used by the main kernel
1844 For more details see Documentation/admin-guide/kdump/kdump.rst
1846 config AUTO_ZRELADDR
1847 bool "Auto calculation of the decompressed kernel image address"
1849 ZRELADDR is the physical address where the decompressed kernel
1850 image will be placed. If AUTO_ZRELADDR is selected, the address
1851 will be determined at run-time, either by masking the current IP
1852 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1853 This assumes the zImage being placed in the first 128MB from
1860 bool "UEFI runtime support"
1861 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1863 select EFI_PARAMS_FROM_FDT
1865 select EFI_GENERIC_STUB
1866 select EFI_RUNTIME_WRAPPERS
1868 This option provides support for runtime services provided
1869 by UEFI firmware (such as non-volatile variables, realtime
1870 clock, and platform reset). A UEFI stub is also provided to
1871 allow the kernel to be booted as an EFI application. This
1872 is only useful for kernels that may run on systems that have
1876 bool "Enable support for SMBIOS (DMI) tables"
1880 This enables SMBIOS/DMI feature for systems.
1882 This option is only useful on systems that have UEFI firmware.
1883 However, even with this option, the resultant kernel should
1884 continue to boot on existing non-UEFI platforms.
1886 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1887 i.e., the the practice of identifying the platform via DMI to
1888 decide whether certain workarounds for buggy hardware and/or
1889 firmware need to be enabled. This would require the DMI subsystem
1890 to be enabled much earlier than we do on ARM, which is non-trivial.
1894 menu "CPU Power Management"
1896 source "drivers/cpufreq/Kconfig"
1898 source "drivers/cpuidle/Kconfig"
1902 menu "Floating point emulation"
1904 comment "At least one emulation must be selected"
1907 bool "NWFPE math emulation"
1908 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1910 Say Y to include the NWFPE floating point emulator in the kernel.
1911 This is necessary to run most binaries. Linux does not currently
1912 support floating point hardware so you need to say Y here even if
1913 your machine has an FPA or floating point co-processor podule.
1915 You may say N here if you are going to load the Acorn FPEmulator
1916 early in the bootup.
1919 bool "Support extended precision"
1920 depends on FPE_NWFPE
1922 Say Y to include 80-bit support in the kernel floating-point
1923 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1924 Note that gcc does not generate 80-bit operations by default,
1925 so in most cases this option only enlarges the size of the
1926 floating point emulator without any good reason.
1928 You almost surely want to say N here.
1931 bool "FastFPE math emulation (EXPERIMENTAL)"
1932 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1934 Say Y here to include the FAST floating point emulator in the kernel.
1935 This is an experimental much faster emulator which now also has full
1936 precision for the mantissa. It does not support any exceptions.
1937 It is very simple, and approximately 3-6 times faster than NWFPE.
1939 It should be sufficient for most programs. It may be not suitable
1940 for scientific calculations, but you have to check this for yourself.
1941 If you do not feel you need a faster FP emulation you should better
1945 bool "VFP-format floating point maths"
1946 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1948 Say Y to include VFP support code in the kernel. This is needed
1949 if your hardware includes a VFP unit.
1951 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1952 release notes and additional status information.
1954 Say N if your target does not have VFP hardware.
1962 bool "Advanced SIMD (NEON) Extension support"
1963 depends on VFPv3 && CPU_V7
1965 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1968 config KERNEL_MODE_NEON
1969 bool "Support for NEON in kernel mode"
1970 depends on NEON && AEABI
1972 Say Y to include support for NEON in kernel mode.
1976 menu "Power management options"
1978 source "kernel/power/Kconfig"
1980 config ARCH_SUSPEND_POSSIBLE
1981 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1982 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1985 config ARM_CPU_SUSPEND
1986 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1987 depends on ARCH_SUSPEND_POSSIBLE
1989 config ARCH_HIBERNATION_POSSIBLE
1992 default y if ARCH_SUSPEND_POSSIBLE
1996 source "drivers/firmware/Kconfig"
1999 source "arch/arm/crypto/Kconfig"
2002 source "arch/arm/Kconfig.assembler"