arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_USE_CMPXCHG_LOCKREF
   9         select ARCH_WANT_IPC_PARSE_VERSION
  10         select BUILDTIME_EXTABLE_SORT if MMU
  11         select CLONE_BACKWARDS
  12         select CPU_PM if (SUSPEND || CPU_IDLE)
  13         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
  14         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  15         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  16         select GENERIC_IDLE_POLL_SETUP
  17         select GENERIC_IRQ_PROBE
  18         select GENERIC_IRQ_SHOW
  19         select GENERIC_PCI_IOMAP
  20         select GENERIC_SCHED_CLOCK
  21         select GENERIC_SMP_IDLE_THREAD
  22         select GENERIC_STRNCPY_FROM_USER
  23         select GENERIC_STRNLEN_USER
  24         select HARDIRQS_SW_RESEND
  25         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  26         select HAVE_ARCH_KGDB
  27         select HAVE_ARCH_SECCOMP_FILTER
  28         select HAVE_ARCH_TRACEHOOK
  29         select HAVE_BPF_JIT
  30         select HAVE_CONTEXT_TRACKING
  31         select HAVE_C_RECORDMCOUNT
  32         select HAVE_DEBUG_KMEMLEAK
  33         select HAVE_DMA_API_DEBUG
  34         select HAVE_DMA_ATTRS
  35         select HAVE_DMA_CONTIGUOUS if MMU
  36         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  37         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  38         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  39         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  40         select HAVE_GENERIC_DMA_COHERENT
  41         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  42         select HAVE_IDE if PCI || ISA || PCMCIA
  43         select HAVE_IRQ_TIME_ACCOUNTING
  44         select HAVE_KERNEL_GZIP
  45         select HAVE_KERNEL_LZ4
  46         select HAVE_KERNEL_LZMA
  47         select HAVE_KERNEL_LZO
  48         select HAVE_KERNEL_XZ
  49         select HAVE_KPROBES if !XIP_KERNEL
  50         select HAVE_KRETPROBES if (HAVE_KPROBES)
  51         select HAVE_MEMBLOCK
  52         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  53         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  54         select HAVE_PERF_EVENTS
  55         select HAVE_PERF_REGS
  56         select HAVE_PERF_USER_STACK_DUMP
  57         select HAVE_REGS_AND_STACK_ACCESS_API
  58         select HAVE_SYSCALL_TRACEPOINTS
  59         select HAVE_UID16
  60         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  61         select IRQ_FORCED_THREADING
  62         select KTIME_SCALAR
  63         select MODULES_USE_ELF_REL
  64         select OLD_SIGACTION
  65         select OLD_SIGSUSPEND3
  66         select PERF_USE_VMALLOC
  67         select RTC_LIB
  68         select SYS_SUPPORTS_APM_EMULATION
  69         # Above selects are sorted alphabetically; please add new ones
  70         # according to that.  Thanks.
  71         help
  72           The ARM series is a line of low-power-consumption RISC chip designs
  73           licensed by ARM Ltd and targeted at embedded applications and
  74           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  75           manufactured, but legacy ARM-based PC hardware remains popular in
  76           Europe.  There is an ARM Linux project with a web page at
  77           <http://www.arm.linux.org.uk/>.
  78
  79 config ARM_HAS_SG_CHAIN
  80         bool
  81
  82 config NEED_SG_DMA_LENGTH
  83         bool
  84
  85 config ARM_DMA_USE_IOMMU
  86         bool
  87         select ARM_HAS_SG_CHAIN
  88         select NEED_SG_DMA_LENGTH
  89
  90 if ARM_DMA_USE_IOMMU
  91
  92 config ARM_DMA_IOMMU_ALIGNMENT
  93         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  94         range 4 9
  95         default 8
  96         help
  97           DMA mapping framework by default aligns all buffers to the smallest
  98           PAGE_SIZE order which is greater than or equal to the requested buffer
  99           size. This works well for buffers up to a few hundreds kilobytes, but
 100           for larger buffers it just a waste of address space. Drivers which has
 101           relatively small addressing window (like 64Mib) might run out of
 102           virtual space with just a few allocations.
 103
 104           With this parameter you can specify the maximum PAGE_SIZE order for
 105           DMA IOMMU buffers. Larger buffers will be aligned only to this
 106           specified order. The order is expressed as a power of two multiplied
 107           by the PAGE_SIZE.
 108
 109 endif
 110
 111 config HAVE_PWM
 112         bool
 113
 114 config MIGHT_HAVE_PCI
 115         bool
 116
 117 config SYS_SUPPORTS_APM_EMULATION
 118         bool
 119
 120 config HAVE_TCM
 121         bool
 122         select GENERIC_ALLOCATOR
 123
 124 config HAVE_PROC_CPU
 125         bool
 126
 127 config NO_IOPORT
 128         bool
 129
 130 config EISA
 131         bool
 132         ---help---
 133           The Extended Industry Standard Architecture (EISA) bus was
 134           developed as an open alternative to the IBM MicroChannel bus.
 135
 136           The EISA bus provided some of the features of the IBM MicroChannel
 137           bus while maintaining backward compatibility with cards made for
 138           the older ISA bus.  The EISA bus saw limited use between 1988 and
 139           1995 when it was made obsolete by the PCI bus.
 140
 141           Say Y here if you are building a kernel for an EISA-based machine.
 142
 143           Otherwise, say N.
 144
 145 config SBUS
 146         bool
 147
 148 config STACKTRACE_SUPPORT
 149         bool
 150         default y
 151
 152 config HAVE_LATENCYTOP_SUPPORT
 153         bool
 154         depends on !SMP
 155         default y
 156
 157 config LOCKDEP_SUPPORT
 158         bool
 159         default y
 160
 161 config TRACE_IRQFLAGS_SUPPORT
 162         bool
 163         default y
 164
 165 config RWSEM_GENERIC_SPINLOCK
 166         bool
 167         default y
 168
 169 config RWSEM_XCHGADD_ALGORITHM
 170         bool
 171
 172 config ARCH_HAS_ILOG2_U32
 173         bool
 174
 175 config ARCH_HAS_ILOG2_U64
 176         bool
 177
 178 config ARCH_HAS_CPUFREQ
 179         bool
 180         help
 181           Internal node to signify that the ARCH has CPUFREQ support
 182           and that the relevant menu configurations are displayed for
 183           it.
 184
 185 config ARCH_HAS_BANDGAP
 186         bool
 187
 188 config GENERIC_HWEIGHT
 189         bool
 190         default y
 191
 192 config GENERIC_CALIBRATE_DELAY
 193         bool
 194         default y
 195
 196 config ARCH_MAY_HAVE_PC_FDC
 197         bool
 198
 199 config ZONE_DMA
 200         bool
 201
 202 config NEED_DMA_MAP_STATE
 203        def_bool y
 204
 205 config ARCH_HAS_DMA_SET_COHERENT_MASK
 206         bool
 207
 208 config GENERIC_ISA_DMA
 209         bool
 210
 211 config FIQ
 212         bool
 213
 214 config NEED_RET_TO_USER
 215         bool
 216
 217 config ARCH_MTD_XIP
 218         bool
 219
 220 config VECTORS_BASE
 221         hex
 222         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 223         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 224         default 0x00000000
 225         help
 226           The base address of exception vectors.  This must be two pages
 227           in size.
 228
 229 config ARM_PATCH_PHYS_VIRT
 230         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 231         default y
 232         depends on !XIP_KERNEL && MMU
 233         depends on !ARCH_REALVIEW || !SPARSEMEM
 234         help
 235           Patch phys-to-virt and virt-to-phys translation functions at
 236           boot and module load time according to the position of the
 237           kernel in system memory.
 238
 239           This can only be used with non-XIP MMU kernels where the base
 240           of physical memory is at a 16MB boundary.
 241
 242           Only disable this option if you know that you do not require
 243           this feature (eg, building a kernel for a single machine) and
 244           you need to shrink the kernel to the minimal size.
 245
 246 config NEED_MACH_GPIO_H
 247         bool
 248         help
 249           Select this when mach/gpio.h is required to provide special
 250           definitions for this platform. The need for mach/gpio.h should
 251           be avoided when possible.
 252
 253 config NEED_MACH_IO_H
 254         bool
 255         help
 256           Select this when mach/io.h is required to provide special
 257           definitions for this platform.  The need for mach/io.h should
 258           be avoided when possible.
 259
 260 config NEED_MACH_MEMORY_H
 261         bool
 262         help
 263           Select this when mach/memory.h is required to provide special
 264           definitions for this platform.  The need for mach/memory.h should
 265           be avoided when possible.
 266
 267 config PHYS_OFFSET
 268         hex "Physical address of main memory" if MMU
 269         depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
 270         default DRAM_BASE if !MMU
 271         help
 272           Please provide the physical address corresponding to the
 273           location of main memory in your system.
 274
 275 config GENERIC_BUG
 276         def_bool y
 277         depends on BUG
 278
 279 source "init/Kconfig"
 280
 281 source "kernel/Kconfig.freezer"
 282
 283 menu "System Type"
 284
 285 config MMU
 286         bool "MMU-based Paged Memory Management Support"
 287         default y
 288         help
 289           Select if you want MMU-based virtualised addressing space
 290           support by paged memory management. If unsure, say 'Y'.
 291
 292 #
 293 # The "ARM system type" choice list is ordered alphabetically by option
 294 # text.  Please add new entries in the option alphabetic order.
 295 #
 296 choice
 297         prompt "ARM system type"
 298         default ARCH_VERSATILE if !MMU
 299         default ARCH_MULTIPLATFORM if MMU
 300
 301 config ARCH_MULTIPLATFORM
 302         bool "Allow multiple platforms to be selected"
 303         depends on MMU
 304         select ARM_PATCH_PHYS_VIRT
 305         select AUTO_ZRELADDR
 306         select COMMON_CLK
 307         select MULTI_IRQ_HANDLER
 308         select SPARSE_IRQ
 309         select USE_OF
 310
 311 config ARCH_INTEGRATOR
 312         bool "ARM Ltd. Integrator family"
 313         select ARCH_HAS_CPUFREQ
 314         select ARM_AMBA
 315         select COMMON_CLK
 316         select COMMON_CLK_VERSATILE
 317         select GENERIC_CLOCKEVENTS
 318         select HAVE_TCM
 319         select ICST
 320         select MULTI_IRQ_HANDLER
 321         select NEED_MACH_MEMORY_H
 322         select PLAT_VERSATILE
 323         select SPARSE_IRQ
 324         select USE_OF
 325         select VERSATILE_FPGA_IRQ
 326         help
 327           Support for ARM's Integrator platform.
 328
 329 config ARCH_REALVIEW
 330         bool "ARM Ltd. RealView family"
 331         select ARCH_WANT_OPTIONAL_GPIOLIB
 332         select ARM_AMBA
 333         select ARM_TIMER_SP804
 334         select COMMON_CLK
 335         select COMMON_CLK_VERSATILE
 336         select GENERIC_CLOCKEVENTS
 337         select GPIO_PL061 if GPIOLIB
 338         select ICST
 339         select NEED_MACH_MEMORY_H
 340         select PLAT_VERSATILE
 341         select PLAT_VERSATILE_CLCD
 342         help
 343           This enables support for ARM Ltd RealView boards.
 344
 345 config ARCH_VERSATILE
 346         bool "ARM Ltd. Versatile family"
 347         select ARCH_WANT_OPTIONAL_GPIOLIB
 348         select ARM_AMBA
 349         select ARM_TIMER_SP804
 350         select ARM_VIC
 351         select CLKDEV_LOOKUP
 352         select GENERIC_CLOCKEVENTS
 353         select HAVE_MACH_CLKDEV
 354         select ICST
 355         select PLAT_VERSATILE
 356         select PLAT_VERSATILE_CLCD
 357         select PLAT_VERSATILE_CLOCK
 358         select VERSATILE_FPGA_IRQ
 359         help
 360           This enables support for ARM Ltd Versatile board.
 361
 362 config ARCH_AT91
 363         bool "Atmel AT91"
 364         select ARCH_REQUIRE_GPIOLIB
 365         select CLKDEV_LOOKUP
 366         select IRQ_DOMAIN
 367         select NEED_MACH_GPIO_H
 368         select NEED_MACH_IO_H if PCCARD
 369         select PINCTRL
 370         select PINCTRL_AT91 if USE_OF
 371         help
 372           This enables support for systems based on Atmel
 373           AT91RM9200 and AT91SAM9* processors.
 374
 375 config ARCH_CLPS711X
 376         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 377         select ARCH_REQUIRE_GPIOLIB
 378         select AUTO_ZRELADDR
 379         select CLKSRC_MMIO
 380         select COMMON_CLK
 381         select CPU_ARM720T
 382         select GENERIC_CLOCKEVENTS
 383         select MFD_SYSCON
 384         select MULTI_IRQ_HANDLER
 385         select SPARSE_IRQ
 386         help
 387           Support for Cirrus Logic 711x/721x/731x based boards.
 388
 389 config ARCH_GEMINI
 390         bool "Cortina Systems Gemini"
 391         select ARCH_REQUIRE_GPIOLIB
 392         select CLKSRC_MMIO
 393         select CPU_FA526
 394         select GENERIC_CLOCKEVENTS
 395         help
 396           Support for the Cortina Systems Gemini family SoCs
 397
 398 config ARCH_EBSA110
 399         bool "EBSA-110"
 400         select ARCH_USES_GETTIMEOFFSET
 401         select CPU_SA110
 402         select ISA
 403         select NEED_MACH_IO_H
 404         select NEED_MACH_MEMORY_H
 405         select NO_IOPORT
 406         help
 407           This is an evaluation board for the StrongARM processor available
 408           from Digital. It has limited hardware on-board, including an
 409           Ethernet interface, two PCMCIA sockets, two serial ports and a
 410           parallel port.
 411
 412 config ARCH_EP93XX
 413         bool "EP93xx-based"
 414         select ARCH_HAS_HOLES_MEMORYMODEL
 415         select ARCH_REQUIRE_GPIOLIB
 416         select ARCH_USES_GETTIMEOFFSET
 417         select ARM_AMBA
 418         select ARM_VIC
 419         select CLKDEV_LOOKUP
 420         select CPU_ARM920T
 421         select NEED_MACH_MEMORY_H
 422         help
 423           This enables support for the Cirrus EP93xx series of CPUs.
 424
 425 config ARCH_FOOTBRIDGE
 426         bool "FootBridge"
 427         select CPU_SA110
 428         select FOOTBRIDGE
 429         select GENERIC_CLOCKEVENTS
 430         select HAVE_IDE
 431         select NEED_MACH_IO_H if !MMU
 432         select NEED_MACH_MEMORY_H
 433         help
 434           Support for systems based on the DC21285 companion chip
 435           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 436
 437 config ARCH_NETX
 438         bool "Hilscher NetX based"
 439         select ARM_VIC
 440         select CLKSRC_MMIO
 441         select CPU_ARM926T
 442         select GENERIC_CLOCKEVENTS
 443         help
 444           This enables support for systems based on the Hilscher NetX Soc
 445
 446 config ARCH_IOP13XX
 447         bool "IOP13xx-based"
 448         depends on MMU
 449         select CPU_XSC3
 450         select NEED_MACH_MEMORY_H
 451         select NEED_RET_TO_USER
 452         select PCI
 453         select PLAT_IOP
 454         select VMSPLIT_1G
 455         help
 456           Support for Intel's IOP13XX (XScale) family of processors.
 457
 458 config ARCH_IOP32X
 459         bool "IOP32x-based"
 460         depends on MMU
 461         select ARCH_REQUIRE_GPIOLIB
 462         select CPU_XSCALE
 463         select GPIO_IOP
 464         select NEED_RET_TO_USER
 465         select PCI
 466         select PLAT_IOP
 467         help
 468           Support for Intel's 80219 and IOP32X (XScale) family of
 469           processors.
 470
 471 config ARCH_IOP33X
 472         bool "IOP33x-based"
 473         depends on MMU
 474         select ARCH_REQUIRE_GPIOLIB
 475         select CPU_XSCALE
 476         select GPIO_IOP
 477         select NEED_RET_TO_USER
 478         select PCI
 479         select PLAT_IOP
 480         help
 481           Support for Intel's IOP33X (XScale) family of processors.
 482
 483 config ARCH_IXP4XX
 484         bool "IXP4xx-based"
 485         depends on MMU
 486         select ARCH_HAS_DMA_SET_COHERENT_MASK
 487         select ARCH_SUPPORTS_BIG_ENDIAN
 488         select ARCH_REQUIRE_GPIOLIB
 489         select CLKSRC_MMIO
 490         select CPU_XSCALE
 491         select DMABOUNCE if PCI
 492         select GENERIC_CLOCKEVENTS
 493         select MIGHT_HAVE_PCI
 494         select NEED_MACH_IO_H
 495         select USB_EHCI_BIG_ENDIAN_DESC
 496         select USB_EHCI_BIG_ENDIAN_MMIO
 497         help
 498           Support for Intel's IXP4XX (XScale) family of processors.
 499
 500 config ARCH_DOVE
 501         bool "Marvell Dove"
 502         select ARCH_REQUIRE_GPIOLIB
 503         select CPU_PJ4
 504         select GENERIC_CLOCKEVENTS
 505         select MIGHT_HAVE_PCI
 506         select MVEBU_MBUS
 507         select PINCTRL
 508         select PINCTRL_DOVE
 509         select PLAT_ORION_LEGACY
 510         select USB_ARCH_HAS_EHCI
 511         help
 512           Support for the Marvell Dove SoC 88AP510
 513
 514 config ARCH_KIRKWOOD
 515         bool "Marvell Kirkwood"
 516         select ARCH_HAS_CPUFREQ
 517         select ARCH_REQUIRE_GPIOLIB
 518         select CPU_FEROCEON
 519         select GENERIC_CLOCKEVENTS
 520         select MVEBU_MBUS
 521         select PCI
 522         select PCI_QUIRKS
 523         select PINCTRL
 524         select PINCTRL_KIRKWOOD
 525         select PLAT_ORION_LEGACY
 526         help
 527           Support for the following Marvell Kirkwood series SoCs:
 528           88F6180, 88F6192 and 88F6281.
 529
 530 config ARCH_MV78XX0
 531         bool "Marvell MV78xx0"
 532         select ARCH_REQUIRE_GPIOLIB
 533         select CPU_FEROCEON
 534         select GENERIC_CLOCKEVENTS
 535         select MVEBU_MBUS
 536         select PCI
 537         select PLAT_ORION_LEGACY
 538         help
 539           Support for the following Marvell MV78xx0 series SoCs:
 540           MV781x0, MV782x0.
 541
 542 config ARCH_ORION5X
 543         bool "Marvell Orion"
 544         depends on MMU
 545         select ARCH_REQUIRE_GPIOLIB
 546         select CPU_FEROCEON
 547         select GENERIC_CLOCKEVENTS
 548         select MVEBU_MBUS
 549         select PCI
 550         select PLAT_ORION_LEGACY
 551         help
 552           Support for the following Marvell Orion 5x series SoCs:
 553           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 554           Orion-2 (5281), Orion-1-90 (6183).
 555
 556 config ARCH_MMP
 557         bool "Marvell PXA168/910/MMP2"
 558         depends on MMU
 559         select ARCH_REQUIRE_GPIOLIB
 560         select CLKDEV_LOOKUP
 561         select GENERIC_ALLOCATOR
 562         select GENERIC_CLOCKEVENTS
 563         select GPIO_PXA
 564         select IRQ_DOMAIN
 565         select MULTI_IRQ_HANDLER
 566         select PINCTRL
 567         select PLAT_PXA
 568         select SPARSE_IRQ
 569         help
 570           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 571
 572 config ARCH_KS8695
 573         bool "Micrel/Kendin KS8695"
 574         select ARCH_REQUIRE_GPIOLIB
 575         select CLKSRC_MMIO
 576         select CPU_ARM922T
 577         select GENERIC_CLOCKEVENTS
 578         select NEED_MACH_MEMORY_H
 579         help
 580           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 581           System-on-Chip devices.
 582
 583 config ARCH_W90X900
 584         bool "Nuvoton W90X900 CPU"
 585         select ARCH_REQUIRE_GPIOLIB
 586         select CLKDEV_LOOKUP
 587         select CLKSRC_MMIO
 588         select CPU_ARM926T
 589         select GENERIC_CLOCKEVENTS
 590         help
 591           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 592           At present, the w90x900 has been renamed nuc900, regarding
 593           the ARM series product line, you can login the following
 594           link address to know more.
 595
 596           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 597                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 598
 599 config ARCH_LPC32XX
 600         bool "NXP LPC32XX"
 601         select ARCH_REQUIRE_GPIOLIB
 602         select ARM_AMBA
 603         select CLKDEV_LOOKUP
 604         select CLKSRC_MMIO
 605         select CPU_ARM926T
 606         select GENERIC_CLOCKEVENTS
 607         select HAVE_IDE
 608         select HAVE_PWM
 609         select USB_ARCH_HAS_OHCI
 610         select USE_OF
 611         help
 612           Support for the NXP LPC32XX family of processors
 613
 614 config ARCH_PXA
 615         bool "PXA2xx/PXA3xx-based"
 616         depends on MMU
 617         select ARCH_HAS_CPUFREQ
 618         select ARCH_MTD_XIP
 619         select ARCH_REQUIRE_GPIOLIB
 620         select ARM_CPU_SUSPEND if PM
 621         select AUTO_ZRELADDR
 622         select CLKDEV_LOOKUP
 623         select CLKSRC_MMIO
 624         select GENERIC_CLOCKEVENTS
 625         select GPIO_PXA
 626         select HAVE_IDE
 627         select MULTI_IRQ_HANDLER
 628         select PLAT_PXA
 629         select SPARSE_IRQ
 630         help
 631           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 632
 633 config ARCH_MSM
 634         bool "Qualcomm MSM"
 635         select ARCH_REQUIRE_GPIOLIB
 636         select CLKSRC_OF if OF
 637         select COMMON_CLK
 638         select GENERIC_CLOCKEVENTS
 639         help
 640           Support for Qualcomm MSM/QSD based systems.  This runs on the
 641           apps processor of the MSM/QSD and depends on a shared memory
 642           interface to the modem processor which runs the baseband
 643           stack and controls some vital subsystems
 644           (clock and power control, etc).
 645
 646 config ARCH_SHMOBILE
 647         bool "Renesas SH-Mobile / R-Mobile"
 648         select ARM_PATCH_PHYS_VIRT
 649         select CLKDEV_LOOKUP
 650         select GENERIC_CLOCKEVENTS
 651         select HAVE_ARM_SCU if SMP
 652         select HAVE_ARM_TWD if SMP
 653         select HAVE_MACH_CLKDEV
 654         select HAVE_SMP
 655         select MIGHT_HAVE_CACHE_L2X0
 656         select MULTI_IRQ_HANDLER
 657         select NO_IOPORT
 658         select PINCTRL
 659         select PM_GENERIC_DOMAINS if PM
 660         select SPARSE_IRQ
 661         help
 662           Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 663
 664 config ARCH_RPC
 665         bool "RiscPC"
 666         select ARCH_ACORN
 667         select ARCH_MAY_HAVE_PC_FDC
 668         select ARCH_SPARSEMEM_ENABLE
 669         select ARCH_USES_GETTIMEOFFSET
 670         select FIQ
 671         select HAVE_IDE
 672         select HAVE_PATA_PLATFORM
 673         select ISA_DMA_API
 674         select NEED_MACH_IO_H
 675         select NEED_MACH_MEMORY_H
 676         select NO_IOPORT
 677         select VIRT_TO_BUS
 678         help
 679           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 680           CD-ROM interface, serial and parallel port, and the floppy drive.
 681
 682 config ARCH_SA1100
 683         bool "SA1100-based"
 684         select ARCH_HAS_CPUFREQ
 685         select ARCH_MTD_XIP
 686         select ARCH_REQUIRE_GPIOLIB
 687         select ARCH_SPARSEMEM_ENABLE
 688         select CLKDEV_LOOKUP
 689         select CLKSRC_MMIO
 690         select CPU_FREQ
 691         select CPU_SA1100
 692         select GENERIC_CLOCKEVENTS
 693         select HAVE_IDE
 694         select ISA
 695         select NEED_MACH_MEMORY_H
 696         select SPARSE_IRQ
 697         help
 698           Support for StrongARM 11x0 based boards.
 699
 700 config ARCH_S3C24XX
 701         bool "Samsung S3C24XX SoCs"
 702         select ARCH_HAS_CPUFREQ
 703         select ARCH_REQUIRE_GPIOLIB
 704         select CLKDEV_LOOKUP
 705         select CLKSRC_SAMSUNG_PWM
 706         select GENERIC_CLOCKEVENTS
 707         select GPIO_SAMSUNG
 708         select HAVE_S3C2410_I2C if I2C
 709         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 710         select HAVE_S3C_RTC if RTC_CLASS
 711         select MULTI_IRQ_HANDLER
 712         select NEED_MACH_GPIO_H
 713         select NEED_MACH_IO_H
 714         select SAMSUNG_ATAGS
 715         help
 716           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 717           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 718           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 719           Samsung SMDK2410 development board (and derivatives).
 720
 721 config ARCH_S3C64XX
 722         bool "Samsung S3C64XX"
 723         select ARCH_HAS_CPUFREQ
 724         select ARCH_REQUIRE_GPIOLIB
 725         select ARM_VIC
 726         select CLKDEV_LOOKUP
 727         select CLKSRC_SAMSUNG_PWM
 728         select COMMON_CLK
 729         select CPU_V6
 730         select GENERIC_CLOCKEVENTS
 731         select GPIO_SAMSUNG
 732         select HAVE_S3C2410_I2C if I2C
 733         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 734         select HAVE_TCM
 735         select NEED_MACH_GPIO_H
 736         select NO_IOPORT
 737         select PLAT_SAMSUNG
 738         select PM_GENERIC_DOMAINS
 739         select S3C_DEV_NAND
 740         select S3C_GPIO_TRACK
 741         select SAMSUNG_ATAGS
 742         select SAMSUNG_GPIOLIB_4BIT
 743         select SAMSUNG_WAKEMASK
 744         select SAMSUNG_WDT_RESET
 745         select USB_ARCH_HAS_OHCI
 746         help
 747           Samsung S3C64XX series based systems
 748
 749 config ARCH_S5P64X0
 750         bool "Samsung S5P6440 S5P6450"
 751         select CLKDEV_LOOKUP
 752         select CLKSRC_SAMSUNG_PWM
 753         select CPU_V6
 754         select GENERIC_CLOCKEVENTS
 755         select GPIO_SAMSUNG
 756         select HAVE_S3C2410_I2C if I2C
 757         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 758         select HAVE_S3C_RTC if RTC_CLASS
 759         select NEED_MACH_GPIO_H
 760         select SAMSUNG_ATAGS
 761         select SAMSUNG_WDT_RESET
 762         help
 763           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
 764           SMDK6450.
 765
 766 config ARCH_S5PC100
 767         bool "Samsung S5PC100"
 768         select ARCH_REQUIRE_GPIOLIB
 769         select CLKDEV_LOOKUP
 770         select CLKSRC_SAMSUNG_PWM
 771         select CPU_V7
 772         select GENERIC_CLOCKEVENTS
 773         select GPIO_SAMSUNG
 774         select HAVE_S3C2410_I2C if I2C
 775         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 776         select HAVE_S3C_RTC if RTC_CLASS
 777         select NEED_MACH_GPIO_H
 778         select SAMSUNG_ATAGS
 779         select SAMSUNG_WDT_RESET
 780         help
 781           Samsung S5PC100 series based systems
 782
 783 config ARCH_S5PV210
 784         bool "Samsung S5PV210/S5PC110"
 785         select ARCH_HAS_CPUFREQ
 786         select ARCH_HAS_HOLES_MEMORYMODEL
 787         select ARCH_SPARSEMEM_ENABLE
 788         select CLKDEV_LOOKUP
 789         select CLKSRC_SAMSUNG_PWM
 790         select CPU_V7
 791         select GENERIC_CLOCKEVENTS
 792         select GPIO_SAMSUNG
 793         select HAVE_S3C2410_I2C if I2C
 794         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 795         select HAVE_S3C_RTC if RTC_CLASS
 796         select NEED_MACH_GPIO_H
 797         select NEED_MACH_MEMORY_H
 798         select SAMSUNG_ATAGS
 799         help
 800           Samsung S5PV210/S5PC110 series based systems
 801
 802 config ARCH_EXYNOS
 803         bool "Samsung EXYNOS"
 804         select ARCH_HAS_CPUFREQ
 805         select ARCH_HAS_HOLES_MEMORYMODEL
 806         select ARCH_REQUIRE_GPIOLIB
 807         select ARCH_SPARSEMEM_ENABLE
 808         select ARM_GIC
 809         select COMMON_CLK
 810         select CPU_V7
 811         select GENERIC_CLOCKEVENTS
 812         select HAVE_S3C2410_I2C if I2C
 813         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 814         select HAVE_S3C_RTC if RTC_CLASS
 815         select NEED_MACH_MEMORY_H
 816         select SPARSE_IRQ
 817         select USE_OF
 818         help
 819           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 820
 821 config ARCH_DAVINCI
 822         bool "TI DaVinci"
 823         select ARCH_HAS_HOLES_MEMORYMODEL
 824         select ARCH_REQUIRE_GPIOLIB
 825         select CLKDEV_LOOKUP
 826         select GENERIC_ALLOCATOR
 827         select GENERIC_CLOCKEVENTS
 828         select GENERIC_IRQ_CHIP
 829         select HAVE_IDE
 830         select TI_PRIV_EDMA
 831         select USE_OF
 832         select ZONE_DMA
 833         help
 834           Support for TI's DaVinci platform.
 835
 836 config ARCH_OMAP1
 837         bool "TI OMAP1"
 838         depends on MMU
 839         select ARCH_HAS_CPUFREQ
 840         select ARCH_HAS_HOLES_MEMORYMODEL
 841         select ARCH_OMAP
 842         select ARCH_REQUIRE_GPIOLIB
 843         select CLKDEV_LOOKUP
 844         select CLKSRC_MMIO
 845         select GENERIC_CLOCKEVENTS
 846         select GENERIC_IRQ_CHIP
 847         select HAVE_IDE
 848         select IRQ_DOMAIN
 849         select NEED_MACH_IO_H if PCCARD
 850         select NEED_MACH_MEMORY_H
 851         help
 852           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 853
 854 endchoice
 855
 856 menu "Multiple platform selection"
 857         depends on ARCH_MULTIPLATFORM
 858
 859 comment "CPU Core family selection"
 860
 861 config ARCH_MULTI_V4T
 862         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 863         depends on !ARCH_MULTI_V6_V7
 864         select ARCH_MULTI_V4_V5
 865         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 866                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 867                 CPU_ARM925T || CPU_ARM940T)
 868
 869 config ARCH_MULTI_V5
 870         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 871         depends on !ARCH_MULTI_V6_V7
 872         select ARCH_MULTI_V4_V5
 873         select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
 874                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 875                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 876
 877 config ARCH_MULTI_V4_V5
 878         bool
 879
 880 config ARCH_MULTI_V6
 881         bool "ARMv6 based platforms (ARM11)"
 882         select ARCH_MULTI_V6_V7
 883         select CPU_V6
 884
 885 config ARCH_MULTI_V7
 886         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 887         default y
 888         select ARCH_MULTI_V6_V7
 889         select CPU_V7
 890
 891 config ARCH_MULTI_V6_V7
 892         bool
 893
 894 config ARCH_MULTI_CPU_AUTO
 895         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 896         select ARCH_MULTI_V5
 897
 898 endmenu
 899
 900 #
 901 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 902 # Kconfigs may be included either alphabetically (according to the
 903 # plat- suffix) or along side the corresponding mach-* source.
 904 #
 905 source "arch/arm/mach-mvebu/Kconfig"
 906
 907 source "arch/arm/mach-at91/Kconfig"
 908
 909 source "arch/arm/mach-bcm/Kconfig"
 910
 911 source "arch/arm/mach-bcm2835/Kconfig"
 912
 913 source "arch/arm/mach-clps711x/Kconfig"
 914
 915 source "arch/arm/mach-cns3xxx/Kconfig"
 916
 917 source "arch/arm/mach-davinci/Kconfig"
 918
 919 source "arch/arm/mach-dove/Kconfig"
 920
 921 source "arch/arm/mach-ep93xx/Kconfig"
 922
 923 source "arch/arm/mach-footbridge/Kconfig"
 924
 925 source "arch/arm/mach-gemini/Kconfig"
 926
 927 source "arch/arm/mach-highbank/Kconfig"
 928
 929 source "arch/arm/mach-integrator/Kconfig"
 930
 931 source "arch/arm/mach-iop32x/Kconfig"
 932
 933 source "arch/arm/mach-iop33x/Kconfig"
 934
 935 source "arch/arm/mach-iop13xx/Kconfig"
 936
 937 source "arch/arm/mach-ixp4xx/Kconfig"
 938
 939 source "arch/arm/mach-keystone/Kconfig"
 940
 941 source "arch/arm/mach-kirkwood/Kconfig"
 942
 943 source "arch/arm/mach-ks8695/Kconfig"
 944
 945 source "arch/arm/mach-msm/Kconfig"
 946
 947 source "arch/arm/mach-mv78xx0/Kconfig"
 948
 949 source "arch/arm/mach-imx/Kconfig"
 950
 951 source "arch/arm/mach-mxs/Kconfig"
 952
 953 source "arch/arm/mach-netx/Kconfig"
 954
 955 source "arch/arm/mach-nomadik/Kconfig"
 956
 957 source "arch/arm/mach-nspire/Kconfig"
 958
 959 source "arch/arm/plat-omap/Kconfig"
 960
 961 source "arch/arm/mach-omap1/Kconfig"
 962
 963 source "arch/arm/mach-omap2/Kconfig"
 964
 965 source "arch/arm/mach-orion5x/Kconfig"
 966
 967 source "arch/arm/mach-picoxcell/Kconfig"
 968
 969 source "arch/arm/mach-pxa/Kconfig"
 970 source "arch/arm/plat-pxa/Kconfig"
 971
 972 source "arch/arm/mach-mmp/Kconfig"
 973
 974 source "arch/arm/mach-realview/Kconfig"
 975
 976 source "arch/arm/mach-rockchip/Kconfig"
 977
 978 source "arch/arm/mach-sa1100/Kconfig"
 979
 980 source "arch/arm/plat-samsung/Kconfig"
 981
 982 source "arch/arm/mach-socfpga/Kconfig"
 983
 984 source "arch/arm/mach-spear/Kconfig"
 985
 986 source "arch/arm/mach-sti/Kconfig"
 987
 988 source "arch/arm/mach-s3c24xx/Kconfig"
 989
 990 source "arch/arm/mach-s3c64xx/Kconfig"
 991
 992 source "arch/arm/mach-s5p64x0/Kconfig"
 993
 994 source "arch/arm/mach-s5pc100/Kconfig"
 995
 996 source "arch/arm/mach-s5pv210/Kconfig"
 997
 998 source "arch/arm/mach-exynos/Kconfig"
 999
1000 source "arch/arm/mach-shmobile/Kconfig"
1001
1002 source "arch/arm/mach-sunxi/Kconfig"
1003
1004 source "arch/arm/mach-prima2/Kconfig"
1005
1006 source "arch/arm/mach-tegra/Kconfig"
1007
1008 source "arch/arm/mach-u300/Kconfig"
1009
1010 source "arch/arm/mach-ux500/Kconfig"
1011
1012 source "arch/arm/mach-versatile/Kconfig"
1013
1014 source "arch/arm/mach-vexpress/Kconfig"
1015 source "arch/arm/plat-versatile/Kconfig"
1016
1017 source "arch/arm/mach-virt/Kconfig"
1018
1019 source "arch/arm/mach-vt8500/Kconfig"
1020
1021 source "arch/arm/mach-w90x900/Kconfig"
1022
1023 source "arch/arm/mach-zynq/Kconfig"
1024
1025 # Definitions to make life easier
1026 config ARCH_ACORN
1027         bool
1028
1029 config PLAT_IOP
1030         bool
1031         select GENERIC_CLOCKEVENTS
1032
1033 config PLAT_ORION
1034         bool
1035         select CLKSRC_MMIO
1036         select COMMON_CLK
1037         select GENERIC_IRQ_CHIP
1038         select IRQ_DOMAIN
1039
1040 config PLAT_ORION_LEGACY
1041         bool
1042         select PLAT_ORION
1043
1044 config PLAT_PXA
1045         bool
1046
1047 config PLAT_VERSATILE
1048         bool
1049
1050 config ARM_TIMER_SP804
1051         bool
1052         select CLKSRC_MMIO
1053         select CLKSRC_OF if OF
1054
1055 source arch/arm/mm/Kconfig
1056
1057 config ARM_NR_BANKS
1058         int
1059         default 16 if ARCH_EP93XX
1060         default 8
1061
1062 config IWMMXT
1063         bool "Enable iWMMXt support" if !CPU_PJ4
1064         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1065         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1066         help
1067           Enable support for iWMMXt context switching at run time if
1068           running on a CPU that supports it.
1069
1070 config MULTI_IRQ_HANDLER
1071         bool
1072         help
1073           Allow each machine to specify it's own IRQ handler at run time.
1074
1075 if !MMU
1076 source "arch/arm/Kconfig-nommu"
1077 endif
1078
1079 config PJ4B_ERRATA_4742
1080         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1081         depends on CPU_PJ4B && MACH_ARMADA_370
1082         default y
1083         help
1084           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1085           Event (WFE) IDLE states, a specific timing sensitivity exists between
1086           the retiring WFI/WFE instructions and the newly issued subsequent
1087           instructions.  This sensitivity can result in a CPU hang scenario.
1088           Workaround:
1089           The software must insert either a Data Synchronization Barrier (DSB)
1090           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1091           instruction
1092
1093 config ARM_ERRATA_326103
1094         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1095         depends on CPU_V6
1096         help
1097           Executing a SWP instruction to read-only memory does not set bit 11
1098           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1099           treat the access as a read, preventing a COW from occurring and
1100           causing the faulting task to livelock.
1101
1102 config ARM_ERRATA_411920
1103         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1104         depends on CPU_V6 || CPU_V6K
1105         help
1106           Invalidation of the Instruction Cache operation can
1107           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1108           It does not affect the MPCore. This option enables the ARM Ltd.
1109           recommended workaround.
1110
1111 config ARM_ERRATA_430973
1112         bool "ARM errata: Stale prediction on replaced interworking branch"
1113         depends on CPU_V7
1114         help
1115           This option enables the workaround for the 430973 Cortex-A8
1116           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1117           interworking branch is replaced with another code sequence at the
1118           same virtual address, whether due to self-modifying code or virtual
1119           to physical address re-mapping, Cortex-A8 does not recover from the
1120           stale interworking branch prediction. This results in Cortex-A8
1121           executing the new code sequence in the incorrect ARM or Thumb state.
1122           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1123           and also flushes the branch target cache at every context switch.
1124           Note that setting specific bits in the ACTLR register may not be
1125           available in non-secure mode.
1126
1127 config ARM_ERRATA_458693
1128         bool "ARM errata: Processor deadlock when a false hazard is created"
1129         depends on CPU_V7
1130         depends on !ARCH_MULTIPLATFORM
1131         help
1132           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1133           erratum. For very specific sequences of memory operations, it is
1134           possible for a hazard condition intended for a cache line to instead
1135           be incorrectly associated with a different cache line. This false
1136           hazard might then cause a processor deadlock. The workaround enables
1137           the L1 caching of the NEON accesses and disables the PLD instruction
1138           in the ACTLR register. Note that setting specific bits in the ACTLR
1139           register may not be available in non-secure mode.
1140
1141 config ARM_ERRATA_460075
1142         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1143         depends on CPU_V7
1144         depends on !ARCH_MULTIPLATFORM
1145         help
1146           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1147           erratum. Any asynchronous access to the L2 cache may encounter a
1148           situation in which recent store transactions to the L2 cache are lost
1149           and overwritten with stale memory contents from external memory. The
1150           workaround disables the write-allocate mode for the L2 cache via the
1151           ACTLR register. Note that setting specific bits in the ACTLR register
1152           may not be available in non-secure mode.
1153
1154 config ARM_ERRATA_742230
1155         bool "ARM errata: DMB operation may be faulty"
1156         depends on CPU_V7 && SMP
1157         depends on !ARCH_MULTIPLATFORM
1158         help
1159           This option enables the workaround for the 742230 Cortex-A9
1160           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1161           between two write operations may not ensure the correct visibility
1162           ordering of the two writes. This workaround sets a specific bit in
1163           the diagnostic register of the Cortex-A9 which causes the DMB
1164           instruction to behave as a DSB, ensuring the correct behaviour of
1165           the two writes.
1166
1167 config ARM_ERRATA_742231
1168         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1169         depends on CPU_V7 && SMP
1170         depends on !ARCH_MULTIPLATFORM
1171         help
1172           This option enables the workaround for the 742231 Cortex-A9
1173           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1174           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1175           accessing some data located in the same cache line, may get corrupted
1176           data due to bad handling of the address hazard when the line gets
1177           replaced from one of the CPUs at the same time as another CPU is
1178           accessing it. This workaround sets specific bits in the diagnostic
1179           register of the Cortex-A9 which reduces the linefill issuing
1180           capabilities of the processor.
1181
1182 config PL310_ERRATA_588369
1183         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1184         depends on CACHE_L2X0
1185         help
1186            The PL310 L2 cache controller implements three types of Clean &
1187            Invalidate maintenance operations: by Physical Address
1188            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1189            They are architecturally defined to behave as the execution of a
1190            clean operation followed immediately by an invalidate operation,
1191            both performing to the same memory location. This functionality
1192            is not correctly implemented in PL310 as clean lines are not
1193            invalidated as a result of these operations.
1194
1195 config ARM_ERRATA_643719
1196         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1197         depends on CPU_V7 && SMP
1198         help
1199           This option enables the workaround for the 643719 Cortex-A9 (prior to
1200           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1201           register returns zero when it should return one. The workaround
1202           corrects this value, ensuring cache maintenance operations which use
1203           it behave as intended and avoiding data corruption.
1204
1205 config ARM_ERRATA_720789
1206         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1207         depends on CPU_V7
1208         help
1209           This option enables the workaround for the 720789 Cortex-A9 (prior to
1210           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1211           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1212           As a consequence of this erratum, some TLB entries which should be
1213           invalidated are not, resulting in an incoherency in the system page
1214           tables. The workaround changes the TLB flushing routines to invalidate
1215           entries regardless of the ASID.
1216
1217 config PL310_ERRATA_727915
1218         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1219         depends on CACHE_L2X0
1220         help
1221           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1222           operation (offset 0x7FC). This operation runs in background so that
1223           PL310 can handle normal accesses while it is in progress. Under very
1224           rare circumstances, due to this erratum, write data can be lost when
1225           PL310 treats a cacheable write transaction during a Clean &
1226           Invalidate by Way operation.
1227
1228 config ARM_ERRATA_743622
1229         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1230         depends on CPU_V7
1231         depends on !ARCH_MULTIPLATFORM
1232         help
1233           This option enables the workaround for the 743622 Cortex-A9
1234           (r2p*) erratum. Under very rare conditions, a faulty
1235           optimisation in the Cortex-A9 Store Buffer may lead to data
1236           corruption. This workaround sets a specific bit in the diagnostic
1237           register of the Cortex-A9 which disables the Store Buffer
1238           optimisation, preventing the defect from occurring. This has no
1239           visible impact on the overall performance or power consumption of the
1240           processor.
1241
1242 config ARM_ERRATA_751472
1243         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1244         depends on CPU_V7
1245         depends on !ARCH_MULTIPLATFORM
1246         help
1247           This option enables the workaround for the 751472 Cortex-A9 (prior
1248           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1249           completion of a following broadcasted operation if the second
1250           operation is received by a CPU before the ICIALLUIS has completed,
1251           potentially leading to corrupted entries in the cache or TLB.
1252
1253 config PL310_ERRATA_753970
1254         bool "PL310 errata: cache sync operation may be faulty"
1255         depends on CACHE_PL310
1256         help
1257           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1258
1259           Under some condition the effect of cache sync operation on
1260           the store buffer still remains when the operation completes.
1261           This means that the store buffer is always asked to drain and
1262           this prevents it from merging any further writes. The workaround
1263           is to replace the normal offset of cache sync operation (0x730)
1264           by another offset targeting an unmapped PL310 register 0x740.
1265           This has the same effect as the cache sync operation: store buffer
1266           drain and waiting for all buffers empty.
1267
1268 config ARM_ERRATA_754322
1269         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1270         depends on CPU_V7
1271         help
1272           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1273           r3p*) erratum. A speculative memory access may cause a page table walk
1274           which starts prior to an ASID switch but completes afterwards. This
1275           can populate the micro-TLB with a stale entry which may be hit with
1276           the new ASID. This workaround places two dsb instructions in the mm
1277           switching code so that no page table walks can cross the ASID switch.
1278
1279 config ARM_ERRATA_754327
1280         bool "ARM errata: no automatic Store Buffer drain"
1281         depends on CPU_V7 && SMP
1282         help
1283           This option enables the workaround for the 754327 Cortex-A9 (prior to
1284           r2p0) erratum. The Store Buffer does not have any automatic draining
1285           mechanism and therefore a livelock may occur if an external agent
1286           continuously polls a memory location waiting to observe an update.
1287           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1288           written polling loops from denying visibility of updates to memory.
1289
1290 config ARM_ERRATA_364296
1291         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1292         depends on CPU_V6
1293         help
1294           This options enables the workaround for the 364296 ARM1136
1295           r0p2 erratum (possible cache data corruption with
1296           hit-under-miss enabled). It sets the undocumented bit 31 in
1297           the auxiliary control register and the FI bit in the control
1298           register, thus disabling hit-under-miss without putting the
1299           processor into full low interrupt latency mode. ARM11MPCore
1300           is not affected.
1301
1302 config ARM_ERRATA_764369
1303         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1304         depends on CPU_V7 && SMP
1305         help
1306           This option enables the workaround for erratum 764369
1307           affecting Cortex-A9 MPCore with two or more processors (all
1308           current revisions). Under certain timing circumstances, a data
1309           cache line maintenance operation by MVA targeting an Inner
1310           Shareable memory region may fail to proceed up to either the
1311           Point of Coherency or to the Point of Unification of the
1312           system. This workaround adds a DSB instruction before the
1313           relevant cache maintenance functions and sets a specific bit
1314           in the diagnostic control register of the SCU.
1315
1316 config PL310_ERRATA_769419
1317         bool "PL310 errata: no automatic Store Buffer drain"
1318         depends on CACHE_L2X0
1319         help
1320           On revisions of the PL310 prior to r3p2, the Store Buffer does
1321           not automatically drain. This can cause normal, non-cacheable
1322           writes to be retained when the memory system is idle, leading
1323           to suboptimal I/O performance for drivers using coherent DMA.
1324           This option adds a write barrier to the cpu_idle loop so that,
1325           on systems with an outer cache, the store buffer is drained
1326           explicitly.
1327
1328 config ARM_ERRATA_775420
1329        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1330        depends on CPU_V7
1331        help
1332          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1333          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1334          operation aborts with MMU exception, it might cause the processor
1335          to deadlock. This workaround puts DSB before executing ISB if
1336          an abort may occur on cache maintenance.
1337
1338 config ARM_ERRATA_798181
1339         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1340         depends on CPU_V7 && SMP
1341         help
1342           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1343           adequately shooting down all use of the old entries. This
1344           option enables the Linux kernel workaround for this erratum
1345           which sends an IPI to the CPUs that are running the same ASID
1346           as the one being invalidated.
1347
1348 config ARM_ERRATA_773022
1349         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1350         depends on CPU_V7
1351         help
1352           This option enables the workaround for the 773022 Cortex-A15
1353           (up to r0p4) erratum. In certain rare sequences of code, the
1354           loop buffer may deliver incorrect instructions. This
1355           workaround disables the loop buffer to avoid the erratum.
1356
1357 endmenu
1358
1359 source "arch/arm/common/Kconfig"
1360
1361 menu "Bus support"
1362
1363 config ARM_AMBA
1364         bool
1365
1366 config ISA
1367         bool
1368         help
1369           Find out whether you have ISA slots on your motherboard.  ISA is the
1370           name of a bus system, i.e. the way the CPU talks to the other stuff
1371           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1372           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1373           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1374
1375 # Select ISA DMA controller support
1376 config ISA_DMA
1377         bool
1378         select ISA_DMA_API
1379
1380 # Select ISA DMA interface
1381 config ISA_DMA_API
1382         bool
1383
1384 config PCI
1385         bool "PCI support" if MIGHT_HAVE_PCI
1386         help
1387           Find out whether you have a PCI motherboard. PCI is the name of a
1388           bus system, i.e. the way the CPU talks to the other stuff inside
1389           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1390           VESA. If you have PCI, say Y, otherwise N.
1391
1392 config PCI_DOMAINS
1393         bool
1394         depends on PCI
1395
1396 config PCI_NANOENGINE
1397         bool "BSE nanoEngine PCI support"
1398         depends on SA1100_NANOENGINE
1399         help
1400           Enable PCI on the BSE nanoEngine board.
1401
1402 config PCI_SYSCALL
1403         def_bool PCI
1404
1405 config PCI_HOST_ITE8152
1406         bool
1407         depends on PCI && MACH_ARMCORE
1408         default y
1409         select DMABOUNCE
1410
1411 source "drivers/pci/Kconfig"
1412 source "drivers/pci/pcie/Kconfig"
1413
1414 source "drivers/pcmcia/Kconfig"
1415
1416 endmenu
1417
1418 menu "Kernel Features"
1419
1420 config HAVE_SMP
1421         bool
1422         help
1423           This option should be selected by machines which have an SMP-
1424           capable CPU.
1425
1426           The only effect of this option is to make the SMP-related
1427           options available to the user for configuration.
1428
1429 config SMP
1430         bool "Symmetric Multi-Processing"
1431         depends on CPU_V6K || CPU_V7
1432         depends on GENERIC_CLOCKEVENTS
1433         depends on HAVE_SMP
1434         depends on MMU || ARM_MPU
1435         select USE_GENERIC_SMP_HELPERS
1436         help
1437           This enables support for systems with more than one CPU. If you have
1438           a system with only one CPU, like most personal computers, say N. If
1439           you have a system with more than one CPU, say Y.
1440
1441           If you say N here, the kernel will run on single and multiprocessor
1442           machines, but will use only one CPU of a multiprocessor machine. If
1443           you say Y here, the kernel will run on many, but not all, single
1444           processor machines. On a single processor machine, the kernel will
1445           run faster if you say N here.
1446
1447           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1448           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1449           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1450
1451           If you don't know what to do here, say N.
1452
1453 config SMP_ON_UP
1454         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1455         depends on SMP && !XIP_KERNEL && MMU
1456         default y
1457         help
1458           SMP kernels contain instructions which fail on non-SMP processors.
1459           Enabling this option allows the kernel to modify itself to make
1460           these instructions safe.  Disabling it allows about 1K of space
1461           savings.
1462
1463           If you don't know what to do here, say Y.
1464
1465 config ARM_CPU_TOPOLOGY
1466         bool "Support cpu topology definition"
1467         depends on SMP && CPU_V7
1468         default y
1469         help
1470           Support ARM cpu topology definition. The MPIDR register defines
1471           affinity between processors which is then used to describe the cpu
1472           topology of an ARM System.
1473
1474 config SCHED_MC
1475         bool "Multi-core scheduler support"
1476         depends on ARM_CPU_TOPOLOGY
1477         help
1478           Multi-core scheduler support improves the CPU scheduler's decision
1479           making when dealing with multi-core CPU chips at a cost of slightly
1480           increased overhead in some places. If unsure say N here.
1481
1482 config SCHED_SMT
1483         bool "SMT scheduler support"
1484         depends on ARM_CPU_TOPOLOGY
1485         help
1486           Improves the CPU scheduler's decision making when dealing with
1487           MultiThreading at a cost of slightly increased overhead in some
1488           places. If unsure say N here.
1489
1490 config HAVE_ARM_SCU
1491         bool
1492         help
1493           This option enables support for the ARM system coherency unit
1494
1495 config HAVE_ARM_ARCH_TIMER
1496         bool "Architected timer support"
1497         depends on CPU_V7
1498         select ARM_ARCH_TIMER
1499         help
1500           This option enables support for the ARM architected timer
1501
1502 config HAVE_ARM_TWD
1503         bool
1504         depends on SMP
1505         select CLKSRC_OF if OF
1506         help
1507           This options enables support for the ARM timer and watchdog unit
1508
1509 config MCPM
1510         bool "Multi-Cluster Power Management"
1511         depends on CPU_V7 && SMP
1512         help
1513           This option provides the common power management infrastructure
1514           for (multi-)cluster based systems, such as big.LITTLE based
1515           systems.
1516
1517 config BIG_LITTLE
1518         bool "big.LITTLE support (Experimental)"
1519         depends on CPU_V7 && SMP
1520         select MCPM
1521         help
1522           This option enables support selections for the big.LITTLE
1523           system architecture.
1524
1525 config BL_SWITCHER
1526         bool "big.LITTLE switcher support"
1527         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1528         select CPU_PM
1529         select ARM_CPU_SUSPEND
1530         help
1531           The big.LITTLE "switcher" provides the core functionality to
1532           transparently handle transition between a cluster of A15's
1533           and a cluster of A7's in a big.LITTLE system.
1534
1535 config BL_SWITCHER_DUMMY_IF
1536         tristate "Simple big.LITTLE switcher user interface"
1537         depends on BL_SWITCHER && DEBUG_KERNEL
1538         help
1539           This is a simple and dummy char dev interface to control
1540           the big.LITTLE switcher core code.  It is meant for
1541           debugging purposes only.
1542
1543 choice
1544         prompt "Memory split"
1545         default VMSPLIT_3G
1546         help
1547           Select the desired split between kernel and user memory.
1548
1549           If you are not absolutely sure what you are doing, leave this
1550           option alone!
1551
1552         config VMSPLIT_3G
1553                 bool "3G/1G user/kernel split"
1554         config VMSPLIT_2G
1555                 bool "2G/2G user/kernel split"
1556         config VMSPLIT_1G
1557                 bool "1G/3G user/kernel split"
1558 endchoice
1559
1560 config PAGE_OFFSET
1561         hex
1562         default 0x40000000 if VMSPLIT_1G
1563         default 0x80000000 if VMSPLIT_2G
1564         default 0xC0000000
1565
1566 config NR_CPUS
1567         int "Maximum number of CPUs (2-32)"
1568         range 2 32
1569         depends on SMP
1570         default "4"
1571
1572 config HOTPLUG_CPU
1573         bool "Support for hot-pluggable CPUs"
1574         depends on SMP
1575         help
1576           Say Y here to experiment with turning CPUs off and on.  CPUs
1577           can be controlled through /sys/devices/system/cpu.
1578
1579 config ARM_PSCI
1580         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1581         depends on CPU_V7
1582         help
1583           Say Y here if you want Linux to communicate with system firmware
1584           implementing the PSCI specification for CPU-centric power
1585           management operations described in ARM document number ARM DEN
1586           0022A ("Power State Coordination Interface System Software on
1587           ARM processors").
1588
1589 # The GPIO number here must be sorted by descending number. In case of
1590 # a multiplatform kernel, we just want the highest value required by the
1591 # selected platforms.
1592 config ARCH_NR_GPIO
1593         int
1594         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1595         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1596         default 392 if ARCH_U8500
1597         default 352 if ARCH_VT8500
1598         default 288 if ARCH_SUNXI
1599         default 264 if MACH_H4700
1600         default 0
1601         help
1602           Maximum number of GPIOs in the system.
1603
1604           If unsure, leave the default value.
1605
1606 source kernel/Kconfig.preempt
1607
1608 config HZ_FIXED
1609         int
1610         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1611                 ARCH_S5PV210 || ARCH_EXYNOS4
1612         default AT91_TIMER_HZ if ARCH_AT91
1613         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1614         default 0
1615
1616 choice
1617         depends on HZ_FIXED = 0
1618         prompt "Timer frequency"
1619
1620 config HZ_100
1621         bool "100 Hz"
1622
1623 config HZ_200
1624         bool "200 Hz"
1625
1626 config HZ_250
1627         bool "250 Hz"
1628
1629 config HZ_300
1630         bool "300 Hz"
1631
1632 config HZ_500
1633         bool "500 Hz"
1634
1635 config HZ_1000
1636         bool "1000 Hz"
1637
1638 endchoice
1639
1640 config HZ
1641         int
1642         default HZ_FIXED if HZ_FIXED != 0
1643         default 100 if HZ_100
1644         default 200 if HZ_200
1645         default 250 if HZ_250
1646         default 300 if HZ_300
1647         default 500 if HZ_500
1648         default 1000
1649
1650 config SCHED_HRTICK
1651         def_bool HIGH_RES_TIMERS
1652
1653 config SCHED_HRTICK
1654         def_bool HIGH_RES_TIMERS
1655
1656 config THUMB2_KERNEL
1657         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1658         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1659         default y if CPU_THUMBONLY
1660         select AEABI
1661         select ARM_ASM_UNIFIED
1662         select ARM_UNWIND
1663         help
1664           By enabling this option, the kernel will be compiled in
1665           Thumb-2 mode. A compiler/assembler that understand the unified
1666           ARM-Thumb syntax is needed.
1667
1668           If unsure, say N.
1669
1670 config THUMB2_AVOID_R_ARM_THM_JUMP11
1671         bool "Work around buggy Thumb-2 short branch relocations in gas"
1672         depends on THUMB2_KERNEL && MODULES
1673         default y
1674         help
1675           Various binutils versions can resolve Thumb-2 branches to
1676           locally-defined, preemptible global symbols as short-range "b.n"
1677           branch instructions.
1678
1679           This is a problem, because there's no guarantee the final
1680           destination of the symbol, or any candidate locations for a
1681           trampoline, are within range of the branch.  For this reason, the
1682           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1683           relocation in modules at all, and it makes little sense to add
1684           support.
1685
1686           The symptom is that the kernel fails with an "unsupported
1687           relocation" error when loading some modules.
1688
1689           Until fixed tools are available, passing
1690           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1691           code which hits this problem, at the cost of a bit of extra runtime
1692           stack usage in some cases.
1693
1694           The problem is described in more detail at:
1695               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1696
1697           Only Thumb-2 kernels are affected.
1698
1699           Unless you are sure your tools don't have this problem, say Y.
1700
1701 config ARM_ASM_UNIFIED
1702         bool
1703
1704 config AEABI
1705         bool "Use the ARM EABI to compile the kernel"
1706         help
1707           This option allows for the kernel to be compiled using the latest
1708           ARM ABI (aka EABI).  This is only useful if you are using a user
1709           space environment that is also compiled with EABI.
1710
1711           Since there are major incompatibilities between the legacy ABI and
1712           EABI, especially with regard to structure member alignment, this
1713           option also changes the kernel syscall calling convention to
1714           disambiguate both ABIs and allow for backward compatibility support
1715           (selected with CONFIG_OABI_COMPAT).
1716
1717           To use this you need GCC version 4.0.0 or later.
1718
1719 config OABI_COMPAT
1720         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1721         depends on AEABI && !THUMB2_KERNEL
1722         help
1723           This option preserves the old syscall interface along with the
1724           new (ARM EABI) one. It also provides a compatibility layer to
1725           intercept syscalls that have structure arguments which layout
1726           in memory differs between the legacy ABI and the new ARM EABI
1727           (only for non "thumb" binaries). This option adds a tiny
1728           overhead to all syscalls and produces a slightly larger kernel.
1729           If you know you'll be using only pure EABI user space then you
1730           can say N here. If this option is not selected and you attempt
1731           to execute a legacy ABI binary then the result will be
1732           UNPREDICTABLE (in fact it can be predicted that it won't work
1733           at all). If in doubt say N.
1734
1735 config ARCH_HAS_HOLES_MEMORYMODEL
1736         bool
1737
1738 config ARCH_SPARSEMEM_ENABLE
1739         bool
1740
1741 config ARCH_SPARSEMEM_DEFAULT
1742         def_bool ARCH_SPARSEMEM_ENABLE
1743
1744 config ARCH_SELECT_MEMORY_MODEL
1745         def_bool ARCH_SPARSEMEM_ENABLE
1746
1747 config HAVE_ARCH_PFN_VALID
1748         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1749
1750 config HIGHMEM
1751         bool "High Memory Support"
1752         depends on MMU
1753         help
1754           The address space of ARM processors is only 4 Gigabytes large
1755           and it has to accommodate user address space, kernel address
1756           space as well as some memory mapped IO. That means that, if you
1757           have a large amount of physical memory and/or IO, not all of the
1758           memory can be "permanently mapped" by the kernel. The physical
1759           memory that is not permanently mapped is called "high memory".
1760
1761           Depending on the selected kernel/user memory split, minimum
1762           vmalloc space and actual amount of RAM, you may not need this
1763           option which should result in a slightly faster kernel.
1764
1765           If unsure, say n.
1766
1767 config HIGHPTE
1768         bool "Allocate 2nd-level pagetables from highmem"
1769         depends on HIGHMEM
1770
1771 config HW_PERF_EVENTS
1772         bool "Enable hardware performance counter support for perf events"
1773         depends on PERF_EVENTS
1774         default y
1775         help
1776           Enable hardware performance counter support for perf events. If
1777           disabled, perf events will use software events only.
1778
1779 config SYS_SUPPORTS_HUGETLBFS
1780        def_bool y
1781        depends on ARM_LPAE
1782
1783 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1784        def_bool y
1785        depends on ARM_LPAE
1786
1787 config ARCH_WANT_GENERAL_HUGETLB
1788         def_bool y
1789
1790 source "mm/Kconfig"
1791
1792 config FORCE_MAX_ZONEORDER
1793         int "Maximum zone order" if ARCH_SHMOBILE
1794         range 11 64 if ARCH_SHMOBILE
1795         default "12" if SOC_AM33XX
1796         default "9" if SA1111
1797         default "11"
1798         help
1799           The kernel memory allocator divides physically contiguous memory
1800           blocks into "zones", where each zone is a power of two number of
1801           pages.  This option selects the largest power of two that the kernel
1802           keeps in the memory allocator.  If you need to allocate very large
1803           blocks of physically contiguous memory, then you may need to
1804           increase this value.
1805
1806           This config option is actually maximum order plus one. For example,
1807           a value of 11 means that the largest free memory block is 2^10 pages.
1808
1809 config ALIGNMENT_TRAP
1810         bool
1811         depends on CPU_CP15_MMU
1812         default y if !ARCH_EBSA110
1813         select HAVE_PROC_CPU if PROC_FS
1814         help
1815           ARM processors cannot fetch/store information which is not
1816           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1817           address divisible by 4. On 32-bit ARM processors, these non-aligned
1818           fetch/store instructions will be emulated in software if you say
1819           here, which has a severe performance impact. This is necessary for
1820           correct operation of some network protocols. With an IP-only
1821           configuration it is safe to say N, otherwise say Y.
1822
1823 config UACCESS_WITH_MEMCPY
1824         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1825         depends on MMU
1826         default y if CPU_FEROCEON
1827         help
1828           Implement faster copy_to_user and clear_user methods for CPU
1829           cores where a 8-word STM instruction give significantly higher
1830           memory write throughput than a sequence of individual 32bit stores.
1831
1832           A possible side effect is a slight increase in scheduling latency
1833           between threads sharing the same address space if they invoke
1834           such copy operations with large buffers.
1835
1836           However, if the CPU data cache is using a write-allocate mode,
1837           this option is unlikely to provide any performance gain.
1838
1839 config SECCOMP
1840         bool
1841         prompt "Enable seccomp to safely compute untrusted bytecode"
1842         ---help---
1843           This kernel feature is useful for number crunching applications
1844           that may need to compute untrusted bytecode during their
1845           execution. By using pipes or other transports made available to
1846           the process as file descriptors supporting the read/write
1847           syscalls, it's possible to isolate those applications in
1848           their own address space using seccomp. Once seccomp is
1849           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1850           and the task is only allowed to execute a few safe syscalls
1851           defined by each seccomp mode.
1852
1853 config CC_STACKPROTECTOR
1854         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1855         help
1856           This option turns on the -fstack-protector GCC feature. This
1857           feature puts, at the beginning of functions, a canary value on
1858           the stack just before the return address, and validates
1859           the value just before actually returning.  Stack based buffer
1860           overflows (that need to overwrite this return address) now also
1861           overwrite the canary, which gets detected and the attack is then
1862           neutralized via a kernel panic.
1863           This feature requires gcc version 4.2 or above.
1864
1865 config XEN_DOM0
1866         def_bool y
1867         depends on XEN
1868
1869 config XEN
1870         bool "Xen guest support on ARM (EXPERIMENTAL)"
1871         depends on ARM && AEABI && OF
1872         depends on CPU_V7 && !CPU_V6
1873         depends on !GENERIC_ATOMIC64
1874         select ARM_PSCI
1875         help
1876           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1877
1878 endmenu
1879
1880 menu "Boot options"
1881
1882 config USE_OF
1883         bool "Flattened Device Tree support"
1884         select IRQ_DOMAIN
1885         select OF
1886         select OF_EARLY_FLATTREE
1887         help
1888           Include support for flattened device tree machine descriptions.
1889
1890 config ATAGS
1891         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1892         default y
1893         help
1894           This is the traditional way of passing data to the kernel at boot
1895           time. If you are solely relying on the flattened device tree (or
1896           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1897           to remove ATAGS support from your kernel binary.  If unsure,
1898           leave this to y.
1899
1900 config DEPRECATED_PARAM_STRUCT
1901         bool "Provide old way to pass kernel parameters"
1902         depends on ATAGS
1903         help
1904           This was deprecated in 2001 and announced to live on for 5 years.
1905           Some old boot loaders still use this way.
1906
1907 # Compressed boot loader in ROM.  Yes, we really want to ask about
1908 # TEXT and BSS so we preserve their values in the config files.
1909 config ZBOOT_ROM_TEXT
1910         hex "Compressed ROM boot loader base address"
1911         default "0"
1912         help
1913           The physical address at which the ROM-able zImage is to be
1914           placed in the target.  Platforms which normally make use of
1915           ROM-able zImage formats normally set this to a suitable
1916           value in their defconfig file.
1917
1918           If ZBOOT_ROM is not enabled, this has no effect.
1919
1920 config ZBOOT_ROM_BSS
1921         hex "Compressed ROM boot loader BSS address"
1922         default "0"
1923         help
1924           The base address of an area of read/write memory in the target
1925           for the ROM-able zImage which must be available while the
1926           decompressor is running. It must be large enough to hold the
1927           entire decompressed kernel plus an additional 128 KiB.
1928           Platforms which normally make use of ROM-able zImage formats
1929           normally set this to a suitable value in their defconfig file.
1930
1931           If ZBOOT_ROM is not enabled, this has no effect.
1932
1933 config ZBOOT_ROM
1934         bool "Compressed boot loader in ROM/flash"
1935         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1936         help
1937           Say Y here if you intend to execute your compressed kernel image
1938           (zImage) directly from ROM or flash.  If unsure, say N.
1939
1940 choice
1941         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1942         depends on ZBOOT_ROM && ARCH_SH7372
1943         default ZBOOT_ROM_NONE
1944         help
1945           Include experimental SD/MMC loading code in the ROM-able zImage.
1946           With this enabled it is possible to write the ROM-able zImage
1947           kernel image to an MMC or SD card and boot the kernel straight
1948           from the reset vector. At reset the processor Mask ROM will load
1949           the first part of the ROM-able zImage which in turn loads the
1950           rest the kernel image to RAM.
1951
1952 config ZBOOT_ROM_NONE
1953         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1954         help
1955           Do not load image from SD or MMC
1956
1957 config ZBOOT_ROM_MMCIF
1958         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1959         help
1960           Load image from MMCIF hardware block.
1961
1962 config ZBOOT_ROM_SH_MOBILE_SDHI
1963         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1964         help
1965           Load image from SDHI hardware block
1966
1967 endchoice
1968
1969 config ARM_APPENDED_DTB
1970         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1971         depends on OF && !ZBOOT_ROM
1972         help
1973           With this option, the boot code will look for a device tree binary
1974           (DTB) appended to zImage
1975           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1976
1977           This is meant as a backward compatibility convenience for those
1978           systems with a bootloader that can't be upgraded to accommodate
1979           the documented boot protocol using a device tree.
1980
1981           Beware that there is very little in terms of protection against
1982           this option being confused by leftover garbage in memory that might
1983           look like a DTB header after a reboot if no actual DTB is appended
1984           to zImage.  Do not leave this option active in a production kernel
1985           if you don't intend to always append a DTB.  Proper passing of the
1986           location into r2 of a bootloader provided DTB is always preferable
1987           to this option.
1988
1989 config ARM_ATAG_DTB_COMPAT
1990         bool "Supplement the appended DTB with traditional ATAG information"
1991         depends on ARM_APPENDED_DTB
1992         help
1993           Some old bootloaders can't be updated to a DTB capable one, yet
1994           they provide ATAGs with memory configuration, the ramdisk address,
1995           the kernel cmdline string, etc.  Such information is dynamically
1996           provided by the bootloader and can't always be stored in a static
1997           DTB.  To allow a device tree enabled kernel to be used with such
1998           bootloaders, this option allows zImage to extract the information
1999           from the ATAG list and store it at run time into the appended DTB.
2000
2001 choice
2002         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2003         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2004
2005 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2006         bool "Use bootloader kernel arguments if available"
2007         help
2008           Uses the command-line options passed by the boot loader instead of
2009           the device tree bootargs property. If the boot loader doesn't provide
2010           any, the device tree bootargs property will be used.
2011
2012 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2013         bool "Extend with bootloader kernel arguments"
2014         help
2015           The command-line arguments provided by the boot loader will be
2016           appended to the the device tree bootargs property.
2017
2018 endchoice
2019
2020 config CMDLINE
2021         string "Default kernel command string"
2022         default ""
2023         help
2024           On some architectures (EBSA110 and CATS), there is currently no way
2025           for the boot loader to pass arguments to the kernel. For these
2026           architectures, you should supply some command-line options at build
2027           time by entering them here. As a minimum, you should specify the
2028           memory size and the root device (e.g., mem=64M root=/dev/nfs).
2029
2030 choice
2031         prompt "Kernel command line type" if CMDLINE != ""
2032         default CMDLINE_FROM_BOOTLOADER
2033         depends on ATAGS
2034
2035 config CMDLINE_FROM_BOOTLOADER
2036         bool "Use bootloader kernel arguments if available"
2037         help
2038           Uses the command-line options passed by the boot loader. If
2039           the boot loader doesn't provide any, the default kernel command
2040           string provided in CMDLINE will be used.
2041
2042 config CMDLINE_EXTEND
2043         bool "Extend bootloader kernel arguments"
2044         help
2045           The command-line arguments provided by the boot loader will be
2046           appended to the default kernel command string.
2047
2048 config CMDLINE_FORCE
2049         bool "Always use the default kernel command string"
2050         help
2051           Always use the default kernel command string, even if the boot
2052           loader passes other arguments to the kernel.
2053           This is useful if you cannot or don't want to change the
2054           command-line options your boot loader passes to the kernel.
2055 endchoice
2056
2057 config XIP_KERNEL
2058         bool "Kernel Execute-In-Place from ROM"
2059         depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2060         help
2061           Execute-In-Place allows the kernel to run from non-volatile storage
2062           directly addressable by the CPU, such as NOR flash. This saves RAM
2063           space since the text section of the kernel is not loaded from flash
2064           to RAM.  Read-write sections, such as the data section and stack,
2065           are still copied to RAM.  The XIP kernel is not compressed since
2066           it has to run directly from flash, so it will take more space to
2067           store it.  The flash address used to link the kernel object files,
2068           and for storing it, is configuration dependent. Therefore, if you
2069           say Y here, you must know the proper physical address where to
2070           store the kernel image depending on your own flash memory usage.
2071
2072           Also note that the make target becomes "make xipImage" rather than
2073           "make zImage" or "make Image".  The final kernel binary to put in
2074           ROM memory will be arch/arm/boot/xipImage.
2075
2076           If unsure, say N.
2077
2078 config XIP_PHYS_ADDR
2079         hex "XIP Kernel Physical Location"
2080         depends on XIP_KERNEL
2081         default "0x00080000"
2082         help
2083           This is the physical address in your flash memory the kernel will
2084           be linked for and stored to.  This address is dependent on your
2085           own flash usage.
2086
2087 config KEXEC
2088         bool "Kexec system call (EXPERIMENTAL)"
2089         depends on (!SMP || PM_SLEEP_SMP)
2090         help
2091           kexec is a system call that implements the ability to shutdown your
2092           current kernel, and to start another kernel.  It is like a reboot
2093           but it is independent of the system firmware.   And like a reboot
2094           you can start any kernel with it, not just Linux.
2095
2096           It is an ongoing process to be certain the hardware in a machine
2097           is properly shutdown, so do not be surprised if this code does not
2098           initially work for you.
2099
2100 config ATAGS_PROC
2101         bool "Export atags in procfs"
2102         depends on ATAGS && KEXEC
2103         default y
2104         help
2105           Should the atags used to boot the kernel be exported in an "atags"
2106           file in procfs. Useful with kexec.
2107
2108 config CRASH_DUMP
2109         bool "Build kdump crash kernel (EXPERIMENTAL)"
2110         help
2111           Generate crash dump after being started by kexec. This should
2112           be normally only set in special crash dump kernels which are
2113           loaded in the main kernel with kexec-tools into a specially
2114           reserved region and then later executed after a crash by
2115           kdump/kexec. The crash dump kernel must be compiled to a
2116           memory address not used by the main kernel
2117
2118           For more details see Documentation/kdump/kdump.txt
2119
2120 config AUTO_ZRELADDR
2121         bool "Auto calculation of the decompressed kernel image address"
2122         depends on !ZBOOT_ROM
2123         help
2124           ZRELADDR is the physical address where the decompressed kernel
2125           image will be placed. If AUTO_ZRELADDR is selected, the address
2126           will be determined at run-time by masking the current IP with
2127           0xf8000000. This assumes the zImage being placed in the first 128MB
2128           from start of memory.
2129
2130 endmenu
2131
2132 menu "CPU Power Management"
2133
2134 if ARCH_HAS_CPUFREQ
2135 source "drivers/cpufreq/Kconfig"
2136 endif
2137
2138 source "drivers/cpuidle/Kconfig"
2139
2140 endmenu
2141
2142 menu "Floating point emulation"
2143
2144 comment "At least one emulation must be selected"
2145
2146 config FPE_NWFPE
2147         bool "NWFPE math emulation"
2148         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2149         ---help---
2150           Say Y to include the NWFPE floating point emulator in the kernel.
2151           This is necessary to run most binaries. Linux does not currently
2152           support floating point hardware so you need to say Y here even if
2153           your machine has an FPA or floating point co-processor podule.
2154
2155           You may say N here if you are going to load the Acorn FPEmulator
2156           early in the bootup.
2157
2158 config FPE_NWFPE_XP
2159         bool "Support extended precision"
2160         depends on FPE_NWFPE
2161         help
2162           Say Y to include 80-bit support in the kernel floating-point
2163           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2164           Note that gcc does not generate 80-bit operations by default,
2165           so in most cases this option only enlarges the size of the
2166           floating point emulator without any good reason.
2167
2168           You almost surely want to say N here.
2169
2170 config FPE_FASTFPE
2171         bool "FastFPE math emulation (EXPERIMENTAL)"
2172         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2173         ---help---
2174           Say Y here to include the FAST floating point emulator in the kernel.
2175           This is an experimental much faster emulator which now also has full
2176           precision for the mantissa.  It does not support any exceptions.
2177           It is very simple, and approximately 3-6 times faster than NWFPE.
2178
2179           It should be sufficient for most programs.  It may be not suitable
2180           for scientific calculations, but you have to check this for yourself.
2181           If you do not feel you need a faster FP emulation you should better
2182           choose NWFPE.
2183
2184 config VFP
2185         bool "VFP-format floating point maths"
2186         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2187         help
2188           Say Y to include VFP support code in the kernel. This is needed
2189           if your hardware includes a VFP unit.
2190
2191           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2192           release notes and additional status information.
2193
2194           Say N if your target does not have VFP hardware.
2195
2196 config VFPv3
2197         bool
2198         depends on VFP
2199         default y if CPU_V7
2200
2201 config NEON
2202         bool "Advanced SIMD (NEON) Extension support"
2203         depends on VFPv3 && CPU_V7
2204         help
2205           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2206           Extension.
2207
2208 config KERNEL_MODE_NEON
2209         bool "Support for NEON in kernel mode"
2210         depends on NEON && AEABI
2211         help
2212           Say Y to include support for NEON in kernel mode.
2213
2214 endmenu
2215
2216 menu "Userspace binary formats"
2217
2218 source "fs/Kconfig.binfmt"
2219
2220 config ARTHUR
2221         tristate "RISC OS personality"
2222         depends on !AEABI
2223         help
2224           Say Y here to include the kernel code necessary if you want to run
2225           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2226           experimental; if this sounds frightening, say N and sleep in peace.
2227           You can also say M here to compile this support as a module (which
2228           will be called arthur).
2229
2230 endmenu
2231
2232 menu "Power management options"
2233
2234 source "kernel/power/Kconfig"
2235
2236 config ARCH_SUSPEND_POSSIBLE
2237         depends on !ARCH_S5PC100
2238         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2239                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2240         def_bool y
2241
2242 config ARM_CPU_SUSPEND
2243         def_bool PM_SLEEP
2244
2245 endmenu
2246
2247 source "net/Kconfig"
2248
2249 source "drivers/Kconfig"
2250
2251 source "fs/Kconfig"
2252
2253 source "arch/arm/Kconfig.debug"
2254
2255 source "security/Kconfig"
2256
2257 source "crypto/Kconfig"
2258
2259 source "lib/Kconfig"
2260
2261 source "arch/arm/kvm/Kconfig"