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lib/decompress_unlz4.c: always set an error return code on failures
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / imx28.dtsi
1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12 #include "skeleton.dtsi"
13 #include "imx28-pinfunc.h"
14
15 / {
16 interrupt-parent = <&icoll>;
17
18 aliases {
19 ethernet0 = &mac0;
20 ethernet1 = &mac1;
21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
26 saif0 = &saif0;
27 saif1 = &saif1;
28 serial0 = &auart0;
29 serial1 = &auart1;
30 serial2 = &auart2;
31 serial3 = &auart3;
32 serial4 = &auart4;
33 spi0 = &ssp1;
34 spi1 = &ssp2;
35 };
36
37 cpus {
38 #address-cells = <0>;
39 #size-cells = <0>;
40
41 cpu {
42 compatible = "arm,arm926ej-s";
43 device_type = "cpu";
44 };
45 };
46
47 apb@80000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 reg = <0x80000000 0x80000>;
52 ranges;
53
54 apbh@80000000 {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 reg = <0x80000000 0x3c900>;
59 ranges;
60
61 icoll: interrupt-controller@80000000 {
62 compatible = "fsl,imx28-icoll", "fsl,icoll";
63 interrupt-controller;
64 #interrupt-cells = <1>;
65 reg = <0x80000000 0x2000>;
66 };
67
68 hsadc: hsadc@80002000 {
69 reg = <0x80002000 0x2000>;
70 interrupts = <13>;
71 dmas = <&dma_apbh 12>;
72 dma-names = "rx";
73 status = "disabled";
74 };
75
76 dma_apbh: dma-apbh@80004000 {
77 compatible = "fsl,imx28-dma-apbh";
78 reg = <0x80004000 0x2000>;
79 interrupts = <82 83 84 85
80 88 88 88 88
81 88 88 88 88
82 87 86 0 0>;
83 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
84 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
85 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
86 "hsadc", "lcdif", "empty", "empty";
87 #dma-cells = <1>;
88 dma-channels = <16>;
89 clocks = <&clks 25>;
90 };
91
92 perfmon: perfmon@80006000 {
93 reg = <0x80006000 0x800>;
94 interrupts = <27>;
95 status = "disabled";
96 };
97
98 gpmi: gpmi-nand@8000c000 {
99 compatible = "fsl,imx28-gpmi-nand";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
103 reg-names = "gpmi-nand", "bch";
104 interrupts = <41>;
105 interrupt-names = "bch";
106 clocks = <&clks 50>;
107 clock-names = "gpmi_io";
108 dmas = <&dma_apbh 4>;
109 dma-names = "rx-tx";
110 status = "disabled";
111 };
112
113 ssp0: ssp@80010000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 reg = <0x80010000 0x2000>;
117 interrupts = <96>;
118 clocks = <&clks 46>;
119 dmas = <&dma_apbh 0>;
120 dma-names = "rx-tx";
121 status = "disabled";
122 };
123
124 ssp1: ssp@80012000 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 reg = <0x80012000 0x2000>;
128 interrupts = <97>;
129 clocks = <&clks 47>;
130 dmas = <&dma_apbh 1>;
131 dma-names = "rx-tx";
132 status = "disabled";
133 };
134
135 ssp2: ssp@80014000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 reg = <0x80014000 0x2000>;
139 interrupts = <98>;
140 clocks = <&clks 48>;
141 dmas = <&dma_apbh 2>;
142 dma-names = "rx-tx";
143 status = "disabled";
144 };
145
146 ssp3: ssp@80016000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 reg = <0x80016000 0x2000>;
150 interrupts = <99>;
151 clocks = <&clks 49>;
152 dmas = <&dma_apbh 3>;
153 dma-names = "rx-tx";
154 status = "disabled";
155 };
156
157 pinctrl: pinctrl@80018000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,imx28-pinctrl", "simple-bus";
161 reg = <0x80018000 0x2000>;
162
163 gpio0: gpio@0 {
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
165 interrupts = <127>;
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
171
172 gpio1: gpio@1 {
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
174 interrupts = <126>;
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 };
180
181 gpio2: gpio@2 {
182 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
183 interrupts = <125>;
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 };
189
190 gpio3: gpio@3 {
191 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
192 interrupts = <124>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 gpio4: gpio@4 {
200 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
201 interrupts = <123>;
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
207
208 duart_pins_a: duart@0 {
209 reg = <0>;
210 fsl,pinmux-ids = <
211 MX28_PAD_PWM0__DUART_RX
212 MX28_PAD_PWM1__DUART_TX
213 >;
214 fsl,drive-strength = <MXS_DRIVE_4mA>;
215 fsl,voltage = <MXS_VOLTAGE_HIGH>;
216 fsl,pull-up = <MXS_PULL_DISABLE>;
217 };
218
219 duart_pins_b: duart@1 {
220 reg = <1>;
221 fsl,pinmux-ids = <
222 MX28_PAD_AUART0_CTS__DUART_RX
223 MX28_PAD_AUART0_RTS__DUART_TX
224 >;
225 fsl,drive-strength = <MXS_DRIVE_4mA>;
226 fsl,voltage = <MXS_VOLTAGE_HIGH>;
227 fsl,pull-up = <MXS_PULL_DISABLE>;
228 };
229
230 duart_4pins_a: duart-4pins@0 {
231 reg = <0>;
232 fsl,pinmux-ids = <
233 MX28_PAD_AUART0_CTS__DUART_RX
234 MX28_PAD_AUART0_RTS__DUART_TX
235 MX28_PAD_AUART0_RX__DUART_CTS
236 MX28_PAD_AUART0_TX__DUART_RTS
237 >;
238 fsl,drive-strength = <MXS_DRIVE_4mA>;
239 fsl,voltage = <MXS_VOLTAGE_HIGH>;
240 fsl,pull-up = <MXS_PULL_DISABLE>;
241 };
242
243 gpmi_pins_a: gpmi-nand@0 {
244 reg = <0>;
245 fsl,pinmux-ids = <
246 MX28_PAD_GPMI_D00__GPMI_D0
247 MX28_PAD_GPMI_D01__GPMI_D1
248 MX28_PAD_GPMI_D02__GPMI_D2
249 MX28_PAD_GPMI_D03__GPMI_D3
250 MX28_PAD_GPMI_D04__GPMI_D4
251 MX28_PAD_GPMI_D05__GPMI_D5
252 MX28_PAD_GPMI_D06__GPMI_D6
253 MX28_PAD_GPMI_D07__GPMI_D7
254 MX28_PAD_GPMI_CE0N__GPMI_CE0N
255 MX28_PAD_GPMI_RDY0__GPMI_READY0
256 MX28_PAD_GPMI_RDN__GPMI_RDN
257 MX28_PAD_GPMI_WRN__GPMI_WRN
258 MX28_PAD_GPMI_ALE__GPMI_ALE
259 MX28_PAD_GPMI_CLE__GPMI_CLE
260 MX28_PAD_GPMI_RESETN__GPMI_RESETN
261 >;
262 fsl,drive-strength = <MXS_DRIVE_4mA>;
263 fsl,voltage = <MXS_VOLTAGE_HIGH>;
264 fsl,pull-up = <MXS_PULL_DISABLE>;
265 };
266
267 gpmi_status_cfg: gpmi-status-cfg {
268 fsl,pinmux-ids = <
269 MX28_PAD_GPMI_RDN__GPMI_RDN
270 MX28_PAD_GPMI_WRN__GPMI_WRN
271 MX28_PAD_GPMI_RESETN__GPMI_RESETN
272 >;
273 fsl,drive-strength = <MXS_DRIVE_12mA>;
274 };
275
276 auart0_pins_a: auart0@0 {
277 reg = <0>;
278 fsl,pinmux-ids = <
279 MX28_PAD_AUART0_RX__AUART0_RX
280 MX28_PAD_AUART0_TX__AUART0_TX
281 MX28_PAD_AUART0_CTS__AUART0_CTS
282 MX28_PAD_AUART0_RTS__AUART0_RTS
283 >;
284 fsl,drive-strength = <MXS_DRIVE_4mA>;
285 fsl,voltage = <MXS_VOLTAGE_HIGH>;
286 fsl,pull-up = <MXS_PULL_DISABLE>;
287 };
288
289 auart0_2pins_a: auart0-2pins@0 {
290 reg = <0>;
291 fsl,pinmux-ids = <
292 MX28_PAD_AUART0_RX__AUART0_RX
293 MX28_PAD_AUART0_TX__AUART0_TX
294 >;
295 fsl,drive-strength = <MXS_DRIVE_4mA>;
296 fsl,voltage = <MXS_VOLTAGE_HIGH>;
297 fsl,pull-up = <MXS_PULL_DISABLE>;
298 };
299
300 auart1_pins_a: auart1@0 {
301 reg = <0>;
302 fsl,pinmux-ids = <
303 MX28_PAD_AUART1_RX__AUART1_RX
304 MX28_PAD_AUART1_TX__AUART1_TX
305 MX28_PAD_AUART1_CTS__AUART1_CTS
306 MX28_PAD_AUART1_RTS__AUART1_RTS
307 >;
308 fsl,drive-strength = <MXS_DRIVE_4mA>;
309 fsl,voltage = <MXS_VOLTAGE_HIGH>;
310 fsl,pull-up = <MXS_PULL_DISABLE>;
311 };
312
313 auart1_2pins_a: auart1-2pins@0 {
314 reg = <0>;
315 fsl,pinmux-ids = <
316 MX28_PAD_AUART1_RX__AUART1_RX
317 MX28_PAD_AUART1_TX__AUART1_TX
318 >;
319 fsl,drive-strength = <MXS_DRIVE_4mA>;
320 fsl,voltage = <MXS_VOLTAGE_HIGH>;
321 fsl,pull-up = <MXS_PULL_DISABLE>;
322 };
323
324 auart2_2pins_a: auart2-2pins@0 {
325 reg = <0>;
326 fsl,pinmux-ids = <
327 MX28_PAD_SSP2_SCK__AUART2_RX
328 MX28_PAD_SSP2_MOSI__AUART2_TX
329 >;
330 fsl,drive-strength = <MXS_DRIVE_4mA>;
331 fsl,voltage = <MXS_VOLTAGE_HIGH>;
332 fsl,pull-up = <MXS_PULL_DISABLE>;
333 };
334
335 auart2_2pins_b: auart2-2pins@1 {
336 reg = <1>;
337 fsl,pinmux-ids = <
338 MX28_PAD_AUART2_RX__AUART2_RX
339 MX28_PAD_AUART2_TX__AUART2_TX
340 >;
341 fsl,drive-strength = <MXS_DRIVE_4mA>;
342 fsl,voltage = <MXS_VOLTAGE_HIGH>;
343 fsl,pull-up = <MXS_PULL_DISABLE>;
344 };
345
346 auart3_pins_a: auart3@0 {
347 reg = <0>;
348 fsl,pinmux-ids = <
349 MX28_PAD_AUART3_RX__AUART3_RX
350 MX28_PAD_AUART3_TX__AUART3_TX
351 MX28_PAD_AUART3_CTS__AUART3_CTS
352 MX28_PAD_AUART3_RTS__AUART3_RTS
353 >;
354 fsl,drive-strength = <MXS_DRIVE_4mA>;
355 fsl,voltage = <MXS_VOLTAGE_HIGH>;
356 fsl,pull-up = <MXS_PULL_DISABLE>;
357 };
358
359 auart3_2pins_a: auart3-2pins@0 {
360 reg = <0>;
361 fsl,pinmux-ids = <
362 MX28_PAD_SSP2_MISO__AUART3_RX
363 MX28_PAD_SSP2_SS0__AUART3_TX
364 >;
365 fsl,drive-strength = <MXS_DRIVE_4mA>;
366 fsl,voltage = <MXS_VOLTAGE_HIGH>;
367 fsl,pull-up = <MXS_PULL_DISABLE>;
368 };
369
370 auart3_2pins_b: auart3-2pins@1 {
371 reg = <1>;
372 fsl,pinmux-ids = <
373 MX28_PAD_AUART3_RX__AUART3_RX
374 MX28_PAD_AUART3_TX__AUART3_TX
375 >;
376 fsl,drive-strength = <MXS_DRIVE_4mA>;
377 fsl,voltage = <MXS_VOLTAGE_HIGH>;
378 fsl,pull-up = <MXS_PULL_DISABLE>;
379 };
380
381 auart4_2pins_a: auart4@0 {
382 reg = <0>;
383 fsl,pinmux-ids = <
384 MX28_PAD_SSP3_SCK__AUART4_TX
385 MX28_PAD_SSP3_MOSI__AUART4_RX
386 >;
387 fsl,drive-strength = <MXS_DRIVE_4mA>;
388 fsl,voltage = <MXS_VOLTAGE_HIGH>;
389 fsl,pull-up = <MXS_PULL_DISABLE>;
390 };
391
392 mac0_pins_a: mac0@0 {
393 reg = <0>;
394 fsl,pinmux-ids = <
395 MX28_PAD_ENET0_MDC__ENET0_MDC
396 MX28_PAD_ENET0_MDIO__ENET0_MDIO
397 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
398 MX28_PAD_ENET0_RXD0__ENET0_RXD0
399 MX28_PAD_ENET0_RXD1__ENET0_RXD1
400 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
401 MX28_PAD_ENET0_TXD0__ENET0_TXD0
402 MX28_PAD_ENET0_TXD1__ENET0_TXD1
403 MX28_PAD_ENET_CLK__CLKCTRL_ENET
404 >;
405 fsl,drive-strength = <MXS_DRIVE_8mA>;
406 fsl,voltage = <MXS_VOLTAGE_HIGH>;
407 fsl,pull-up = <MXS_PULL_ENABLE>;
408 };
409
410 mac1_pins_a: mac1@0 {
411 reg = <0>;
412 fsl,pinmux-ids = <
413 MX28_PAD_ENET0_CRS__ENET1_RX_EN
414 MX28_PAD_ENET0_RXD2__ENET1_RXD0
415 MX28_PAD_ENET0_RXD3__ENET1_RXD1
416 MX28_PAD_ENET0_COL__ENET1_TX_EN
417 MX28_PAD_ENET0_TXD2__ENET1_TXD0
418 MX28_PAD_ENET0_TXD3__ENET1_TXD1
419 >;
420 fsl,drive-strength = <MXS_DRIVE_8mA>;
421 fsl,voltage = <MXS_VOLTAGE_HIGH>;
422 fsl,pull-up = <MXS_PULL_ENABLE>;
423 };
424
425 mmc0_8bit_pins_a: mmc0-8bit@0 {
426 reg = <0>;
427 fsl,pinmux-ids = <
428 MX28_PAD_SSP0_DATA0__SSP0_D0
429 MX28_PAD_SSP0_DATA1__SSP0_D1
430 MX28_PAD_SSP0_DATA2__SSP0_D2
431 MX28_PAD_SSP0_DATA3__SSP0_D3
432 MX28_PAD_SSP0_DATA4__SSP0_D4
433 MX28_PAD_SSP0_DATA5__SSP0_D5
434 MX28_PAD_SSP0_DATA6__SSP0_D6
435 MX28_PAD_SSP0_DATA7__SSP0_D7
436 MX28_PAD_SSP0_CMD__SSP0_CMD
437 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
438 MX28_PAD_SSP0_SCK__SSP0_SCK
439 >;
440 fsl,drive-strength = <MXS_DRIVE_8mA>;
441 fsl,voltage = <MXS_VOLTAGE_HIGH>;
442 fsl,pull-up = <MXS_PULL_ENABLE>;
443 };
444
445 mmc0_4bit_pins_a: mmc0-4bit@0 {
446 reg = <0>;
447 fsl,pinmux-ids = <
448 MX28_PAD_SSP0_DATA0__SSP0_D0
449 MX28_PAD_SSP0_DATA1__SSP0_D1
450 MX28_PAD_SSP0_DATA2__SSP0_D2
451 MX28_PAD_SSP0_DATA3__SSP0_D3
452 MX28_PAD_SSP0_CMD__SSP0_CMD
453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
454 MX28_PAD_SSP0_SCK__SSP0_SCK
455 >;
456 fsl,drive-strength = <MXS_DRIVE_8mA>;
457 fsl,voltage = <MXS_VOLTAGE_HIGH>;
458 fsl,pull-up = <MXS_PULL_ENABLE>;
459 };
460
461 mmc0_cd_cfg: mmc0-cd-cfg {
462 fsl,pinmux-ids = <
463 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
464 >;
465 fsl,pull-up = <MXS_PULL_DISABLE>;
466 };
467
468 mmc0_sck_cfg: mmc0-sck-cfg {
469 fsl,pinmux-ids = <
470 MX28_PAD_SSP0_SCK__SSP0_SCK
471 >;
472 fsl,drive-strength = <MXS_DRIVE_12mA>;
473 fsl,pull-up = <MXS_PULL_DISABLE>;
474 };
475
476 mmc2_4bit_pins_a: mmc2-4bit@0 {
477 reg = <0>;
478 fsl,pinmux-ids = <
479 MX28_PAD_SSP0_DATA4__SSP2_D0
480 MX28_PAD_SSP1_SCK__SSP2_D1
481 MX28_PAD_SSP1_CMD__SSP2_D2
482 MX28_PAD_SSP0_DATA5__SSP2_D3
483 MX28_PAD_SSP0_DATA6__SSP2_CMD
484 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
485 MX28_PAD_SSP0_DATA7__SSP2_SCK
486 >;
487 fsl,drive-strength = <MXS_DRIVE_8mA>;
488 fsl,voltage = <MXS_VOLTAGE_HIGH>;
489 fsl,pull-up = <MXS_PULL_ENABLE>;
490 };
491
492 mmc2_cd_cfg: mmc2-cd-cfg {
493 fsl,pinmux-ids = <
494 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
495 >;
496 fsl,pull-up = <MXS_PULL_DISABLE>;
497 };
498
499 mmc2_sck_cfg: mmc2-sck-cfg {
500 fsl,pinmux-ids = <
501 MX28_PAD_SSP0_DATA7__SSP2_SCK
502 >;
503 fsl,drive-strength = <MXS_DRIVE_12mA>;
504 fsl,pull-up = <MXS_PULL_DISABLE>;
505 };
506
507 i2c0_pins_a: i2c0@0 {
508 reg = <0>;
509 fsl,pinmux-ids = <
510 MX28_PAD_I2C0_SCL__I2C0_SCL
511 MX28_PAD_I2C0_SDA__I2C0_SDA
512 >;
513 fsl,drive-strength = <MXS_DRIVE_8mA>;
514 fsl,voltage = <MXS_VOLTAGE_HIGH>;
515 fsl,pull-up = <MXS_PULL_ENABLE>;
516 };
517
518 i2c0_pins_b: i2c0@1 {
519 reg = <1>;
520 fsl,pinmux-ids = <
521 MX28_PAD_AUART0_RX__I2C0_SCL
522 MX28_PAD_AUART0_TX__I2C0_SDA
523 >;
524 fsl,drive-strength = <MXS_DRIVE_8mA>;
525 fsl,voltage = <MXS_VOLTAGE_HIGH>;
526 fsl,pull-up = <MXS_PULL_ENABLE>;
527 };
528
529 i2c1_pins_a: i2c1@0 {
530 reg = <0>;
531 fsl,pinmux-ids = <
532 MX28_PAD_PWM0__I2C1_SCL
533 MX28_PAD_PWM1__I2C1_SDA
534 >;
535 fsl,drive-strength = <MXS_DRIVE_8mA>;
536 fsl,voltage = <MXS_VOLTAGE_HIGH>;
537 fsl,pull-up = <MXS_PULL_ENABLE>;
538 };
539
540 saif0_pins_a: saif0@0 {
541 reg = <0>;
542 fsl,pinmux-ids = <
543 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
544 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
545 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
546 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
547 >;
548 fsl,drive-strength = <MXS_DRIVE_12mA>;
549 fsl,voltage = <MXS_VOLTAGE_HIGH>;
550 fsl,pull-up = <MXS_PULL_ENABLE>;
551 };
552
553 saif0_pins_b: saif0@1 {
554 reg = <1>;
555 fsl,pinmux-ids = <
556 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
557 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
558 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
559 >;
560 fsl,drive-strength = <MXS_DRIVE_12mA>;
561 fsl,voltage = <MXS_VOLTAGE_HIGH>;
562 fsl,pull-up = <MXS_PULL_ENABLE>;
563 };
564
565 saif1_pins_a: saif1@0 {
566 reg = <0>;
567 fsl,pinmux-ids = <
568 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
569 >;
570 fsl,drive-strength = <MXS_DRIVE_12mA>;
571 fsl,voltage = <MXS_VOLTAGE_HIGH>;
572 fsl,pull-up = <MXS_PULL_ENABLE>;
573 };
574
575 pwm0_pins_a: pwm0@0 {
576 reg = <0>;
577 fsl,pinmux-ids = <
578 MX28_PAD_PWM0__PWM_0
579 >;
580 fsl,drive-strength = <MXS_DRIVE_4mA>;
581 fsl,voltage = <MXS_VOLTAGE_HIGH>;
582 fsl,pull-up = <MXS_PULL_DISABLE>;
583 };
584
585 pwm2_pins_a: pwm2@0 {
586 reg = <0>;
587 fsl,pinmux-ids = <
588 MX28_PAD_PWM2__PWM_2
589 >;
590 fsl,drive-strength = <MXS_DRIVE_4mA>;
591 fsl,voltage = <MXS_VOLTAGE_HIGH>;
592 fsl,pull-up = <MXS_PULL_DISABLE>;
593 };
594
595 pwm3_pins_a: pwm3@0 {
596 reg = <0>;
597 fsl,pinmux-ids = <
598 MX28_PAD_PWM3__PWM_3
599 >;
600 fsl,drive-strength = <MXS_DRIVE_4mA>;
601 fsl,voltage = <MXS_VOLTAGE_HIGH>;
602 fsl,pull-up = <MXS_PULL_DISABLE>;
603 };
604
605 pwm3_pins_b: pwm3@1 {
606 reg = <1>;
607 fsl,pinmux-ids = <
608 MX28_PAD_SAIF0_MCLK__PWM_3
609 >;
610 fsl,drive-strength = <MXS_DRIVE_4mA>;
611 fsl,voltage = <MXS_VOLTAGE_HIGH>;
612 fsl,pull-up = <MXS_PULL_DISABLE>;
613 };
614
615 pwm4_pins_a: pwm4@0 {
616 reg = <0>;
617 fsl,pinmux-ids = <
618 MX28_PAD_PWM4__PWM_4
619 >;
620 fsl,drive-strength = <MXS_DRIVE_4mA>;
621 fsl,voltage = <MXS_VOLTAGE_HIGH>;
622 fsl,pull-up = <MXS_PULL_DISABLE>;
623 };
624
625 lcdif_24bit_pins_a: lcdif-24bit@0 {
626 reg = <0>;
627 fsl,pinmux-ids = <
628 MX28_PAD_LCD_D00__LCD_D0
629 MX28_PAD_LCD_D01__LCD_D1
630 MX28_PAD_LCD_D02__LCD_D2
631 MX28_PAD_LCD_D03__LCD_D3
632 MX28_PAD_LCD_D04__LCD_D4
633 MX28_PAD_LCD_D05__LCD_D5
634 MX28_PAD_LCD_D06__LCD_D6
635 MX28_PAD_LCD_D07__LCD_D7
636 MX28_PAD_LCD_D08__LCD_D8
637 MX28_PAD_LCD_D09__LCD_D9
638 MX28_PAD_LCD_D10__LCD_D10
639 MX28_PAD_LCD_D11__LCD_D11
640 MX28_PAD_LCD_D12__LCD_D12
641 MX28_PAD_LCD_D13__LCD_D13
642 MX28_PAD_LCD_D14__LCD_D14
643 MX28_PAD_LCD_D15__LCD_D15
644 MX28_PAD_LCD_D16__LCD_D16
645 MX28_PAD_LCD_D17__LCD_D17
646 MX28_PAD_LCD_D18__LCD_D18
647 MX28_PAD_LCD_D19__LCD_D19
648 MX28_PAD_LCD_D20__LCD_D20
649 MX28_PAD_LCD_D21__LCD_D21
650 MX28_PAD_LCD_D22__LCD_D22
651 MX28_PAD_LCD_D23__LCD_D23
652 >;
653 fsl,drive-strength = <MXS_DRIVE_4mA>;
654 fsl,voltage = <MXS_VOLTAGE_HIGH>;
655 fsl,pull-up = <MXS_PULL_DISABLE>;
656 };
657
658 lcdif_16bit_pins_a: lcdif-16bit@0 {
659 reg = <0>;
660 fsl,pinmux-ids = <
661 MX28_PAD_LCD_D00__LCD_D0
662 MX28_PAD_LCD_D01__LCD_D1
663 MX28_PAD_LCD_D02__LCD_D2
664 MX28_PAD_LCD_D03__LCD_D3
665 MX28_PAD_LCD_D04__LCD_D4
666 MX28_PAD_LCD_D05__LCD_D5
667 MX28_PAD_LCD_D06__LCD_D6
668 MX28_PAD_LCD_D07__LCD_D7
669 MX28_PAD_LCD_D08__LCD_D8
670 MX28_PAD_LCD_D09__LCD_D9
671 MX28_PAD_LCD_D10__LCD_D10
672 MX28_PAD_LCD_D11__LCD_D11
673 MX28_PAD_LCD_D12__LCD_D12
674 MX28_PAD_LCD_D13__LCD_D13
675 MX28_PAD_LCD_D14__LCD_D14
676 MX28_PAD_LCD_D15__LCD_D15
677 >;
678 fsl,drive-strength = <MXS_DRIVE_4mA>;
679 fsl,voltage = <MXS_VOLTAGE_HIGH>;
680 fsl,pull-up = <MXS_PULL_DISABLE>;
681 };
682
683 lcdif_sync_pins_a: lcdif-sync@0 {
684 reg = <0>;
685 fsl,pinmux-ids = <
686 MX28_PAD_LCD_RS__LCD_DOTCLK
687 MX28_PAD_LCD_CS__LCD_ENABLE
688 MX28_PAD_LCD_RD_E__LCD_VSYNC
689 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
690 >;
691 fsl,drive-strength = <MXS_DRIVE_4mA>;
692 fsl,voltage = <MXS_VOLTAGE_HIGH>;
693 fsl,pull-up = <MXS_PULL_DISABLE>;
694 };
695
696 can0_pins_a: can0@0 {
697 reg = <0>;
698 fsl,pinmux-ids = <
699 MX28_PAD_GPMI_RDY2__CAN0_TX
700 MX28_PAD_GPMI_RDY3__CAN0_RX
701 >;
702 fsl,drive-strength = <MXS_DRIVE_4mA>;
703 fsl,voltage = <MXS_VOLTAGE_HIGH>;
704 fsl,pull-up = <MXS_PULL_DISABLE>;
705 };
706
707 can1_pins_a: can1@0 {
708 reg = <0>;
709 fsl,pinmux-ids = <
710 MX28_PAD_GPMI_CE2N__CAN1_TX
711 MX28_PAD_GPMI_CE3N__CAN1_RX
712 >;
713 fsl,drive-strength = <MXS_DRIVE_4mA>;
714 fsl,voltage = <MXS_VOLTAGE_HIGH>;
715 fsl,pull-up = <MXS_PULL_DISABLE>;
716 };
717
718 spi2_pins_a: spi2@0 {
719 reg = <0>;
720 fsl,pinmux-ids = <
721 MX28_PAD_SSP2_SCK__SSP2_SCK
722 MX28_PAD_SSP2_MOSI__SSP2_CMD
723 MX28_PAD_SSP2_MISO__SSP2_D0
724 MX28_PAD_SSP2_SS0__SSP2_D3
725 >;
726 fsl,drive-strength = <MXS_DRIVE_8mA>;
727 fsl,voltage = <MXS_VOLTAGE_HIGH>;
728 fsl,pull-up = <MXS_PULL_ENABLE>;
729 };
730
731 spi3_pins_a: spi3@0 {
732 reg = <0>;
733 fsl,pinmux-ids = <
734 MX28_PAD_AUART2_RX__SSP3_D4
735 MX28_PAD_AUART2_TX__SSP3_D5
736 MX28_PAD_SSP3_SCK__SSP3_SCK
737 MX28_PAD_SSP3_MOSI__SSP3_CMD
738 MX28_PAD_SSP3_MISO__SSP3_D0
739 MX28_PAD_SSP3_SS0__SSP3_D3
740 >;
741 fsl,drive-strength = <MXS_DRIVE_8mA>;
742 fsl,voltage = <MXS_VOLTAGE_HIGH>;
743 fsl,pull-up = <MXS_PULL_DISABLE>;
744 };
745
746 usbphy0_pins_a: usbphy0@0 {
747 reg = <0>;
748 fsl,pinmux-ids = <
749 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
750 >;
751 fsl,drive-strength = <MXS_DRIVE_12mA>;
752 fsl,voltage = <MXS_VOLTAGE_HIGH>;
753 fsl,pull-up = <MXS_PULL_DISABLE>;
754 };
755
756 usbphy0_pins_b: usbphy0@1 {
757 reg = <1>;
758 fsl,pinmux-ids = <
759 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
760 >;
761 fsl,drive-strength = <MXS_DRIVE_12mA>;
762 fsl,voltage = <MXS_VOLTAGE_HIGH>;
763 fsl,pull-up = <MXS_PULL_DISABLE>;
764 };
765
766 usbphy1_pins_a: usbphy1@0 {
767 reg = <0>;
768 fsl,pinmux-ids = <
769 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
770 >;
771 fsl,drive-strength = <MXS_DRIVE_12mA>;
772 fsl,voltage = <MXS_VOLTAGE_HIGH>;
773 fsl,pull-up = <MXS_PULL_DISABLE>;
774 };
775
776 usb0_id_pins_a: usb0id@0 {
777 reg = <0>;
778 fsl,pinmux-ids = <
779 MX28_PAD_AUART1_RTS__USB0_ID
780 >;
781 fsl,drive-strength = <MXS_DRIVE_12mA>;
782 fsl,voltage = <MXS_VOLTAGE_HIGH>;
783 fsl,pull-up = <MXS_PULL_ENABLE>;
784 };
785 };
786
787 digctl: digctl@8001c000 {
788 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
789 reg = <0x8001c000 0x2000>;
790 interrupts = <89>;
791 status = "disabled";
792 };
793
794 etm: etm@80022000 {
795 reg = <0x80022000 0x2000>;
796 status = "disabled";
797 };
798
799 dma_apbx: dma-apbx@80024000 {
800 compatible = "fsl,imx28-dma-apbx";
801 reg = <0x80024000 0x2000>;
802 interrupts = <78 79 66 0
803 80 81 68 69
804 70 71 72 73
805 74 75 76 77>;
806 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
807 "saif0", "saif1", "i2c0", "i2c1",
808 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
809 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
810 #dma-cells = <1>;
811 dma-channels = <16>;
812 clocks = <&clks 26>;
813 };
814
815 dcp: dcp@80028000 {
816 reg = <0x80028000 0x2000>;
817 interrupts = <52 53 54>;
818 compatible = "fsl-dcp";
819 };
820
821 pxp: pxp@8002a000 {
822 reg = <0x8002a000 0x2000>;
823 interrupts = <39>;
824 status = "disabled";
825 };
826
827 ocotp: ocotp@8002c000 {
828 compatible = "fsl,ocotp";
829 reg = <0x8002c000 0x2000>;
830 status = "disabled";
831 };
832
833 axi-ahb@8002e000 {
834 reg = <0x8002e000 0x2000>;
835 status = "disabled";
836 };
837
838 lcdif: lcdif@80030000 {
839 compatible = "fsl,imx28-lcdif";
840 reg = <0x80030000 0x2000>;
841 interrupts = <38>;
842 clocks = <&clks 55>;
843 dmas = <&dma_apbh 13>;
844 dma-names = "rx";
845 status = "disabled";
846 };
847
848 can0: can@80032000 {
849 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
850 reg = <0x80032000 0x2000>;
851 interrupts = <8>;
852 clocks = <&clks 58>, <&clks 58>;
853 clock-names = "ipg", "per";
854 status = "disabled";
855 };
856
857 can1: can@80034000 {
858 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
859 reg = <0x80034000 0x2000>;
860 interrupts = <9>;
861 clocks = <&clks 59>, <&clks 59>;
862 clock-names = "ipg", "per";
863 status = "disabled";
864 };
865
866 simdbg: simdbg@8003c000 {
867 reg = <0x8003c000 0x200>;
868 status = "disabled";
869 };
870
871 simgpmisel: simgpmisel@8003c200 {
872 reg = <0x8003c200 0x100>;
873 status = "disabled";
874 };
875
876 simsspsel: simsspsel@8003c300 {
877 reg = <0x8003c300 0x100>;
878 status = "disabled";
879 };
880
881 simmemsel: simmemsel@8003c400 {
882 reg = <0x8003c400 0x100>;
883 status = "disabled";
884 };
885
886 gpiomon: gpiomon@8003c500 {
887 reg = <0x8003c500 0x100>;
888 status = "disabled";
889 };
890
891 simenet: simenet@8003c700 {
892 reg = <0x8003c700 0x100>;
893 status = "disabled";
894 };
895
896 armjtag: armjtag@8003c800 {
897 reg = <0x8003c800 0x100>;
898 status = "disabled";
899 };
900 };
901
902 apbx@80040000 {
903 compatible = "simple-bus";
904 #address-cells = <1>;
905 #size-cells = <1>;
906 reg = <0x80040000 0x40000>;
907 ranges;
908
909 clks: clkctrl@80040000 {
910 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
911 reg = <0x80040000 0x2000>;
912 #clock-cells = <1>;
913 };
914
915 saif0: saif@80042000 {
916 compatible = "fsl,imx28-saif";
917 reg = <0x80042000 0x2000>;
918 interrupts = <59>;
919 #clock-cells = <0>;
920 clocks = <&clks 53>;
921 dmas = <&dma_apbx 4>;
922 dma-names = "rx-tx";
923 status = "disabled";
924 };
925
926 power: power@80044000 {
927 reg = <0x80044000 0x2000>;
928 status = "disabled";
929 };
930
931 saif1: saif@80046000 {
932 compatible = "fsl,imx28-saif";
933 reg = <0x80046000 0x2000>;
934 interrupts = <58>;
935 clocks = <&clks 54>;
936 dmas = <&dma_apbx 5>;
937 dma-names = "rx-tx";
938 status = "disabled";
939 };
940
941 lradc: lradc@80050000 {
942 compatible = "fsl,imx28-lradc";
943 reg = <0x80050000 0x2000>;
944 interrupts = <10 14 15 16 17 18 19
945 20 21 22 23 24 25>;
946 status = "disabled";
947 clocks = <&clks 41>;
948 };
949
950 spdif: spdif@80054000 {
951 reg = <0x80054000 0x2000>;
952 interrupts = <45>;
953 dmas = <&dma_apbx 2>;
954 dma-names = "tx";
955 status = "disabled";
956 };
957
958 mxs_rtc: rtc@80056000 {
959 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
960 reg = <0x80056000 0x2000>;
961 interrupts = <29>;
962 };
963
964 i2c0: i2c@80058000 {
965 #address-cells = <1>;
966 #size-cells = <0>;
967 compatible = "fsl,imx28-i2c";
968 reg = <0x80058000 0x2000>;
969 interrupts = <111>;
970 clock-frequency = <100000>;
971 dmas = <&dma_apbx 6>;
972 dma-names = "rx-tx";
973 status = "disabled";
974 };
975
976 i2c1: i2c@8005a000 {
977 #address-cells = <1>;
978 #size-cells = <0>;
979 compatible = "fsl,imx28-i2c";
980 reg = <0x8005a000 0x2000>;
981 interrupts = <110>;
982 clock-frequency = <100000>;
983 dmas = <&dma_apbx 7>;
984 dma-names = "rx-tx";
985 status = "disabled";
986 };
987
988 pwm: pwm@80064000 {
989 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
990 reg = <0x80064000 0x2000>;
991 clocks = <&clks 44>;
992 #pwm-cells = <2>;
993 fsl,pwm-number = <8>;
994 status = "disabled";
995 };
996
997 timer: timrot@80068000 {
998 compatible = "fsl,imx28-timrot", "fsl,timrot";
999 reg = <0x80068000 0x2000>;
1000 interrupts = <48 49 50 51>;
1001 clocks = <&clks 26>;
1002 };
1003
1004 auart0: serial@8006a000 {
1005 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1006 reg = <0x8006a000 0x2000>;
1007 interrupts = <112>;
1008 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1009 dma-names = "rx", "tx";
1010 clocks = <&clks 45>;
1011 status = "disabled";
1012 };
1013
1014 auart1: serial@8006c000 {
1015 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1016 reg = <0x8006c000 0x2000>;
1017 interrupts = <113>;
1018 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1019 dma-names = "rx", "tx";
1020 clocks = <&clks 45>;
1021 status = "disabled";
1022 };
1023
1024 auart2: serial@8006e000 {
1025 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1026 reg = <0x8006e000 0x2000>;
1027 interrupts = <114>;
1028 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1029 dma-names = "rx", "tx";
1030 clocks = <&clks 45>;
1031 status = "disabled";
1032 };
1033
1034 auart3: serial@80070000 {
1035 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1036 reg = <0x80070000 0x2000>;
1037 interrupts = <115>;
1038 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1039 dma-names = "rx", "tx";
1040 clocks = <&clks 45>;
1041 status = "disabled";
1042 };
1043
1044 auart4: serial@80072000 {
1045 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1046 reg = <0x80072000 0x2000>;
1047 interrupts = <116>;
1048 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1049 dma-names = "rx", "tx";
1050 clocks = <&clks 45>;
1051 status = "disabled";
1052 };
1053
1054 duart: serial@80074000 {
1055 compatible = "arm,pl011", "arm,primecell";
1056 reg = <0x80074000 0x1000>;
1057 interrupts = <47>;
1058 clocks = <&clks 45>, <&clks 26>;
1059 clock-names = "uart", "apb_pclk";
1060 status = "disabled";
1061 };
1062
1063 usbphy0: usbphy@8007c000 {
1064 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1065 reg = <0x8007c000 0x2000>;
1066 clocks = <&clks 62>;
1067 status = "disabled";
1068 };
1069
1070 usbphy1: usbphy@8007e000 {
1071 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1072 reg = <0x8007e000 0x2000>;
1073 clocks = <&clks 63>;
1074 status = "disabled";
1075 };
1076 };
1077 };
1078
1079 ahb@80080000 {
1080 compatible = "simple-bus";
1081 #address-cells = <1>;
1082 #size-cells = <1>;
1083 reg = <0x80080000 0x80000>;
1084 ranges;
1085
1086 usb0: usb@80080000 {
1087 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1088 reg = <0x80080000 0x10000>;
1089 interrupts = <93>;
1090 clocks = <&clks 60>;
1091 fsl,usbphy = <&usbphy0>;
1092 status = "disabled";
1093 };
1094
1095 usb1: usb@80090000 {
1096 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1097 reg = <0x80090000 0x10000>;
1098 interrupts = <92>;
1099 clocks = <&clks 61>;
1100 fsl,usbphy = <&usbphy1>;
1101 status = "disabled";
1102 };
1103
1104 dflpt: dflpt@800c0000 {
1105 reg = <0x800c0000 0x10000>;
1106 status = "disabled";
1107 };
1108
1109 mac0: ethernet@800f0000 {
1110 compatible = "fsl,imx28-fec";
1111 reg = <0x800f0000 0x4000>;
1112 interrupts = <101>;
1113 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1114 clock-names = "ipg", "ahb", "enet_out";
1115 status = "disabled";
1116 };
1117
1118 mac1: ethernet@800f4000 {
1119 compatible = "fsl,imx28-fec";
1120 reg = <0x800f4000 0x4000>;
1121 interrupts = <102>;
1122 clocks = <&clks 57>, <&clks 57>;
1123 clock-names = "ipg", "ahb";
1124 status = "disabled";
1125 };
1126
1127 etn_switch: switch@800f8000 {
1128 reg = <0x800f8000 0x8000>;
1129 status = "disabled";
1130 };
1131 };
1132 };
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