arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "imx53-pinfunc.h"
  14 #include <dt-bindings/clock/imx5-clock.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/input/input.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 / {
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         aliases {
  24                 ethernet0 = &fec;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 gpio5 = &gpio6;
  31                 gpio6 = &gpio7;
  32                 i2c0 = &i2c1;
  33                 i2c1 = &i2c2;
  34                 i2c2 = &i2c3;
  35                 mmc0 = &esdhc1;
  36                 mmc1 = &esdhc2;
  37                 mmc2 = &esdhc3;
  38                 mmc3 = &esdhc4;
  39                 serial0 = &uart1;
  40                 serial1 = &uart2;
  41                 serial2 = &uart3;
  42                 serial3 = &uart4;
  43                 serial4 = &uart5;
  44                 spi0 = &ecspi1;
  45                 spi1 = &ecspi2;
  46                 spi2 = &cspi;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52                 cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a8";
  55                         reg = <0x0>;
  56                         clocks = <&clks IMX5_CLK_ARM>;
  57                         clock-latency = <61036>;
  58                         voltage-tolerance = <5>;
  59                         operating-points = <
  60                                 /* kHz */
  61                                  166666  850000
  62                                  400000  900000
  63                                  800000 1050000
  64                                 1000000 1200000
  65                                 1200000 1300000
  66                         >;
  67                 };
  68         };
  69
  70         display-subsystem {
  71                 compatible = "fsl,imx-display-subsystem";
  72                 ports = <&ipu_di0>, <&ipu_di1>;
  73         };
  74
  75         tzic: tz-interrupt-controller@0fffc000 {
  76                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  77                 interrupt-controller;
  78                 #interrupt-cells = <1>;
  79                 reg = <0x0fffc000 0x4000>;
  80         };
  81
  82         clocks {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85
  86                 ckil {
  87                         compatible = "fsl,imx-ckil", "fixed-clock";
  88                         #clock-cells = <0>;
  89                         clock-frequency = <32768>;
  90                 };
  91
  92                 ckih1 {
  93                         compatible = "fsl,imx-ckih1", "fixed-clock";
  94                         #clock-cells = <0>;
  95                         clock-frequency = <22579200>;
  96                 };
  97
  98                 ckih2 {
  99                         compatible = "fsl,imx-ckih2", "fixed-clock";
 100                         #clock-cells = <0>;
 101                         clock-frequency = <0>;
 102                 };
 103
 104                 osc {
 105                         compatible = "fsl,imx-osc", "fixed-clock";
 106                         #clock-cells = <0>;
 107                         clock-frequency = <24000000>;
 108                 };
 109         };
 110
 111         soc {
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 compatible = "simple-bus";
 115                 interrupt-parent = <&tzic>;
 116                 ranges;
 117
 118                 sata: sata@10000000 {
 119                         compatible = "fsl,imx53-ahci";
 120                         reg = <0x10000000 0x1000>;
 121                         interrupts = <28>;
 122                         clocks = <&clks IMX5_CLK_SATA_GATE>,
 123                                  <&clks IMX5_CLK_SATA_REF>,
 124                                  <&clks IMX5_CLK_AHB>;
 125                         clock-names = "sata", "sata_ref", "ahb";
 126                         status = "disabled";
 127                 };
 128
 129                 ipu: ipu@18000000 {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         compatible = "fsl,imx53-ipu";
 133                         reg = <0x18000000 0x08000000>;
 134                         interrupts = <11 10>;
 135                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 136                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 137                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 138                         clock-names = "bus", "di0", "di1";
 139                         resets = <&src 2>;
 140
 141                         ipu_csi0: port@0 {
 142                                 reg = <0>;
 143                         };
 144
 145                         ipu_csi1: port@1 {
 146                                 reg = <1>;
 147                         };
 148
 149                         ipu_di0: port@2 {
 150                                 #address-cells = <1>;
 151                                 #size-cells = <0>;
 152                                 reg = <2>;
 153
 154                                 ipu_di0_disp0: endpoint@0 {
 155                                         reg = <0>;
 156                                 };
 157
 158                                 ipu_di0_lvds0: endpoint@1 {
 159                                         reg = <1>;
 160                                         remote-endpoint = <&lvds0_in>;
 161                                 };
 162                         };
 163
 164                         ipu_di1: port@3 {
 165                                 #address-cells = <1>;
 166                                 #size-cells = <0>;
 167                                 reg = <3>;
 168
 169                                 ipu_di1_disp1: endpoint@0 {
 170                                         reg = <0>;
 171                                 };
 172
 173                                 ipu_di1_lvds1: endpoint@1 {
 174                                         reg = <1>;
 175                                         remote-endpoint = <&lvds1_in>;
 176                                 };
 177
 178                                 ipu_di1_tve: endpoint@2 {
 179                                         reg = <2>;
 180                                         remote-endpoint = <&tve_in>;
 181                                 };
 182                         };
 183                 };
 184
 185                 aips@50000000 { /* AIPS1 */
 186                         compatible = "fsl,aips-bus", "simple-bus";
 187                         #address-cells = <1>;
 188                         #size-cells = <1>;
 189                         reg = <0x50000000 0x10000000>;
 190                         ranges;
 191
 192                         spba@50000000 {
 193                                 compatible = "fsl,spba-bus", "simple-bus";
 194                                 #address-cells = <1>;
 195                                 #size-cells = <1>;
 196                                 reg = <0x50000000 0x40000>;
 197                                 ranges;
 198
 199                                 esdhc1: esdhc@50004000 {
 200                                         compatible = "fsl,imx53-esdhc";
 201                                         reg = <0x50004000 0x4000>;
 202                                         interrupts = <1>;
 203                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 204                                                  <&clks IMX5_CLK_DUMMY>,
 205                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 206                                         clock-names = "ipg", "ahb", "per";
 207                                         bus-width = <4>;
 208                                         status = "disabled";
 209                                 };
 210
 211                                 esdhc2: esdhc@50008000 {
 212                                         compatible = "fsl,imx53-esdhc";
 213                                         reg = <0x50008000 0x4000>;
 214                                         interrupts = <2>;
 215                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 216                                                  <&clks IMX5_CLK_DUMMY>,
 217                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 218                                         clock-names = "ipg", "ahb", "per";
 219                                         bus-width = <4>;
 220                                         status = "disabled";
 221                                 };
 222
 223                                 uart3: serial@5000c000 {
 224                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 225                                         reg = <0x5000c000 0x4000>;
 226                                         interrupts = <33>;
 227                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 228                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 229                                         clock-names = "ipg", "per";
 230                                         dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
 231                                         dma-names = "rx", "tx";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 ecspi1: ecspi@50010000 {
 236                                         #address-cells = <1>;
 237                                         #size-cells = <0>;
 238                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 239                                         reg = <0x50010000 0x4000>;
 240                                         interrupts = <36>;
 241                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 242                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 243                                         clock-names = "ipg", "per";
 244                                         status = "disabled";
 245                                 };
 246
 247                                 ssi2: ssi@50014000 {
 248                                         #sound-dai-cells = <0>;
 249                                         compatible = "fsl,imx53-ssi",
 250                                                         "fsl,imx51-ssi",
 251                                                         "fsl,imx21-ssi";
 252                                         reg = <0x50014000 0x4000>;
 253                                         interrupts = <30>;
 254                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
 255                                                  <&clks IMX5_CLK_SSI2_ROOT_GATE>;
 256                                         clock-names = "ipg", "baud";
 257                                         dmas = <&sdma 24 1 0>,
 258                                                <&sdma 25 1 0>;
 259                                         dma-names = "rx", "tx";
 260                                         fsl,fifo-depth = <15>;
 261                                         status = "disabled";
 262                                 };
 263
 264                                 esdhc3: esdhc@50020000 {
 265                                         compatible = "fsl,imx53-esdhc";
 266                                         reg = <0x50020000 0x4000>;
 267                                         interrupts = <3>;
 268                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 269                                                  <&clks IMX5_CLK_DUMMY>,
 270                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 271                                         clock-names = "ipg", "ahb", "per";
 272                                         bus-width = <4>;
 273                                         status = "disabled";
 274                                 };
 275
 276                                 esdhc4: esdhc@50024000 {
 277                                         compatible = "fsl,imx53-esdhc";
 278                                         reg = <0x50024000 0x4000>;
 279                                         interrupts = <4>;
 280                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 281                                                  <&clks IMX5_CLK_DUMMY>,
 282                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 283                                         clock-names = "ipg", "ahb", "per";
 284                                         bus-width = <4>;
 285                                         status = "disabled";
 286                                 };
 287                         };
 288
 289                         aipstz1: bridge@53f00000 {
 290                                 compatible = "fsl,imx53-aipstz";
 291                                 reg = <0x53f00000 0x60>;
 292                         };
 293
 294                         usbphy0: usbphy@0 {
 295                                 compatible = "usb-nop-xceiv";
 296                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 297                                 clock-names = "main_clk";
 298                                 status = "okay";
 299                         };
 300
 301                         usbphy1: usbphy@1 {
 302                                 compatible = "usb-nop-xceiv";
 303                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 304                                 clock-names = "main_clk";
 305                                 status = "okay";
 306                         };
 307
 308                         usbotg: usb@53f80000 {
 309                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 310                                 reg = <0x53f80000 0x0200>;
 311                                 interrupts = <18>;
 312                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 313                                 fsl,usbmisc = <&usbmisc 0>;
 314                                 fsl,usbphy = <&usbphy0>;
 315                                 status = "disabled";
 316                         };
 317
 318                         usbh1: usb@53f80200 {
 319                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 320                                 reg = <0x53f80200 0x0200>;
 321                                 interrupts = <14>;
 322                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 323                                 fsl,usbmisc = <&usbmisc 1>;
 324                                 fsl,usbphy = <&usbphy1>;
 325                                 dr_mode = "host";
 326                                 status = "disabled";
 327                         };
 328
 329                         usbh2: usb@53f80400 {
 330                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 331                                 reg = <0x53f80400 0x0200>;
 332                                 interrupts = <16>;
 333                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 334                                 fsl,usbmisc = <&usbmisc 2>;
 335                                 dr_mode = "host";
 336                                 status = "disabled";
 337                         };
 338
 339                         usbh3: usb@53f80600 {
 340                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 341                                 reg = <0x53f80600 0x0200>;
 342                                 interrupts = <17>;
 343                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 344                                 fsl,usbmisc = <&usbmisc 3>;
 345                                 dr_mode = "host";
 346                                 status = "disabled";
 347                         };
 348
 349                         usbmisc: usbmisc@53f80800 {
 350                                 #index-cells = <1>;
 351                                 compatible = "fsl,imx53-usbmisc";
 352                                 reg = <0x53f80800 0x200>;
 353                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 354                         };
 355
 356                         gpio1: gpio@53f84000 {
 357                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 358                                 reg = <0x53f84000 0x4000>;
 359                                 interrupts = <50 51>;
 360                                 gpio-controller;
 361                                 #gpio-cells = <2>;
 362                                 interrupt-controller;
 363                                 #interrupt-cells = <2>;
 364                         };
 365
 366                         gpio2: gpio@53f88000 {
 367                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 368                                 reg = <0x53f88000 0x4000>;
 369                                 interrupts = <52 53>;
 370                                 gpio-controller;
 371                                 #gpio-cells = <2>;
 372                                 interrupt-controller;
 373                                 #interrupt-cells = <2>;
 374                         };
 375
 376                         gpio3: gpio@53f8c000 {
 377                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 378                                 reg = <0x53f8c000 0x4000>;
 379                                 interrupts = <54 55>;
 380                                 gpio-controller;
 381                                 #gpio-cells = <2>;
 382                                 interrupt-controller;
 383                                 #interrupt-cells = <2>;
 384                         };
 385
 386                         gpio4: gpio@53f90000 {
 387                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 388                                 reg = <0x53f90000 0x4000>;
 389                                 interrupts = <56 57>;
 390                                 gpio-controller;
 391                                 #gpio-cells = <2>;
 392                                 interrupt-controller;
 393                                 #interrupt-cells = <2>;
 394                         };
 395
 396                         kpp: kpp@53f94000 {
 397                                 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
 398                                 reg = <0x53f94000 0x4000>;
 399                                 interrupts = <60>;
 400                                 clocks = <&clks IMX5_CLK_DUMMY>;
 401                                 status = "disabled";
 402                         };
 403
 404                         wdog1: wdog@53f98000 {
 405                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 406                                 reg = <0x53f98000 0x4000>;
 407                                 interrupts = <58>;
 408                                 clocks = <&clks IMX5_CLK_DUMMY>;
 409                         };
 410
 411                         wdog2: wdog@53f9c000 {
 412                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 413                                 reg = <0x53f9c000 0x4000>;
 414                                 interrupts = <59>;
 415                                 clocks = <&clks IMX5_CLK_DUMMY>;
 416                                 status = "disabled";
 417                         };
 418
 419                         gpt: timer@53fa0000 {
 420                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 421                                 reg = <0x53fa0000 0x4000>;
 422                                 interrupts = <39>;
 423                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 424                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 425                                 clock-names = "ipg", "per";
 426                         };
 427
 428                         iomuxc: iomuxc@53fa8000 {
 429                                 compatible = "fsl,imx53-iomuxc";
 430                                 reg = <0x53fa8000 0x4000>;
 431                         };
 432
 433                         gpr: iomuxc-gpr@53fa8000 {
 434                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 435                                 reg = <0x53fa8000 0xc>;
 436                         };
 437
 438                         ldb: ldb@53fa8008 {
 439                                 #address-cells = <1>;
 440                                 #size-cells = <0>;
 441                                 compatible = "fsl,imx53-ldb";
 442                                 reg = <0x53fa8008 0x4>;
 443                                 gpr = <&gpr>;
 444                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 445                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 446                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 447                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 448                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 449                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 450                                 clock-names = "di0_pll", "di1_pll",
 451                                               "di0_sel", "di1_sel",
 452                                               "di0", "di1";
 453                                 status = "disabled";
 454
 455                                 lvds-channel@0 {
 456                                         #address-cells = <1>;
 457                                         #size-cells = <0>;
 458                                         reg = <0>;
 459                                         status = "disabled";
 460
 461                                         port@0 {
 462                                                 reg = <0>;
 463
 464                                                 lvds0_in: endpoint {
 465                                                         remote-endpoint = <&ipu_di0_lvds0>;
 466                                                 };
 467                                         };
 468                                 };
 469
 470                                 lvds-channel@1 {
 471                                         #address-cells = <1>;
 472                                         #size-cells = <0>;
 473                                         reg = <1>;
 474                                         status = "disabled";
 475
 476                                         port@1 {
 477                                                 reg = <1>;
 478
 479                                                 lvds1_in: endpoint {
 480                                                         remote-endpoint = <&ipu_di1_lvds1>;
 481                                                 };
 482                                         };
 483                                 };
 484                         };
 485
 486                         pwm1: pwm@53fb4000 {
 487                                 #pwm-cells = <2>;
 488                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 489                                 reg = <0x53fb4000 0x4000>;
 490                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 491                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 492                                 clock-names = "ipg", "per";
 493                                 interrupts = <61>;
 494                         };
 495
 496                         pwm2: pwm@53fb8000 {
 497                                 #pwm-cells = <2>;
 498                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 499                                 reg = <0x53fb8000 0x4000>;
 500                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 501                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 502                                 clock-names = "ipg", "per";
 503                                 interrupts = <94>;
 504                         };
 505
 506                         uart1: serial@53fbc000 {
 507                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 508                                 reg = <0x53fbc000 0x4000>;
 509                                 interrupts = <31>;
 510                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 511                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 512                                 clock-names = "ipg", "per";
 513                                 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
 514                                 dma-names = "rx", "tx";
 515                                 status = "disabled";
 516                         };
 517
 518                         uart2: serial@53fc0000 {
 519                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 520                                 reg = <0x53fc0000 0x4000>;
 521                                 interrupts = <32>;
 522                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 523                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 524                                 clock-names = "ipg", "per";
 525                                 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
 526                                 dma-names = "rx", "tx";
 527                                 status = "disabled";
 528                         };
 529
 530                         can1: can@53fc8000 {
 531                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 532                                 reg = <0x53fc8000 0x4000>;
 533                                 interrupts = <82>;
 534                                 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
 535                                          <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
 536                                 clock-names = "ipg", "per";
 537                                 status = "disabled";
 538                         };
 539
 540                         can2: can@53fcc000 {
 541                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 542                                 reg = <0x53fcc000 0x4000>;
 543                                 interrupts = <83>;
 544                                 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
 545                                          <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
 546                                 clock-names = "ipg", "per";
 547                                 status = "disabled";
 548                         };
 549
 550                         src: src@53fd0000 {
 551                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 552                                 reg = <0x53fd0000 0x4000>;
 553                                 #reset-cells = <1>;
 554                         };
 555
 556                         clks: ccm@53fd4000{
 557                                 compatible = "fsl,imx53-ccm";
 558                                 reg = <0x53fd4000 0x4000>;
 559                                 interrupts = <0 71 0x04 0 72 0x04>;
 560                                 #clock-cells = <1>;
 561                         };
 562
 563                         gpio5: gpio@53fdc000 {
 564                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 565                                 reg = <0x53fdc000 0x4000>;
 566                                 interrupts = <103 104>;
 567                                 gpio-controller;
 568                                 #gpio-cells = <2>;
 569                                 interrupt-controller;
 570                                 #interrupt-cells = <2>;
 571                         };
 572
 573                         gpio6: gpio@53fe0000 {
 574                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 575                                 reg = <0x53fe0000 0x4000>;
 576                                 interrupts = <105 106>;
 577                                 gpio-controller;
 578                                 #gpio-cells = <2>;
 579                                 interrupt-controller;
 580                                 #interrupt-cells = <2>;
 581                         };
 582
 583                         gpio7: gpio@53fe4000 {
 584                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 585                                 reg = <0x53fe4000 0x4000>;
 586                                 interrupts = <107 108>;
 587                                 gpio-controller;
 588                                 #gpio-cells = <2>;
 589                                 interrupt-controller;
 590                                 #interrupt-cells = <2>;
 591                         };
 592
 593                         i2c3: i2c@53fec000 {
 594                                 #address-cells = <1>;
 595                                 #size-cells = <0>;
 596                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 597                                 reg = <0x53fec000 0x4000>;
 598                                 interrupts = <64>;
 599                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 600                                 status = "disabled";
 601                         };
 602
 603                         uart4: serial@53ff0000 {
 604                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 605                                 reg = <0x53ff0000 0x4000>;
 606                                 interrupts = <13>;
 607                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 608                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 609                                 clock-names = "ipg", "per";
 610                                 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
 611                                 dma-names = "rx", "tx";
 612                                 status = "disabled";
 613                         };
 614                 };
 615
 616                 aips@60000000 { /* AIPS2 */
 617                         compatible = "fsl,aips-bus", "simple-bus";
 618                         #address-cells = <1>;
 619                         #size-cells = <1>;
 620                         reg = <0x60000000 0x10000000>;
 621                         ranges;
 622
 623                         aipstz2: bridge@63f00000 {
 624                                 compatible = "fsl,imx53-aipstz";
 625                                 reg = <0x63f00000 0x60>;
 626                         };
 627
 628                         iim: iim@63f98000 {
 629                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 630                                 reg = <0x63f98000 0x4000>;
 631                                 interrupts = <69>;
 632                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 633                         };
 634
 635                         uart5: serial@63f90000 {
 636                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 637                                 reg = <0x63f90000 0x4000>;
 638                                 interrupts = <86>;
 639                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 640                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 641                                 clock-names = "ipg", "per";
 642                                 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
 643                                 dma-names = "rx", "tx";
 644                                 status = "disabled";
 645                         };
 646
 647                         owire: owire@63fa4000 {
 648                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 649                                 reg = <0x63fa4000 0x4000>;
 650                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 651                                 status = "disabled";
 652                         };
 653
 654                         ecspi2: ecspi@63fac000 {
 655                                 #address-cells = <1>;
 656                                 #size-cells = <0>;
 657                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 658                                 reg = <0x63fac000 0x4000>;
 659                                 interrupts = <37>;
 660                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 661                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 662                                 clock-names = "ipg", "per";
 663                                 status = "disabled";
 664                         };
 665
 666                         sdma: sdma@63fb0000 {
 667                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 668                                 reg = <0x63fb0000 0x4000>;
 669                                 interrupts = <6>;
 670                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 671                                          <&clks IMX5_CLK_SDMA_GATE>;
 672                                 clock-names = "ipg", "ahb";
 673                                 #dma-cells = <3>;
 674                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 675                         };
 676
 677                         cspi: cspi@63fc0000 {
 678                                 #address-cells = <1>;
 679                                 #size-cells = <0>;
 680                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 681                                 reg = <0x63fc0000 0x4000>;
 682                                 interrupts = <38>;
 683                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 684                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 685                                 clock-names = "ipg", "per";
 686                                 status = "disabled";
 687                         };
 688
 689                         i2c2: i2c@63fc4000 {
 690                                 #address-cells = <1>;
 691                                 #size-cells = <0>;
 692                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 693                                 reg = <0x63fc4000 0x4000>;
 694                                 interrupts = <63>;
 695                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 696                                 status = "disabled";
 697                         };
 698
 699                         i2c1: i2c@63fc8000 {
 700                                 #address-cells = <1>;
 701                                 #size-cells = <0>;
 702                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 703                                 reg = <0x63fc8000 0x4000>;
 704                                 interrupts = <62>;
 705                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 706                                 status = "disabled";
 707                         };
 708
 709                         ssi1: ssi@63fcc000 {
 710                                 #sound-dai-cells = <0>;
 711                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 712                                                 "fsl,imx21-ssi";
 713                                 reg = <0x63fcc000 0x4000>;
 714                                 interrupts = <29>;
 715                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
 716                                          <&clks IMX5_CLK_SSI1_ROOT_GATE>;
 717                                 clock-names = "ipg", "baud";
 718                                 dmas = <&sdma 28 0 0>,
 719                                        <&sdma 29 0 0>;
 720                                 dma-names = "rx", "tx";
 721                                 fsl,fifo-depth = <15>;
 722                                 status = "disabled";
 723                         };
 724
 725                         audmux: audmux@63fd0000 {
 726                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 727                                 reg = <0x63fd0000 0x4000>;
 728                                 status = "disabled";
 729                         };
 730
 731                         nfc: nand@63fdb000 {
 732                                 compatible = "fsl,imx53-nand";
 733                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 734                                 interrupts = <8>;
 735                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 736                                 status = "disabled";
 737                         };
 738
 739                         ssi3: ssi@63fe8000 {
 740                                 #sound-dai-cells = <0>;
 741                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 742                                                 "fsl,imx21-ssi";
 743                                 reg = <0x63fe8000 0x4000>;
 744                                 interrupts = <96>;
 745                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
 746                                          <&clks IMX5_CLK_SSI3_ROOT_GATE>;
 747                                 clock-names = "ipg", "baud";
 748                                 dmas = <&sdma 46 0 0>,
 749                                        <&sdma 47 0 0>;
 750                                 dma-names = "rx", "tx";
 751                                 fsl,fifo-depth = <15>;
 752                                 status = "disabled";
 753                         };
 754
 755                         fec: ethernet@63fec000 {
 756                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 757                                 reg = <0x63fec000 0x4000>;
 758                                 interrupts = <87>;
 759                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 760                                          <&clks IMX5_CLK_FEC_GATE>,
 761                                          <&clks IMX5_CLK_FEC_GATE>;
 762                                 clock-names = "ipg", "ahb", "ptp";
 763                                 status = "disabled";
 764                         };
 765
 766                         tve: tve@63ff0000 {
 767                                 compatible = "fsl,imx53-tve";
 768                                 reg = <0x63ff0000 0x1000>;
 769                                 interrupts = <92>;
 770                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 771                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 772                                 clock-names = "tve", "di_sel";
 773                                 status = "disabled";
 774
 775                                 port {
 776                                         tve_in: endpoint {
 777                                                 remote-endpoint = <&ipu_di1_tve>;
 778                                         };
 779                                 };
 780                         };
 781
 782                         vpu: vpu@63ff4000 {
 783                                 compatible = "fsl,imx53-vpu", "cnm,coda7541";
 784                                 reg = <0x63ff4000 0x1000>;
 785                                 interrupts = <9>;
 786                                 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
 787                                          <&clks IMX5_CLK_VPU_GATE>;
 788                                 clock-names = "per", "ahb";
 789                                 resets = <&src 1>;
 790                                 iram = <&ocram>;
 791                         };
 792
 793                         sahara: crypto@63ff8000 {
 794                                 compatible = "fsl,imx53-sahara";
 795                                 reg = <0x63ff8000 0x4000>;
 796                                 interrupts = <19 20>;
 797                                 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
 798                                          <&clks IMX5_CLK_SAHARA_IPG_GATE>;
 799                                 clock-names = "ipg", "ahb";
 800                         };
 801                 };
 802
 803                 ocram: sram@f8000000 {
 804                         compatible = "mmio-sram";
 805                         reg = <0xf8000000 0x20000>;
 806                         clocks = <&clks IMX5_CLK_OCRAM>;
 807                 };
 808
 809                 pmu {
 810                         compatible = "arm,cortex-a8-pmu";
 811                         interrupts = <77>;
 812                 };
 813         };
 814 };