2 * Device Tree Source for Renesas r8a7779
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7779-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/r8a7779-sysc.h>
18 compatible = "renesas,r8a7779";
19 interrupt-parent = <&gic>;
29 compatible = "arm,cortex-a9";
31 clock-frequency = <1000000000>;
32 clocks = <&cpg_clocks R8A7779_CLK_Z>;
36 compatible = "arm,cortex-a9";
38 clock-frequency = <1000000000>;
39 clocks = <&cpg_clocks R8A7779_CLK_Z>;
40 power-domains = <&sysc R8A7779_PD_ARM1>;
44 compatible = "arm,cortex-a9";
46 clock-frequency = <1000000000>;
47 clocks = <&cpg_clocks R8A7779_CLK_Z>;
48 power-domains = <&sysc R8A7779_PD_ARM2>;
52 compatible = "arm,cortex-a9";
54 clock-frequency = <1000000000>;
55 clocks = <&cpg_clocks R8A7779_CLK_Z>;
56 power-domains = <&sysc R8A7779_PD_ARM3>;
66 gic: interrupt-controller@f0001000 {
67 compatible = "arm,cortex-a9-gic";
68 #interrupt-cells = <3>;
70 reg = <0xf0001000 0x1000>,
75 compatible = "arm,cortex-a9-twd-timer";
76 reg = <0xf0000600 0x20>;
77 interrupts = <GIC_PPI 13
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
79 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
82 gpio0: gpio@ffc40000 {
83 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
84 reg = <0xffc40000 0x2c>;
85 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
88 gpio-ranges = <&pfc 0 0 32>;
89 #interrupt-cells = <2>;
93 gpio1: gpio@ffc41000 {
94 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
95 reg = <0xffc41000 0x2c>;
96 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
99 gpio-ranges = <&pfc 0 32 32>;
100 #interrupt-cells = <2>;
101 interrupt-controller;
104 gpio2: gpio@ffc42000 {
105 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
106 reg = <0xffc42000 0x2c>;
107 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
110 gpio-ranges = <&pfc 0 64 32>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
115 gpio3: gpio@ffc43000 {
116 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
117 reg = <0xffc43000 0x2c>;
118 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
121 gpio-ranges = <&pfc 0 96 32>;
122 #interrupt-cells = <2>;
123 interrupt-controller;
126 gpio4: gpio@ffc44000 {
127 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
128 reg = <0xffc44000 0x2c>;
129 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
132 gpio-ranges = <&pfc 0 128 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
137 gpio5: gpio@ffc45000 {
138 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
139 reg = <0xffc45000 0x2c>;
140 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
143 gpio-ranges = <&pfc 0 160 32>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
148 gpio6: gpio@ffc46000 {
149 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
150 reg = <0xffc46000 0x2c>;
151 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
154 gpio-ranges = <&pfc 0 192 9>;
155 #interrupt-cells = <2>;
156 interrupt-controller;
159 irqpin0: interrupt-controller@fe78001c {
160 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
161 #interrupt-cells = <2>;
163 interrupt-controller;
164 reg = <0xfe78001c 4>,
170 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
171 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
172 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
173 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
174 sense-bitfield-width = <2>;
178 #address-cells = <1>;
180 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
181 reg = <0xffc70000 0x1000>;
182 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
184 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
189 #address-cells = <1>;
191 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
192 reg = <0xffc71000 0x1000>;
193 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
195 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
200 #address-cells = <1>;
202 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
203 reg = <0xffc72000 0x1000>;
204 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
206 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
211 #address-cells = <1>;
213 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
214 reg = <0xffc73000 0x1000>;
215 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
217 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
221 scif0: serial@ffe40000 {
222 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
224 reg = <0xffe40000 0x100>;
225 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
227 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
228 clock-names = "fck", "brg_int", "scif_clk";
229 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
233 scif1: serial@ffe41000 {
234 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
236 reg = <0xffe41000 0x100>;
237 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
239 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
240 clock-names = "fck", "brg_int", "scif_clk";
241 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
245 scif2: serial@ffe42000 {
246 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
248 reg = <0xffe42000 0x100>;
249 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
251 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
252 clock-names = "fck", "brg_int", "scif_clk";
253 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
257 scif3: serial@ffe43000 {
258 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
260 reg = <0xffe43000 0x100>;
261 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
263 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
264 clock-names = "fck", "brg_int", "scif_clk";
265 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
269 scif4: serial@ffe44000 {
270 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
272 reg = <0xffe44000 0x100>;
273 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
275 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
276 clock-names = "fck", "brg_int", "scif_clk";
277 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
281 scif5: serial@ffe45000 {
282 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
284 reg = <0xffe45000 0x100>;
285 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
287 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
288 clock-names = "fck", "brg_int", "scif_clk";
289 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
293 pfc: pin-controller@fffc0000 {
294 compatible = "renesas,pfc-r8a7779";
295 reg = <0xfffc0000 0x23c>;
299 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
300 reg = <0xffc48000 0x38>;
303 tmu0: timer@ffd80000 {
304 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
305 reg = <0xffd80000 0x30>;
306 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
311 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
313 #renesas,channels = <3>;
318 tmu1: timer@ffd81000 {
319 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
320 reg = <0xffd81000 0x30>;
321 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
326 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
328 #renesas,channels = <3>;
333 tmu2: timer@ffd82000 {
334 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
335 reg = <0xffd82000 0x30>;
336 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
341 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
343 #renesas,channels = <3>;
348 sata: sata@fc600000 {
349 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
350 reg = <0xfc600000 0x2000>;
351 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
353 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
358 compatible = "renesas,sdhi-r8a7779";
359 reg = <0xffe4c000 0x100>;
360 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
362 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
367 compatible = "renesas,sdhi-r8a7779";
368 reg = <0xffe4d000 0x100>;
369 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
371 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
376 compatible = "renesas,sdhi-r8a7779";
377 reg = <0xffe4e000 0x100>;
378 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
380 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
385 compatible = "renesas,sdhi-r8a7779";
386 reg = <0xffe4f000 0x100>;
387 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
389 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
393 hspi0: spi@fffc7000 {
394 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
395 reg = <0xfffc7000 0x18>;
396 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>;
399 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
400 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
404 hspi1: spi@fffc8000 {
405 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
406 reg = <0xfffc8000 0x18>;
407 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
408 #address-cells = <1>;
410 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
411 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
415 hspi2: spi@fffc6000 {
416 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
417 reg = <0xfffc6000 0x18>;
418 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
421 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
422 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
426 du: display@fff80000 {
427 compatible = "renesas,du-r8a7779";
428 reg = <0xfff80000 0x40000>;
429 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp1_clks R8A7779_CLK_DU>;
431 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
435 #address-cells = <1>;
440 du_out_rgb0: endpoint {
445 du_out_rgb1: endpoint {
452 #address-cells = <1>;
456 /* External root clock */
458 compatible = "fixed-clock";
460 /* This value must be overriden by the board. */
461 clock-frequency = <0>;
464 /* External SCIF clock */
466 compatible = "fixed-clock";
468 /* This value must be overridden by the board. */
469 clock-frequency = <0>;
472 /* Special CPG clocks */
473 cpg_clocks: clocks@ffc80000 {
474 compatible = "renesas,r8a7779-cpg-clocks";
475 reg = <0xffc80000 0x30>;
476 clocks = <&extal_clk>;
478 clock-output-names = "plla", "z", "zs", "s",
479 "s1", "p", "b", "out";
480 #power-domain-cells = <0>;
483 /* Fixed factor clocks */
485 compatible = "fixed-factor-clock";
486 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
492 compatible = "fixed-factor-clock";
493 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
499 compatible = "fixed-factor-clock";
500 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
506 compatible = "fixed-factor-clock";
507 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
514 mstp0_clks: clocks@ffc80030 {
515 compatible = "renesas,r8a7779-mstp-clocks",
516 "renesas,cpg-mstp-clocks";
517 reg = <0xffc80030 4>;
518 clocks = <&cpg_clocks R8A7779_CLK_S>,
519 <&cpg_clocks R8A7779_CLK_P>,
520 <&cpg_clocks R8A7779_CLK_P>,
521 <&cpg_clocks R8A7779_CLK_P>,
522 <&cpg_clocks R8A7779_CLK_S>,
523 <&cpg_clocks R8A7779_CLK_S>,
524 <&cpg_clocks R8A7779_CLK_P>,
525 <&cpg_clocks R8A7779_CLK_P>,
526 <&cpg_clocks R8A7779_CLK_P>,
527 <&cpg_clocks R8A7779_CLK_P>,
528 <&cpg_clocks R8A7779_CLK_P>,
529 <&cpg_clocks R8A7779_CLK_P>,
530 <&cpg_clocks R8A7779_CLK_P>,
531 <&cpg_clocks R8A7779_CLK_P>,
532 <&cpg_clocks R8A7779_CLK_P>,
533 <&cpg_clocks R8A7779_CLK_P>;
536 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
537 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
538 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
539 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
540 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
541 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
542 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
543 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
546 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
547 "hscif0", "scif5", "scif4", "scif3", "scif2",
548 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
551 mstp1_clks: clocks@ffc80034 {
552 compatible = "renesas,r8a7779-mstp-clocks",
553 "renesas,cpg-mstp-clocks";
554 reg = <0xffc80034 4>, <0xffc80044 4>;
555 clocks = <&cpg_clocks R8A7779_CLK_P>,
556 <&cpg_clocks R8A7779_CLK_P>,
557 <&cpg_clocks R8A7779_CLK_S>,
558 <&cpg_clocks R8A7779_CLK_S>,
559 <&cpg_clocks R8A7779_CLK_S>,
560 <&cpg_clocks R8A7779_CLK_S>,
561 <&cpg_clocks R8A7779_CLK_P>,
562 <&cpg_clocks R8A7779_CLK_P>,
563 <&cpg_clocks R8A7779_CLK_P>,
564 <&cpg_clocks R8A7779_CLK_S>;
567 R8A7779_CLK_USB01 R8A7779_CLK_USB2
568 R8A7779_CLK_DU R8A7779_CLK_VIN2
569 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
570 R8A7779_CLK_ETHER R8A7779_CLK_SATA
571 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
580 mstp3_clks: clocks@ffc8003c {
581 compatible = "renesas,r8a7779-mstp-clocks",
582 "renesas,cpg-mstp-clocks";
583 reg = <0xffc8003c 4>;
584 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
585 <&s4_clk>, <&s4_clk>;
588 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
589 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
590 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
593 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
598 prr: chipid@ff000044 {
599 compatible = "renesas,prr";
600 reg = <0xff000044 4>;
603 rst: reset-controller@ffcc0000 {
604 compatible = "renesas,r8a7779-reset-wdt";
605 reg = <0xffcc0000 0x48>;
608 sysc: system-controller@ffd85000 {
609 compatible = "renesas,r8a7779-sysc";
610 reg = <0xffd85000 0x0200>;
611 #power-domain-cells = <1>;