2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3036-cru.h>
46 #include "skeleton.dtsi"
49 compatible = "rockchip,rk3036";
51 interrupt-parent = <&gic>;
67 device_type = "memory";
68 reg = <0x60000000 0x40000000>;
74 enable-method = "rockchip,rk3036-smp";
78 compatible = "arm,cortex-a7";
80 resets = <&cru SRST_CORE0>;
85 clock-latency = <40000>;
86 clocks = <&cru ARMCLK>;
91 compatible = "arm,cortex-a7";
93 resets = <&cru SRST_CORE1>;
98 compatible = "arm,amba-bus";
103 pdma: pdma@20078000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0x20078000 0x4000>;
106 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
109 arm,pl330-broken-no-flushp;
110 clocks = <&cru ACLK_DMAC2>;
111 clock-names = "apb_pclk";
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
119 interrupt-affinity = <&cpu0>, <&cpu1>;
123 compatible = "arm,armv7-timer";
124 arm,cpu-registers-not-fw-configured;
125 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
129 clock-frequency = <24000000>;
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "xin24m";
139 bus_intmem@10080000 {
140 compatible = "mmio-sram";
141 reg = <0x10080000 0x2000>;
142 #address-cells = <1>;
144 ranges = <0 0x10080000 0x2000>;
147 compatible = "rockchip,rk3066-smp-sram";
152 gic: interrupt-controller@10139000 {
153 compatible = "arm,gic-400";
154 interrupt-controller;
155 #interrupt-cells = <3>;
156 #address-cells = <0>;
158 reg = <0x10139000 0x1000>,
162 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
165 usb_otg: usb@10180000 {
166 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
168 reg = <0x10180000 0x40000>;
169 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru HCLK_OTG0>;
173 g-np-tx-fifo-size = <16>;
174 g-rx-fifo-size = <275>;
175 g-tx-fifo-size = <256 128 128 64 64 32>;
180 usb_host: usb@101c0000 {
181 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
183 reg = <0x101c0000 0x40000>;
184 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&cru HCLK_OTG1>;
191 sdmmc: dwmmc@10214000 {
192 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
193 reg = <0x10214000 0x4000>;
194 clock-frequency = <37500000>;
195 clock-freq-min-max = <400000 37500000>;
196 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
197 clock-names = "biu", "ciu";
198 fifo-depth = <0x100>;
199 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
203 sdio: dwmmc@10218000 {
204 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
205 reg = <0x10218000 0x4000>;
206 clock-freq-min-max = <400000 37500000>;
207 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
208 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
209 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
210 fifo-depth = <0x100>;
211 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
215 emmc: dwmmc@1021c000 {
216 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
217 reg = <0x1021c000 0x4000>;
218 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
222 clock-frequency = <37500000>;
223 clock-freq-min-max = <400000 37500000>;
224 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
225 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
226 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
227 default-sample-phase = <158>;
231 fifo-depth = <0x100>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
241 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
242 reg = <0x10220000 0x4000>;
243 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
244 #address-cells = <1>;
246 clock-names = "i2s_clk", "i2s_hclk";
247 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
248 dmas = <&pdma 0>, <&pdma 1>;
249 dma-names = "tx", "rx";
250 pinctrl-names = "default";
251 pinctrl-0 = <&i2s_bus>;
255 cru: clock-controller@20000000 {
256 compatible = "rockchip,rk3036-cru";
257 reg = <0x20000000 0x1000>;
258 rockchip,grf = <&grf>;
261 assigned-clocks = <&cru PLL_GPLL>;
262 assigned-clock-rates = <594000000>;
265 grf: syscon@20008000 {
266 compatible = "rockchip,rk3036-grf", "syscon";
267 reg = <0x20008000 0x1000>;
270 acodec: acodec-ana@20030000 {
271 compatible = "rk3036-codec";
272 reg = <0x20030000 0x4000>;
273 rockchip,grf = <&grf>;
274 clock-names = "acodec_pclk";
275 clocks = <&cru PCLK_ACODEC>;
279 timer: timer@20044000 {
280 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
281 reg = <0x20044000 0x20>;
282 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&xin24m>, <&cru PCLK_TIMER>;
284 clock-names = "timer", "pclk";
288 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
289 reg = <0x20050000 0x10>;
291 clocks = <&cru PCLK_PWM>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&pwm0_pin>;
299 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
300 reg = <0x20050010 0x10>;
302 clocks = <&cru PCLK_PWM>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pwm1_pin>;
310 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
311 reg = <0x20050020 0x10>;
313 clocks = <&cru PCLK_PWM>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pwm2_pin>;
321 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
322 reg = <0x20050030 0x10>;
324 clocks = <&cru PCLK_PWM>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&pwm3_pin>;
332 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
333 reg = <0x20056000 0x1000>;
334 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
338 clocks = <&cru PCLK_I2C1>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c1_xfer>;
345 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
346 reg = <0x2005a000 0x1000>;
347 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
351 clocks = <&cru PCLK_I2C2>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c2_xfer>;
357 uart0: serial@20060000 {
358 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
359 reg = <0x20060000 0x100>;
360 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
363 clock-frequency = <24000000>;
364 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
365 clock-names = "baudclk", "apb_pclk";
366 pinctrl-names = "default";
367 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
371 uart1: serial@20064000 {
372 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
373 reg = <0x20064000 0x100>;
374 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
377 clock-frequency = <24000000>;
378 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
379 clock-names = "baudclk", "apb_pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&uart1_xfer>;
385 uart2: serial@20068000 {
386 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
387 reg = <0x20068000 0x100>;
388 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
391 clock-frequency = <24000000>;
392 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
393 clock-names = "baudclk", "apb_pclk";
394 pinctrl-names = "default";
395 pinctrl-0 = <&uart2_xfer>;
400 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
401 reg = <0x20072000 0x1000>;
402 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
406 clocks = <&cru PCLK_I2C0>;
407 pinctrl-names = "default";
408 pinctrl-0 = <&i2c0_xfer>;
413 compatible = "rockchip,rockchip-spi";
414 reg = <0x20074000 0x1000>;
415 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
416 clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
417 clock-names = "apb-pclk","spi_pclk";
418 dmas = <&pdma 8>, <&pdma 9>;
419 dma-names = "tx", "rx";
420 pinctrl-names = "default";
421 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
422 #address-cells = <1>;
428 compatible = "rockchip,rk3036-pinctrl";
429 rockchip,grf = <&grf>;
430 #address-cells = <1>;
434 gpio0: gpio0@2007c000 {
435 compatible = "rockchip,gpio-bank";
436 reg = <0x2007c000 0x100>;
437 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&cru PCLK_GPIO0>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
447 gpio1: gpio1@20080000 {
448 compatible = "rockchip,gpio-bank";
449 reg = <0x20080000 0x100>;
450 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru PCLK_GPIO1>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
460 gpio2: gpio2@20084000 {
461 compatible = "rockchip,gpio-bank";
462 reg = <0x20084000 0x100>;
463 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cru PCLK_GPIO2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
473 pcfg_pull_default: pcfg_pull_default {
474 bias-pull-pin-default;
477 pcfg_pull_none: pcfg-pull-none {
483 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
489 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
495 rockchip,pins = <0 1 2 &pcfg_pull_none>;
501 rockchip,pins = <0 27 1 &pcfg_pull_none>;
506 sdmmc_clk: sdmmc-clk {
507 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
510 sdmmc_cmd: sdmmc-cmd {
511 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
515 rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
518 sdmmc_bus1: sdmmc-bus1 {
519 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
522 sdmmc_bus4: sdmmc-bus4 {
523 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
524 <1 19 RK_FUNC_1 &pcfg_pull_default>,
525 <1 20 RK_FUNC_1 &pcfg_pull_default>,
526 <1 21 RK_FUNC_1 &pcfg_pull_default>;
531 sdio_bus1: sdio-bus1 {
532 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
535 sdio_bus4: sdio-bus4 {
536 rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
537 <0 12 RK_FUNC_1 &pcfg_pull_default>,
538 <0 13 RK_FUNC_1 &pcfg_pull_default>,
539 <0 14 RK_FUNC_1 &pcfg_pull_default>;
543 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
547 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
553 * We run eMMC at max speed; bump up drive strength.
554 * We also have external pulls, so disable the internal ones.
557 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
561 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
564 emmc_bus8: emmc-bus8 {
565 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
566 <1 25 RK_FUNC_2 &pcfg_pull_default>,
567 <1 26 RK_FUNC_2 &pcfg_pull_default>,
568 <1 27 RK_FUNC_2 &pcfg_pull_default>,
569 <1 28 RK_FUNC_2 &pcfg_pull_default>,
570 <1 29 RK_FUNC_2 &pcfg_pull_default>,
571 <1 30 RK_FUNC_2 &pcfg_pull_default>,
572 <1 31 RK_FUNC_2 &pcfg_pull_default>;
577 i2c0_xfer: i2c0-xfer {
578 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
579 <0 1 RK_FUNC_1 &pcfg_pull_none>;
584 i2c1_xfer: i2c1-xfer {
585 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
586 <0 3 RK_FUNC_1 &pcfg_pull_none>;
591 i2c2_xfer: i2c2-xfer {
592 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
593 <2 21 RK_FUNC_1 &pcfg_pull_none>;
599 rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>,
600 <1 1 RK_FUNC_1 &pcfg_pull_default>,
601 <1 2 RK_FUNC_1 &pcfg_pull_default>,
602 <1 3 RK_FUNC_1 &pcfg_pull_default>,
603 <1 4 RK_FUNC_1 &pcfg_pull_default>,
604 <1 5 RK_FUNC_1 &pcfg_pull_default>;
609 uart0_xfer: uart0-xfer {
610 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
611 <0 17 RK_FUNC_1 &pcfg_pull_none>;
614 uart0_cts: uart0-cts {
615 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
618 uart0_rts: uart0-rts {
619 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
624 uart1_xfer: uart1-xfer {
625 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
626 <2 23 RK_FUNC_1 &pcfg_pull_none>;
628 /* no rts / cts for uart1 */
632 uart2_xfer: uart2-xfer {
633 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
634 <1 19 RK_FUNC_2 &pcfg_pull_none>;
636 /* no rts / cts for uart2 */
641 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
645 rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>;
649 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>;
653 rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>;
658 rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>;