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1 /*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9 #include "stih41x.dtsi"
10 #include "stih415-clock.dtsi"
11 #include "stih415-pinctrl.dtsi"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 / {
14
15 L2: cache-controller {
16 compatible = "arm,pl310-cache";
17 reg = <0xfffe2000 0x1000>;
18 arm,data-latency = <3 2 2>;
19 arm,tag-latency = <1 1 1>;
20 cache-unified;
21 cache-level = <2>;
22 };
23
24 soc {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 interrupt-parent = <&intc>;
28 ranges;
29 compatible = "simple-bus";
30
31 syscfg_sbc: sbc-syscfg@fe600000{
32 compatible = "st,stih415-sbc-syscfg", "syscon";
33 reg = <0xfe600000 0xb4>;
34 };
35
36 syscfg_front: front-syscfg@fee10000{
37 compatible = "st,stih415-front-syscfg", "syscon";
38 reg = <0xfee10000 0x194>;
39 };
40
41 syscfg_rear: rear-syscfg@fe830000{
42 compatible = "st,stih415-rear-syscfg", "syscon";
43 reg = <0xfe830000 0x190>;
44 };
45
46 /* MPE syscfgs */
47 syscfg_left: left-syscfg@fd690000{
48 compatible = "st,stih415-left-syscfg", "syscon";
49 reg = <0xfd690000 0x78>;
50 };
51
52 syscfg_right: right-syscfg@fd320000{
53 compatible = "st,stih415-right-syscfg", "syscon";
54 reg = <0xfd320000 0x180>;
55 };
56
57 syscfg_system: system-syscfg@fdde0000 {
58 compatible = "st,stih415-system-syscfg", "syscon";
59 reg = <0xfdde0000 0x15c>;
60 };
61
62 syscfg_lpm: lpm-syscfg@fe4b5100{
63 compatible = "st,stih415-lpm-syscfg", "syscon";
64 reg = <0xfe4b5100 0x08>;
65 };
66
67 serial2: serial@fed32000 {
68 compatible = "st,asc";
69 status = "disabled";
70 reg = <0xfed32000 0x2c>;
71 interrupts = <0 197 0>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_serial2>;
74 clocks = <&CLKS_ICN_REG_0>;
75 };
76
77 /* SBC comms block ASCs in SASG1 */
78 sbc_serial1: serial@fe531000 {
79 compatible = "st,asc";
80 status = "disabled";
81 reg = <0xfe531000 0x2c>;
82 interrupts = <0 210 0>;
83 clocks = <&CLK_SYSIN>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_sbc_serial1>;
86 };
87
88 i2c@fed40000 {
89 compatible = "st,comms-ssc4-i2c";
90 reg = <0xfed40000 0x110>;
91 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&CLKS_ICN_REG_0>;
93 clock-names = "ssc";
94 clock-frequency = <400000>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_i2c0_default>;
97
98 status = "disabled";
99 };
100
101 i2c@fed41000 {
102 compatible = "st,comms-ssc4-i2c";
103 reg = <0xfed41000 0x110>;
104 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&CLKS_ICN_REG_0>;
106 clock-names = "ssc";
107 clock-frequency = <400000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_i2c1_default>;
110
111 status = "disabled";
112 };
113
114 i2c@fe540000 {
115 compatible = "st,comms-ssc4-i2c";
116 reg = <0xfe540000 0x110>;
117 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&CLK_SYSIN>;
119 clock-names = "ssc";
120 clock-frequency = <400000>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
123
124 status = "disabled";
125 };
126
127 i2c@fe541000 {
128 compatible = "st,comms-ssc4-i2c";
129 reg = <0xfe541000 0x110>;
130 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&CLK_SYSIN>;
132 clock-names = "ssc";
133 clock-frequency = <400000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
136
137 status = "disabled";
138 };
139 };
140 };