arch/arm/boot/dts/stm32h743.dtsi

   1 /*
   2  * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "skeleton.dtsi"
  44 #include "armv7-m.dtsi"
  45 #include <dt-bindings/clock/stm32h7-clks.h>
  46 #include <dt-bindings/mfd/stm32h7-rcc.h>
  47
  48 / {
  49         clocks {
  50                 clk_hse: clk-hse {
  51                         #clock-cells = <0>;
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <0>;
  54                 };
  55
  56                 clk_lse: clk-lse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 clk_i2s: i2s_ckin {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <0>;
  66                 };
  67         };
  68
  69         soc {
  70                 timer5: timer@40000c00 {
  71                         compatible = "st,stm32-timer";
  72                         reg = <0x40000c00 0x400>;
  73                         interrupts = <50>;
  74                         clocks = <&rcc TIM5_CK>;
  75                 };
  76
  77                 lptimer1: timer@40002400 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         compatible = "st,stm32-lptimer";
  81                         reg = <0x40002400 0x400>;
  82                         clocks = <&rcc LPTIM1_CK>;
  83                         clock-names = "mux";
  84                         status = "disabled";
  85
  86                         pwm {
  87                                 compatible = "st,stm32-pwm-lp";
  88                                 status = "disabled";
  89                         };
  90
  91                         trigger@0 {
  92                                 compatible = "st,stm32-lptimer-trigger";
  93                                 reg = <0>;
  94                                 status = "disabled";
  95                         };
  96
  97                         counter {
  98                                 compatible = "st,stm32-lptimer-counter";
  99                                 status = "disabled";
 100                         };
 101                 };
 102
 103                 usart2: serial@40004400 {
 104                         compatible = "st,stm32f7-uart";
 105                         reg = <0x40004400 0x400>;
 106                         interrupts = <38>;
 107                         status = "disabled";
 108                         clocks = <&rcc USART2_CK>;
 109                 };
 110
 111                 dac: dac@40007400 {
 112                         compatible = "st,stm32h7-dac-core";
 113                         reg = <0x40007400 0x400>;
 114                         clocks = <&rcc DAC12_CK>;
 115                         clock-names = "pclk";
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         status = "disabled";
 119
 120                         dac1: dac@1 {
 121                                 compatible = "st,stm32-dac";
 122                                 #io-channels-cells = <1>;
 123                                 reg = <1>;
 124                                 status = "disabled";
 125                         };
 126
 127                         dac2: dac@2 {
 128                                 compatible = "st,stm32-dac";
 129                                 #io-channels-cells = <1>;
 130                                 reg = <2>;
 131                                 status = "disabled";
 132                         };
 133                 };
 134
 135                 usart1: serial@40011000 {
 136                         compatible = "st,stm32f7-uart";
 137                         reg = <0x40011000 0x400>;
 138                         interrupts = <37>;
 139                         status = "disabled";
 140                         clocks = <&rcc USART1_CK>;
 141                 };
 142
 143                 dma1: dma@40020000 {
 144                         compatible = "st,stm32-dma";
 145                         reg = <0x40020000 0x400>;
 146                         interrupts = <11>,
 147                                      <12>,
 148                                      <13>,
 149                                      <14>,
 150                                      <15>,
 151                                      <16>,
 152                                      <17>,
 153                                      <47>;
 154                         clocks = <&rcc DMA1_CK>;
 155                         #dma-cells = <4>;
 156                         st,mem2mem;
 157                         dma-requests = <8>;
 158                         status = "disabled";
 159                 };
 160
 161                 dma2: dma@40020400 {
 162                         compatible = "st,stm32-dma";
 163                         reg = <0x40020400 0x400>;
 164                         interrupts = <56>,
 165                                      <57>,
 166                                      <58>,
 167                                      <59>,
 168                                      <60>,
 169                                      <68>,
 170                                      <69>,
 171                                      <70>;
 172                         clocks = <&rcc DMA2_CK>;
 173                         #dma-cells = <4>;
 174                         st,mem2mem;
 175                         dma-requests = <8>;
 176                         status = "disabled";
 177                 };
 178
 179                 dmamux1: dma-router@40020800 {
 180                         compatible = "st,stm32h7-dmamux";
 181                         reg = <0x40020800 0x1c>;
 182                         #dma-cells = <3>;
 183                         dma-channels = <16>;
 184                         dma-requests = <128>;
 185                         dma-masters = <&dma1 &dma2>;
 186                         clocks = <&rcc DMA1_CK>;
 187                 };
 188
 189                 adc_12: adc@40022000 {
 190                         compatible = "st,stm32h7-adc-core";
 191                         reg = <0x40022000 0x400>;
 192                         interrupts = <18>;
 193                         clocks = <&rcc ADC12_CK>;
 194                         clock-names = "bus";
 195                         interrupt-controller;
 196                         #interrupt-cells = <1>;
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                         status = "disabled";
 200
 201                         adc1: adc@0 {
 202                                 compatible = "st,stm32h7-adc";
 203                                 #io-channel-cells = <1>;
 204                                 reg = <0x0>;
 205                                 interrupt-parent = <&adc_12>;
 206                                 interrupts = <0>;
 207                                 status = "disabled";
 208                         };
 209
 210                         adc2: adc@100 {
 211                                 compatible = "st,stm32h7-adc";
 212                                 #io-channel-cells = <1>;
 213                                 reg = <0x100>;
 214                                 interrupt-parent = <&adc_12>;
 215                                 interrupts = <1>;
 216                                 status = "disabled";
 217                         };
 218                 };
 219
 220                 mdma1: dma@52000000 {
 221                         compatible = "st,stm32h7-mdma";
 222                         reg = <0x52000000 0x1000>;
 223                         interrupts = <122>;
 224                         clocks = <&rcc MDMA_CK>;
 225                         #dma-cells = <5>;
 226                         dma-channels = <16>;
 227                         dma-requests = <32>;
 228                 };
 229
 230                 lptimer2: timer@58002400 {
 231                         #address-cells = <1>;
 232                         #size-cells = <0>;
 233                         compatible = "st,stm32-lptimer";
 234                         reg = <0x58002400 0x400>;
 235                         clocks = <&rcc LPTIM2_CK>;
 236                         clock-names = "mux";
 237                         status = "disabled";
 238
 239                         pwm {
 240                                 compatible = "st,stm32-pwm-lp";
 241                                 status = "disabled";
 242                         };
 243
 244                         trigger@1 {
 245                                 compatible = "st,stm32-lptimer-trigger";
 246                                 reg = <1>;
 247                                 status = "disabled";
 248                         };
 249
 250                         counter {
 251                                 compatible = "st,stm32-lptimer-counter";
 252                                 status = "disabled";
 253                         };
 254                 };
 255
 256                 lptimer3: timer@58002800 {
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         compatible = "st,stm32-lptimer";
 260                         reg = <0x58002800 0x400>;
 261                         clocks = <&rcc LPTIM3_CK>;
 262                         clock-names = "mux";
 263                         status = "disabled";
 264
 265                         pwm {
 266                                 compatible = "st,stm32-pwm-lp";
 267                                 status = "disabled";
 268                         };
 269
 270                         trigger@2 {
 271                                 compatible = "st,stm32-lptimer-trigger";
 272                                 reg = <2>;
 273                                 status = "disabled";
 274                         };
 275                 };
 276
 277                 lptimer4: timer@58002c00 {
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         compatible = "st,stm32-lptimer";
 281                         reg = <0x58002c00 0x400>;
 282                         clocks = <&rcc LPTIM4_CK>;
 283                         clock-names = "mux";
 284                         status = "disabled";
 285
 286                         pwm {
 287                                 compatible = "st,stm32-pwm-lp";
 288                                 status = "disabled";
 289                         };
 290                 };
 291
 292                 lptimer5: timer@58003000 {
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         compatible = "st,stm32-lptimer";
 296                         reg = <0x58003000 0x400>;
 297                         clocks = <&rcc LPTIM5_CK>;
 298                         clock-names = "mux";
 299                         status = "disabled";
 300
 301                         pwm {
 302                                 compatible = "st,stm32-pwm-lp";
 303                                 status = "disabled";
 304                         };
 305                 };
 306
 307                 vrefbuf: regulator@58003C00 {
 308                         compatible = "st,stm32-vrefbuf";
 309                         reg = <0x58003C00 0x8>;
 310                         clocks = <&rcc VREF_CK>;
 311                         regulator-min-microvolt = <1500000>;
 312                         regulator-max-microvolt = <2500000>;
 313                         status = "disabled";
 314                 };
 315
 316                 rcc: reset-clock-controller@58024400 {
 317                         compatible = "st,stm32h743-rcc", "st,stm32-rcc";
 318                         reg = <0x58024400 0x400>;
 319                         #clock-cells = <1>;
 320                         #reset-cells = <1>;
 321                         clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
 322                         st,syscfg = <&pwrcfg>;
 323                 };
 324
 325                 pwrcfg: power-config@58024800 {
 326                         compatible = "syscon";
 327                         reg = <0x58024800 0x400>;
 328                 };
 329
 330                 adc_3: adc@58026000 {
 331                         compatible = "st,stm32h7-adc-core";
 332                         reg = <0x58026000 0x400>;
 333                         interrupts = <127>;
 334                         clocks = <&rcc ADC3_CK>;
 335                         clock-names = "bus";
 336                         interrupt-controller;
 337                         #interrupt-cells = <1>;
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         status = "disabled";
 341
 342                         adc3: adc@0 {
 343                                 compatible = "st,stm32h7-adc";
 344                                 #io-channel-cells = <1>;
 345                                 reg = <0x0>;
 346                                 interrupt-parent = <&adc_3>;
 347                                 interrupts = <0>;
 348                                 status = "disabled";
 349                         };
 350                 };
 351         };
 352 };
 353
 354 &systick {
 355         clock-frequency = <250000000>;
 356         status = "okay";
 357 };