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workqueue: avoid hard lockups in show_workqueue_state()
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / sun4i-a10.dtsi
1 /*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
48
49 / {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
53
54 aliases {
55 ethernet0 = &emac;
56 };
57
58 chosen {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
65 "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
70 status = "disabled";
71 };
72
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer";
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
82 status = "disabled";
83 };
84
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
87 "simple-framebuffer";
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
93 status = "disabled";
94 };
95
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
98 "simple-framebuffer";
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
105 status = "disabled";
106 };
107 };
108
109 cpus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 cpu0: cpu@0 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a8";
115 reg = <0x0>;
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
118 operating-points = <
119 /* kHz uV */
120 1008000 1400000
121 912000 1350000
122 864000 1300000
123 624000 1250000
124 >;
125 #cooling-cells = <2>;
126 cooling-min-level = <0>;
127 cooling-max-level = <3>;
128 };
129 };
130
131 thermal-zones {
132 cpu-thermal {
133 /* milliseconds */
134 polling-delay-passive = <250>;
135 polling-delay = <1000>;
136 thermal-sensors = <&rtp>;
137
138 cooling-maps {
139 map0 {
140 trip = <&cpu_alert0>;
141 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
142 };
143 };
144
145 trips {
146 cpu_alert0: cpu-alert0 {
147 /* milliCelsius */
148 temperature = <850000>;
149 hysteresis = <2000>;
150 type = "passive";
151 };
152
153 cpu_crit: cpu-crit {
154 /* milliCelsius */
155 temperature = <100000>;
156 hysteresis = <2000>;
157 type = "critical";
158 };
159 };
160 };
161 };
162
163 clocks {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges;
167
168 osc24M: clk-24M {
169 #clock-cells = <0>;
170 compatible = "fixed-clock";
171 clock-frequency = <24000000>;
172 clock-output-names = "osc24M";
173 };
174
175 osc32k: clk-32k {
176 #clock-cells = <0>;
177 compatible = "fixed-clock";
178 clock-frequency = <32768>;
179 clock-output-names = "osc32k";
180 };
181 };
182
183 de: display-engine {
184 compatible = "allwinner,sun4i-a10-display-engine";
185 allwinner,pipelines = <&fe0>, <&fe1>;
186 status = "disabled";
187 };
188
189 soc {
190 compatible = "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges;
194
195 sram-controller@1c00000 {
196 compatible = "allwinner,sun4i-a10-sram-controller";
197 reg = <0x01c00000 0x30>;
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges;
201
202 sram_a: sram@0 {
203 compatible = "mmio-sram";
204 reg = <0x00000000 0xc000>;
205 #address-cells = <1>;
206 #size-cells = <1>;
207 ranges = <0 0x00000000 0xc000>;
208
209 emac_sram: sram-section@8000 {
210 compatible = "allwinner,sun4i-a10-sram-a3-a4";
211 reg = <0x8000 0x4000>;
212 status = "disabled";
213 };
214 };
215
216 sram_d: sram@10000 {
217 compatible = "mmio-sram";
218 reg = <0x00010000 0x1000>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 ranges = <0 0x00010000 0x1000>;
222
223 otg_sram: sram-section@0 {
224 compatible = "allwinner,sun4i-a10-sram-d";
225 reg = <0x0000 0x1000>;
226 status = "disabled";
227 };
228 };
229 };
230
231 dma: dma-controller@1c02000 {
232 compatible = "allwinner,sun4i-a10-dma";
233 reg = <0x01c02000 0x1000>;
234 interrupts = <27>;
235 clocks = <&ccu CLK_AHB_DMA>;
236 #dma-cells = <2>;
237 };
238
239 nfc: nand@1c03000 {
240 compatible = "allwinner,sun4i-a10-nand";
241 reg = <0x01c03000 0x1000>;
242 interrupts = <37>;
243 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
244 clock-names = "ahb", "mod";
245 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
246 dma-names = "rxtx";
247 status = "disabled";
248 #address-cells = <1>;
249 #size-cells = <0>;
250 };
251
252 spi0: spi@1c05000 {
253 compatible = "allwinner,sun4i-a10-spi";
254 reg = <0x01c05000 0x1000>;
255 interrupts = <10>;
256 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
257 clock-names = "ahb", "mod";
258 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
259 <&dma SUN4I_DMA_DEDICATED 26>;
260 dma-names = "rx", "tx";
261 status = "disabled";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 };
265
266 spi1: spi@1c06000 {
267 compatible = "allwinner,sun4i-a10-spi";
268 reg = <0x01c06000 0x1000>;
269 interrupts = <11>;
270 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
271 clock-names = "ahb", "mod";
272 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
273 <&dma SUN4I_DMA_DEDICATED 8>;
274 dma-names = "rx", "tx";
275 pinctrl-names = "default";
276 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
277 status = "disabled";
278 #address-cells = <1>;
279 #size-cells = <0>;
280 };
281
282 emac: ethernet@1c0b000 {
283 compatible = "allwinner,sun4i-a10-emac";
284 reg = <0x01c0b000 0x1000>;
285 interrupts = <55>;
286 clocks = <&ccu CLK_AHB_EMAC>;
287 allwinner,sram = <&emac_sram 1>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&emac_pins>;
290 status = "disabled";
291 };
292
293 mdio: mdio@1c0b080 {
294 compatible = "allwinner,sun4i-a10-mdio";
295 reg = <0x01c0b080 0x14>;
296 status = "disabled";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 };
300
301 tcon0: lcd-controller@1c0c000 {
302 compatible = "allwinner,sun4i-a10-tcon";
303 reg = <0x01c0c000 0x1000>;
304 interrupts = <44>;
305 resets = <&ccu RST_TCON0>;
306 reset-names = "lcd";
307 clocks = <&ccu CLK_AHB_LCD0>,
308 <&ccu CLK_TCON0_CH0>,
309 <&ccu CLK_TCON0_CH1>;
310 clock-names = "ahb",
311 "tcon-ch0",
312 "tcon-ch1";
313 clock-output-names = "tcon0-pixel-clock";
314 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
315
316 ports {
317 #address-cells = <1>;
318 #size-cells = <0>;
319
320 tcon0_in: port@0 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 reg = <0>;
324
325 tcon0_in_be0: endpoint@0 {
326 reg = <0>;
327 remote-endpoint = <&be0_out_tcon0>;
328 };
329
330 tcon0_in_be1: endpoint@1 {
331 reg = <1>;
332 remote-endpoint = <&be1_out_tcon0>;
333 };
334 };
335
336 tcon0_out: port@1 {
337 #address-cells = <1>;
338 #size-cells = <0>;
339 reg = <1>;
340
341 tcon0_out_hdmi: endpoint@1 {
342 reg = <1>;
343 remote-endpoint = <&hdmi_in_tcon0>;
344 allwinner,tcon-channel = <1>;
345 };
346 };
347 };
348 };
349
350 tcon1: lcd-controller@1c0d000 {
351 compatible = "allwinner,sun4i-a10-tcon";
352 reg = <0x01c0d000 0x1000>;
353 interrupts = <45>;
354 resets = <&ccu RST_TCON1>;
355 reset-names = "lcd";
356 clocks = <&ccu CLK_AHB_LCD1>,
357 <&ccu CLK_TCON1_CH0>,
358 <&ccu CLK_TCON1_CH1>;
359 clock-names = "ahb",
360 "tcon-ch0",
361 "tcon-ch1";
362 clock-output-names = "tcon1-pixel-clock";
363 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
364
365 ports {
366 #address-cells = <1>;
367 #size-cells = <0>;
368
369 tcon1_in: port@0 {
370 #address-cells = <1>;
371 #size-cells = <0>;
372 reg = <0>;
373
374 tcon1_in_be0: endpoint@0 {
375 reg = <0>;
376 remote-endpoint = <&be0_out_tcon1>;
377 };
378
379 tcon1_in_be1: endpoint@1 {
380 reg = <1>;
381 remote-endpoint = <&be1_out_tcon1>;
382 };
383 };
384
385 tcon1_out: port@1 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 reg = <1>;
389
390 tcon1_out_hdmi: endpoint@1 {
391 reg = <1>;
392 remote-endpoint = <&hdmi_in_tcon1>;
393 allwinner,tcon-channel = <1>;
394 };
395 };
396 };
397 };
398
399 mmc0: mmc@1c0f000 {
400 compatible = "allwinner,sun4i-a10-mmc";
401 reg = <0x01c0f000 0x1000>;
402 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
403 clock-names = "ahb", "mmc";
404 interrupts = <32>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&mmc0_pins>;
407 status = "disabled";
408 #address-cells = <1>;
409 #size-cells = <0>;
410 };
411
412 mmc1: mmc@1c10000 {
413 compatible = "allwinner,sun4i-a10-mmc";
414 reg = <0x01c10000 0x1000>;
415 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
416 clock-names = "ahb", "mmc";
417 interrupts = <33>;
418 status = "disabled";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 };
422
423 mmc2: mmc@1c11000 {
424 compatible = "allwinner,sun4i-a10-mmc";
425 reg = <0x01c11000 0x1000>;
426 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
427 clock-names = "ahb", "mmc";
428 interrupts = <34>;
429 status = "disabled";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 };
433
434 mmc3: mmc@1c12000 {
435 compatible = "allwinner,sun4i-a10-mmc";
436 reg = <0x01c12000 0x1000>;
437 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
438 clock-names = "ahb", "mmc";
439 interrupts = <35>;
440 status = "disabled";
441 #address-cells = <1>;
442 #size-cells = <0>;
443 };
444
445 usb_otg: usb@1c13000 {
446 compatible = "allwinner,sun4i-a10-musb";
447 reg = <0x01c13000 0x0400>;
448 clocks = <&ccu CLK_AHB_OTG>;
449 interrupts = <38>;
450 interrupt-names = "mc";
451 phys = <&usbphy 0>;
452 phy-names = "usb";
453 extcon = <&usbphy 0>;
454 allwinner,sram = <&otg_sram 1>;
455 status = "disabled";
456 };
457
458 usbphy: phy@1c13400 {
459 #phy-cells = <1>;
460 compatible = "allwinner,sun4i-a10-usb-phy";
461 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
462 reg-names = "phy_ctrl", "pmu1", "pmu2";
463 clocks = <&ccu CLK_USB_PHY>;
464 clock-names = "usb_phy";
465 resets = <&ccu RST_USB_PHY0>,
466 <&ccu RST_USB_PHY1>,
467 <&ccu RST_USB_PHY2>;
468 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
469 status = "disabled";
470 };
471
472 ehci0: usb@1c14000 {
473 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
474 reg = <0x01c14000 0x100>;
475 interrupts = <39>;
476 clocks = <&ccu CLK_AHB_EHCI0>;
477 phys = <&usbphy 1>;
478 phy-names = "usb";
479 status = "disabled";
480 };
481
482 ohci0: usb@1c14400 {
483 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
484 reg = <0x01c14400 0x100>;
485 interrupts = <64>;
486 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
487 phys = <&usbphy 1>;
488 phy-names = "usb";
489 status = "disabled";
490 };
491
492 crypto: crypto-engine@1c15000 {
493 compatible = "allwinner,sun4i-a10-crypto";
494 reg = <0x01c15000 0x1000>;
495 interrupts = <86>;
496 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
497 clock-names = "ahb", "mod";
498 };
499
500 hdmi: hdmi@1c16000 {
501 compatible = "allwinner,sun4i-a10-hdmi";
502 reg = <0x01c16000 0x1000>;
503 interrupts = <58>;
504 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
505 <&ccu 9>,
506 <&ccu 18>;
507 clock-names = "ahb", "mod", "pll-0", "pll-1";
508 dmas = <&dma SUN4I_DMA_NORMAL 16>,
509 <&dma SUN4I_DMA_NORMAL 16>,
510 <&dma SUN4I_DMA_DEDICATED 24>;
511 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
512 status = "disabled";
513
514 ports {
515 #address-cells = <1>;
516 #size-cells = <0>;
517
518 hdmi_in: port@0 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 reg = <0>;
522
523 hdmi_in_tcon0: endpoint@0 {
524 reg = <0>;
525 remote-endpoint = <&tcon0_out_hdmi>;
526 };
527
528 hdmi_in_tcon1: endpoint@1 {
529 reg = <1>;
530 remote-endpoint = <&tcon1_out_hdmi>;
531 };
532 };
533
534 hdmi_out: port@1 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 reg = <1>;
538 };
539 };
540 };
541
542 spi2: spi@1c17000 {
543 compatible = "allwinner,sun4i-a10-spi";
544 reg = <0x01c17000 0x1000>;
545 interrupts = <12>;
546 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
547 clock-names = "ahb", "mod";
548 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
549 <&dma SUN4I_DMA_DEDICATED 28>;
550 dma-names = "rx", "tx";
551 status = "disabled";
552 #address-cells = <1>;
553 #size-cells = <0>;
554 };
555
556 ahci: sata@1c18000 {
557 compatible = "allwinner,sun4i-a10-ahci";
558 reg = <0x01c18000 0x1000>;
559 interrupts = <56>;
560 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
561 status = "disabled";
562 };
563
564 ehci1: usb@1c1c000 {
565 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
566 reg = <0x01c1c000 0x100>;
567 interrupts = <40>;
568 clocks = <&ccu CLK_AHB_EHCI1>;
569 phys = <&usbphy 2>;
570 phy-names = "usb";
571 status = "disabled";
572 };
573
574 ohci1: usb@1c1c400 {
575 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
576 reg = <0x01c1c400 0x100>;
577 interrupts = <65>;
578 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
579 phys = <&usbphy 2>;
580 phy-names = "usb";
581 status = "disabled";
582 };
583
584 spi3: spi@1c1f000 {
585 compatible = "allwinner,sun4i-a10-spi";
586 reg = <0x01c1f000 0x1000>;
587 interrupts = <50>;
588 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
589 clock-names = "ahb", "mod";
590 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
591 <&dma SUN4I_DMA_DEDICATED 30>;
592 dma-names = "rx", "tx";
593 status = "disabled";
594 #address-cells = <1>;
595 #size-cells = <0>;
596 };
597
598 ccu: clock@1c20000 {
599 compatible = "allwinner,sun4i-a10-ccu";
600 reg = <0x01c20000 0x400>;
601 clocks = <&osc24M>, <&osc32k>;
602 clock-names = "hosc", "losc";
603 #clock-cells = <1>;
604 #reset-cells = <1>;
605 };
606
607 intc: interrupt-controller@1c20400 {
608 compatible = "allwinner,sun4i-a10-ic";
609 reg = <0x01c20400 0x400>;
610 interrupt-controller;
611 #interrupt-cells = <1>;
612 };
613
614 pio: pinctrl@1c20800 {
615 compatible = "allwinner,sun4i-a10-pinctrl";
616 reg = <0x01c20800 0x400>;
617 interrupts = <28>;
618 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
619 clock-names = "apb", "hosc", "losc";
620 gpio-controller;
621 interrupt-controller;
622 #interrupt-cells = <3>;
623 #gpio-cells = <3>;
624
625 can0_ph_pins: can0-ph-pins {
626 pins = "PH20", "PH21";
627 function = "can";
628 };
629
630 emac_pins: emac0-pins {
631 pins = "PA0", "PA1", "PA2",
632 "PA3", "PA4", "PA5", "PA6",
633 "PA7", "PA8", "PA9", "PA10",
634 "PA11", "PA12", "PA13", "PA14",
635 "PA15", "PA16";
636 function = "emac";
637 };
638
639 i2c0_pins: i2c0-pins {
640 pins = "PB0", "PB1";
641 function = "i2c0";
642 };
643
644 i2c1_pins: i2c1-pins {
645 pins = "PB18", "PB19";
646 function = "i2c1";
647 };
648
649 i2c2_pins: i2c2-pins {
650 pins = "PB20", "PB21";
651 function = "i2c2";
652 };
653
654 ir0_rx_pins: ir0-rx-pin {
655 pins = "PB4";
656 function = "ir0";
657 };
658
659 ir0_tx_pins: ir0-tx-pin {
660 pins = "PB3";
661 function = "ir0";
662 };
663
664 ir1_rx_pins: ir1-rx-pin {
665 pins = "PB23";
666 function = "ir1";
667 };
668
669 ir1_tx_pins: ir1-tx-pin {
670 pins = "PB22";
671 function = "ir1";
672 };
673
674 mmc0_pins: mmc0-pins {
675 pins = "PF0", "PF1", "PF2",
676 "PF3", "PF4", "PF5";
677 function = "mmc0";
678 drive-strength = <30>;
679 bias-pull-up;
680 };
681
682 ps2_ch0_pins: ps2-ch0-pins {
683 pins = "PI20", "PI21";
684 function = "ps2";
685 };
686
687 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
688 pins = "PH12", "PH13";
689 function = "ps2";
690 };
691
692 pwm0_pin: pwm0-pin {
693 pins = "PB2";
694 function = "pwm";
695 };
696
697 pwm1_pin: pwm1-pin {
698 pins = "PI3";
699 function = "pwm";
700 };
701
702 spdif_tx_pin: spdif-tx-pin {
703 pins = "PB13";
704 function = "spdif";
705 bias-pull-up;
706 };
707
708 spi0_pi_pins: spi0-pi-pins {
709 pins = "PI11", "PI12", "PI13";
710 function = "spi0";
711 };
712
713 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
714 pins = "PI10";
715 function = "spi0";
716 };
717
718 spi1_pins: spi1-pins {
719 pins = "PI17", "PI18", "PI19";
720 function = "spi1";
721 };
722
723 spi1_cs0_pin: spi1-cs0-pin {
724 pins = "PI16";
725 function = "spi1";
726 };
727
728 spi2_pb_pins: spi2-pb-pins {
729 pins = "PB15", "PB16", "PB17";
730 function = "spi2";
731 };
732
733 spi2_pc_pins: spi2-pc-pins {
734 pins = "PC20", "PC21", "PC22";
735 function = "spi2";
736 };
737
738 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
739 pins = "PB14";
740 function = "spi2";
741 };
742
743 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
744 pins = "PC19";
745 function = "spi2";
746 };
747
748 uart0_pb_pins: uart0-pb-pins {
749 pins = "PB22", "PB23";
750 function = "uart0";
751 };
752
753 uart0_pf_pins: uart0-pf-pins {
754 pins = "PF2", "PF4";
755 function = "uart0";
756 };
757
758 uart1_pins: uart1-pins {
759 pins = "PA10", "PA11";
760 function = "uart1";
761 };
762 };
763
764 timer@1c20c00 {
765 compatible = "allwinner,sun4i-a10-timer";
766 reg = <0x01c20c00 0x90>;
767 interrupts = <22>;
768 clocks = <&osc24M>;
769 };
770
771 wdt: watchdog@1c20c90 {
772 compatible = "allwinner,sun4i-a10-wdt";
773 reg = <0x01c20c90 0x10>;
774 };
775
776 rtc: rtc@1c20d00 {
777 compatible = "allwinner,sun4i-a10-rtc";
778 reg = <0x01c20d00 0x20>;
779 interrupts = <24>;
780 };
781
782 pwm: pwm@1c20e00 {
783 compatible = "allwinner,sun4i-a10-pwm";
784 reg = <0x01c20e00 0xc>;
785 clocks = <&osc24M>;
786 #pwm-cells = <3>;
787 status = "disabled";
788 };
789
790 spdif: spdif@1c21000 {
791 #sound-dai-cells = <0>;
792 compatible = "allwinner,sun4i-a10-spdif";
793 reg = <0x01c21000 0x400>;
794 interrupts = <13>;
795 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
796 clock-names = "apb", "spdif";
797 dmas = <&dma SUN4I_DMA_NORMAL 2>,
798 <&dma SUN4I_DMA_NORMAL 2>;
799 dma-names = "rx", "tx";
800 status = "disabled";
801 };
802
803 ir0: ir@1c21800 {
804 compatible = "allwinner,sun4i-a10-ir";
805 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
806 clock-names = "apb", "ir";
807 interrupts = <5>;
808 reg = <0x01c21800 0x40>;
809 status = "disabled";
810 };
811
812 ir1: ir@1c21c00 {
813 compatible = "allwinner,sun4i-a10-ir";
814 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
815 clock-names = "apb", "ir";
816 interrupts = <6>;
817 reg = <0x01c21c00 0x40>;
818 status = "disabled";
819 };
820
821 i2s0: i2s@1c22400 {
822 #sound-dai-cells = <0>;
823 compatible = "allwinner,sun4i-a10-i2s";
824 reg = <0x01c22400 0x400>;
825 interrupts = <16>;
826 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
827 clock-names = "apb", "mod";
828 dmas = <&dma SUN4I_DMA_NORMAL 3>,
829 <&dma SUN4I_DMA_NORMAL 3>;
830 dma-names = "rx", "tx";
831 status = "disabled";
832 };
833
834 lradc: lradc@1c22800 {
835 compatible = "allwinner,sun4i-a10-lradc-keys";
836 reg = <0x01c22800 0x100>;
837 interrupts = <31>;
838 status = "disabled";
839 };
840
841 codec: codec@1c22c00 {
842 #sound-dai-cells = <0>;
843 compatible = "allwinner,sun4i-a10-codec";
844 reg = <0x01c22c00 0x40>;
845 interrupts = <30>;
846 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
847 clock-names = "apb", "codec";
848 dmas = <&dma SUN4I_DMA_NORMAL 19>,
849 <&dma SUN4I_DMA_NORMAL 19>;
850 dma-names = "rx", "tx";
851 status = "disabled";
852 };
853
854 sid: eeprom@1c23800 {
855 compatible = "allwinner,sun4i-a10-sid";
856 reg = <0x01c23800 0x10>;
857 };
858
859 rtp: rtp@1c25000 {
860 compatible = "allwinner,sun4i-a10-ts";
861 reg = <0x01c25000 0x100>;
862 interrupts = <29>;
863 #thermal-sensor-cells = <0>;
864 };
865
866 uart0: serial@1c28000 {
867 compatible = "snps,dw-apb-uart";
868 reg = <0x01c28000 0x400>;
869 interrupts = <1>;
870 reg-shift = <2>;
871 reg-io-width = <4>;
872 clocks = <&ccu CLK_APB1_UART0>;
873 status = "disabled";
874 };
875
876 uart1: serial@1c28400 {
877 compatible = "snps,dw-apb-uart";
878 reg = <0x01c28400 0x400>;
879 interrupts = <2>;
880 reg-shift = <2>;
881 reg-io-width = <4>;
882 clocks = <&ccu CLK_APB1_UART1>;
883 status = "disabled";
884 };
885
886 uart2: serial@1c28800 {
887 compatible = "snps,dw-apb-uart";
888 reg = <0x01c28800 0x400>;
889 interrupts = <3>;
890 reg-shift = <2>;
891 reg-io-width = <4>;
892 clocks = <&ccu CLK_APB1_UART2>;
893 status = "disabled";
894 };
895
896 uart3: serial@1c28c00 {
897 compatible = "snps,dw-apb-uart";
898 reg = <0x01c28c00 0x400>;
899 interrupts = <4>;
900 reg-shift = <2>;
901 reg-io-width = <4>;
902 clocks = <&ccu CLK_APB1_UART3>;
903 status = "disabled";
904 };
905
906 uart4: serial@1c29000 {
907 compatible = "snps,dw-apb-uart";
908 reg = <0x01c29000 0x400>;
909 interrupts = <17>;
910 reg-shift = <2>;
911 reg-io-width = <4>;
912 clocks = <&ccu CLK_APB1_UART4>;
913 status = "disabled";
914 };
915
916 uart5: serial@1c29400 {
917 compatible = "snps,dw-apb-uart";
918 reg = <0x01c29400 0x400>;
919 interrupts = <18>;
920 reg-shift = <2>;
921 reg-io-width = <4>;
922 clocks = <&ccu CLK_APB1_UART5>;
923 status = "disabled";
924 };
925
926 uart6: serial@1c29800 {
927 compatible = "snps,dw-apb-uart";
928 reg = <0x01c29800 0x400>;
929 interrupts = <19>;
930 reg-shift = <2>;
931 reg-io-width = <4>;
932 clocks = <&ccu CLK_APB1_UART6>;
933 status = "disabled";
934 };
935
936 uart7: serial@1c29c00 {
937 compatible = "snps,dw-apb-uart";
938 reg = <0x01c29c00 0x400>;
939 interrupts = <20>;
940 reg-shift = <2>;
941 reg-io-width = <4>;
942 clocks = <&ccu CLK_APB1_UART7>;
943 status = "disabled";
944 };
945
946 ps20: ps2@1c2a000 {
947 compatible = "allwinner,sun4i-a10-ps2";
948 reg = <0x01c2a000 0x400>;
949 interrupts = <62>;
950 clocks = <&ccu CLK_APB1_PS20>;
951 status = "disabled";
952 };
953
954 ps21: ps2@1c2a400 {
955 compatible = "allwinner,sun4i-a10-ps2";
956 reg = <0x01c2a400 0x400>;
957 interrupts = <63>;
958 clocks = <&ccu CLK_APB1_PS21>;
959 status = "disabled";
960 };
961
962 i2c0: i2c@1c2ac00 {
963 compatible = "allwinner,sun4i-a10-i2c";
964 reg = <0x01c2ac00 0x400>;
965 interrupts = <7>;
966 clocks = <&ccu CLK_APB1_I2C0>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&i2c0_pins>;
969 status = "disabled";
970 #address-cells = <1>;
971 #size-cells = <0>;
972 };
973
974 i2c1: i2c@1c2b000 {
975 compatible = "allwinner,sun4i-a10-i2c";
976 reg = <0x01c2b000 0x400>;
977 interrupts = <8>;
978 clocks = <&ccu CLK_APB1_I2C1>;
979 pinctrl-names = "default";
980 pinctrl-0 = <&i2c1_pins>;
981 status = "disabled";
982 #address-cells = <1>;
983 #size-cells = <0>;
984 };
985
986 i2c2: i2c@1c2b400 {
987 compatible = "allwinner,sun4i-a10-i2c";
988 reg = <0x01c2b400 0x400>;
989 interrupts = <9>;
990 clocks = <&ccu CLK_APB1_I2C2>;
991 pinctrl-names = "default";
992 pinctrl-0 = <&i2c2_pins>;
993 status = "disabled";
994 #address-cells = <1>;
995 #size-cells = <0>;
996 };
997
998 can0: can@1c2bc00 {
999 compatible = "allwinner,sun4i-a10-can";
1000 reg = <0x01c2bc00 0x400>;
1001 interrupts = <26>;
1002 clocks = <&ccu CLK_APB1_CAN>;
1003 status = "disabled";
1004 };
1005
1006 fe0: display-frontend@1e00000 {
1007 compatible = "allwinner,sun4i-a10-display-frontend";
1008 reg = <0x01e00000 0x20000>;
1009 interrupts = <47>;
1010 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1011 <&ccu CLK_DRAM_DE_FE0>;
1012 clock-names = "ahb", "mod",
1013 "ram";
1014 resets = <&ccu RST_DE_FE0>;
1015
1016 ports {
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019
1020 fe0_out: port@1 {
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 reg = <1>;
1024
1025 fe0_out_be0: endpoint@0 {
1026 reg = <0>;
1027 remote-endpoint = <&be0_in_fe0>;
1028 };
1029
1030 fe0_out_be1: endpoint@1 {
1031 reg = <1>;
1032 remote-endpoint = <&be1_in_fe0>;
1033 };
1034 };
1035 };
1036 };
1037
1038 fe1: display-frontend@1e20000 {
1039 compatible = "allwinner,sun4i-a10-display-frontend";
1040 reg = <0x01e20000 0x20000>;
1041 interrupts = <48>;
1042 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1043 <&ccu CLK_DRAM_DE_FE1>;
1044 clock-names = "ahb", "mod",
1045 "ram";
1046 resets = <&ccu RST_DE_FE1>;
1047
1048 ports {
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051
1052 fe1_out: port@1 {
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 reg = <1>;
1056
1057 fe1_out_be0: endpoint@0 {
1058 reg = <0>;
1059 remote-endpoint = <&be0_in_fe1>;
1060 };
1061
1062 fe1_out_be1: endpoint@1 {
1063 reg = <1>;
1064 remote-endpoint = <&be1_in_fe1>;
1065 };
1066 };
1067 };
1068 };
1069
1070 be1: display-backend@1e40000 {
1071 compatible = "allwinner,sun4i-a10-display-backend";
1072 reg = <0x01e40000 0x10000>;
1073 interrupts = <48>;
1074 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1075 <&ccu CLK_DRAM_DE_BE1>;
1076 clock-names = "ahb", "mod",
1077 "ram";
1078 resets = <&ccu RST_DE_BE1>;
1079
1080 ports {
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1083
1084 be1_in: port@0 {
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1087 reg = <0>;
1088
1089 be1_in_fe0: endpoint@0 {
1090 reg = <0>;
1091 remote-endpoint = <&fe0_out_be1>;
1092 };
1093
1094 be1_in_fe1: endpoint@1 {
1095 reg = <1>;
1096 remote-endpoint = <&fe1_out_be1>;
1097 };
1098 };
1099
1100 be1_out: port@1 {
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1103 reg = <1>;
1104
1105 be1_out_tcon0: endpoint@0 {
1106 reg = <0>;
1107 remote-endpoint = <&tcon1_in_be0>;
1108 };
1109
1110 be1_out_tcon1: endpoint@1 {
1111 reg = <1>;
1112 remote-endpoint = <&tcon1_in_be1>;
1113 };
1114 };
1115 };
1116 };
1117
1118 be0: display-backend@1e60000 {
1119 compatible = "allwinner,sun4i-a10-display-backend";
1120 reg = <0x01e60000 0x10000>;
1121 interrupts = <47>;
1122 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1123 <&ccu CLK_DRAM_DE_BE0>;
1124 clock-names = "ahb", "mod",
1125 "ram";
1126 resets = <&ccu RST_DE_BE0>;
1127
1128 ports {
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131
1132 be0_in: port@0 {
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135 reg = <0>;
1136
1137 be0_in_fe0: endpoint@0 {
1138 reg = <0>;
1139 remote-endpoint = <&fe0_out_be0>;
1140 };
1141
1142 be0_in_fe1: endpoint@1 {
1143 reg = <1>;
1144 remote-endpoint = <&fe1_out_be0>;
1145 };
1146 };
1147
1148 be0_out: port@1 {
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151 reg = <1>;
1152
1153 be0_out_tcon0: endpoint@0 {
1154 reg = <0>;
1155 remote-endpoint = <&tcon0_in_be0>;
1156 };
1157
1158 be0_out_tcon1: endpoint@1 {
1159 reg = <1>;
1160 remote-endpoint = <&tcon1_in_be0>;
1161 };
1162 };
1163 };
1164 };
1165 };
1166 };
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