arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         aliases {
  20                 ethernet0 = &emac;
  21         };
  22
  23         chosen {
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26                 ranges;
  27
  28                 framebuffer@0 {
  29                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  30                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  31                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  32                                  <&ahb_gates 44>;
  33                         status = "disabled";
  34                 };
  35         };
  36
  37         cpus {
  38                 cpu@0 {
  39                         compatible = "arm,cortex-a8";
  40                 };
  41         };
  42
  43         memory {
  44                 reg = <0x40000000 0x20000000>;
  45         };
  46
  47         clocks {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges;
  51
  52                 /*
  53                  * This is a dummy clock, to be used as placeholder on
  54                  * other mux clocks when a specific parent clock is not
  55                  * yet implemented. It should be dropped when the driver
  56                  * is complete.
  57                  */
  58                 dummy: dummy {
  59                         #clock-cells = <0>;
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <0>;
  62                 };
  63
  64                 osc24M: clk@01c20050 {
  65                         #clock-cells = <0>;
  66                         compatible = "allwinner,sun4i-a10-osc-clk";
  67                         reg = <0x01c20050 0x4>;
  68                         clock-frequency = <24000000>;
  69                         clock-output-names = "osc24M";
  70                 };
  71
  72                 osc32k: clk@0 {
  73                         #clock-cells = <0>;
  74                         compatible = "fixed-clock";
  75                         clock-frequency = <32768>;
  76                         clock-output-names = "osc32k";
  77                 };
  78
  79                 pll1: clk@01c20000 {
  80                         #clock-cells = <0>;
  81                         compatible = "allwinner,sun4i-a10-pll1-clk";
  82                         reg = <0x01c20000 0x4>;
  83                         clocks = <&osc24M>;
  84                         clock-output-names = "pll1";
  85                 };
  86
  87                 pll4: clk@01c20018 {
  88                         #clock-cells = <0>;
  89                         compatible = "allwinner,sun4i-a10-pll1-clk";
  90                         reg = <0x01c20018 0x4>;
  91                         clocks = <&osc24M>;
  92                         clock-output-names = "pll4";
  93                 };
  94
  95                 pll5: clk@01c20020 {
  96                         #clock-cells = <1>;
  97                         compatible = "allwinner,sun4i-a10-pll5-clk";
  98                         reg = <0x01c20020 0x4>;
  99                         clocks = <&osc24M>;
 100                         clock-output-names = "pll5_ddr", "pll5_other";
 101                 };
 102
 103                 pll6: clk@01c20028 {
 104                         #clock-cells = <1>;
 105                         compatible = "allwinner,sun4i-a10-pll6-clk";
 106                         reg = <0x01c20028 0x4>;
 107                         clocks = <&osc24M>;
 108                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 109                 };
 110
 111                 /* dummy is 200M */
 112                 cpu: cpu@01c20054 {
 113                         #clock-cells = <0>;
 114                         compatible = "allwinner,sun4i-a10-cpu-clk";
 115                         reg = <0x01c20054 0x4>;
 116                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 117                         clock-output-names = "cpu";
 118                 };
 119
 120                 axi: axi@01c20054 {
 121                         #clock-cells = <0>;
 122                         compatible = "allwinner,sun4i-a10-axi-clk";
 123                         reg = <0x01c20054 0x4>;
 124                         clocks = <&cpu>;
 125                         clock-output-names = "axi";
 126                 };
 127
 128                 axi_gates: clk@01c2005c {
 129                         #clock-cells = <1>;
 130                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 131                         reg = <0x01c2005c 0x4>;
 132                         clocks = <&axi>;
 133                         clock-output-names = "axi_dram";
 134                 };
 135
 136                 ahb: ahb@01c20054 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-a10-ahb-clk";
 139                         reg = <0x01c20054 0x4>;
 140                         clocks = <&axi>;
 141                         clock-output-names = "ahb";
 142                 };
 143
 144                 ahb_gates: clk@01c20060 {
 145                         #clock-cells = <1>;
 146                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 147                         reg = <0x01c20060 0x8>;
 148                         clocks = <&ahb>;
 149                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 150                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 151                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 152                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 153                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 154                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 155                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 156                 };
 157
 158                 apb0: apb0@01c20054 {
 159                         #clock-cells = <0>;
 160                         compatible = "allwinner,sun4i-a10-apb0-clk";
 161                         reg = <0x01c20054 0x4>;
 162                         clocks = <&ahb>;
 163                         clock-output-names = "apb0";
 164                 };
 165
 166                 apb0_gates: clk@01c20068 {
 167                         #clock-cells = <1>;
 168                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 169                         reg = <0x01c20068 0x4>;
 170                         clocks = <&apb0>;
 171                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 172                                 "apb0_ir", "apb0_keypad";
 173                 };
 174
 175                 apb1: clk@01c20058 {
 176                         #clock-cells = <0>;
 177                         compatible = "allwinner,sun4i-a10-apb1-clk";
 178                         reg = <0x01c20058 0x4>;
 179                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 180                         clock-output-names = "apb1";
 181                 };
 182
 183                 apb1_gates: clk@01c2006c {
 184                         #clock-cells = <1>;
 185                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 186                         reg = <0x01c2006c 0x4>;
 187                         clocks = <&apb1>;
 188                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 189                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 190                                 "apb1_uart2", "apb1_uart3";
 191                 };
 192
 193                 nand_clk: clk@01c20080 {
 194                         #clock-cells = <0>;
 195                         compatible = "allwinner,sun4i-a10-mod0-clk";
 196                         reg = <0x01c20080 0x4>;
 197                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 198                         clock-output-names = "nand";
 199                 };
 200
 201                 ms_clk: clk@01c20084 {
 202                         #clock-cells = <0>;
 203                         compatible = "allwinner,sun4i-a10-mod0-clk";
 204                         reg = <0x01c20084 0x4>;
 205                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 206                         clock-output-names = "ms";
 207                 };
 208
 209                 mmc0_clk: clk@01c20088 {
 210                         #clock-cells = <1>;
 211                         compatible = "allwinner,sun4i-a10-mmc-clk";
 212                         reg = <0x01c20088 0x4>;
 213                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 214                         clock-output-names = "mmc0",
 215                                              "mmc0_output",
 216                                              "mmc0_sample";
 217                 };
 218
 219                 mmc1_clk: clk@01c2008c {
 220                         #clock-cells = <1>;
 221                         compatible = "allwinner,sun4i-a10-mmc-clk";
 222                         reg = <0x01c2008c 0x4>;
 223                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 224                         clock-output-names = "mmc1",
 225                                              "mmc1_output",
 226                                              "mmc1_sample";
 227                 };
 228
 229                 mmc2_clk: clk@01c20090 {
 230                         #clock-cells = <1>;
 231                         compatible = "allwinner,sun4i-a10-mmc-clk";
 232                         reg = <0x01c20090 0x4>;
 233                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 234                         clock-output-names = "mmc2",
 235                                              "mmc2_output",
 236                                              "mmc2_sample";
 237                 };
 238
 239                 ts_clk: clk@01c20098 {
 240                         #clock-cells = <0>;
 241                         compatible = "allwinner,sun4i-a10-mod0-clk";
 242                         reg = <0x01c20098 0x4>;
 243                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 244                         clock-output-names = "ts";
 245                 };
 246
 247                 ss_clk: clk@01c2009c {
 248                         #clock-cells = <0>;
 249                         compatible = "allwinner,sun4i-a10-mod0-clk";
 250                         reg = <0x01c2009c 0x4>;
 251                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 252                         clock-output-names = "ss";
 253                 };
 254
 255                 spi0_clk: clk@01c200a0 {
 256                         #clock-cells = <0>;
 257                         compatible = "allwinner,sun4i-a10-mod0-clk";
 258                         reg = <0x01c200a0 0x4>;
 259                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 260                         clock-output-names = "spi0";
 261                 };
 262
 263                 spi1_clk: clk@01c200a4 {
 264                         #clock-cells = <0>;
 265                         compatible = "allwinner,sun4i-a10-mod0-clk";
 266                         reg = <0x01c200a4 0x4>;
 267                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 268                         clock-output-names = "spi1";
 269                 };
 270
 271                 spi2_clk: clk@01c200a8 {
 272                         #clock-cells = <0>;
 273                         compatible = "allwinner,sun4i-a10-mod0-clk";
 274                         reg = <0x01c200a8 0x4>;
 275                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 276                         clock-output-names = "spi2";
 277                 };
 278
 279                 ir0_clk: clk@01c200b0 {
 280                         #clock-cells = <0>;
 281                         compatible = "allwinner,sun4i-a10-mod0-clk";
 282                         reg = <0x01c200b0 0x4>;
 283                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 284                         clock-output-names = "ir0";
 285                 };
 286
 287                 usb_clk: clk@01c200cc {
 288                         #clock-cells = <1>;
 289                         #reset-cells = <1>;
 290                         compatible = "allwinner,sun5i-a13-usb-clk";
 291                         reg = <0x01c200cc 0x4>;
 292                         clocks = <&pll6 1>;
 293                         clock-output-names = "usb_ohci0", "usb_phy";
 294                 };
 295
 296                 mbus_clk: clk@01c2015c {
 297                         #clock-cells = <0>;
 298                         compatible = "allwinner,sun5i-a13-mbus-clk";
 299                         reg = <0x01c2015c 0x4>;
 300                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 301                         clock-output-names = "mbus";
 302                 };
 303         };
 304
 305         soc@01c00000 {
 306                 compatible = "simple-bus";
 307                 #address-cells = <1>;
 308                 #size-cells = <1>;
 309                 ranges;
 310
 311                 dma: dma-controller@01c02000 {
 312                         compatible = "allwinner,sun4i-a10-dma";
 313                         reg = <0x01c02000 0x1000>;
 314                         interrupts = <27>;
 315                         clocks = <&ahb_gates 6>;
 316                         #dma-cells = <2>;
 317                 };
 318
 319                 spi0: spi@01c05000 {
 320                         compatible = "allwinner,sun4i-a10-spi";
 321                         reg = <0x01c05000 0x1000>;
 322                         interrupts = <10>;
 323                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 324                         clock-names = "ahb", "mod";
 325                         dmas = <&dma 1 27>, <&dma 1 26>;
 326                         dma-names = "rx", "tx";
 327                         status = "disabled";
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                 };
 331
 332                 spi1: spi@01c06000 {
 333                         compatible = "allwinner,sun4i-a10-spi";
 334                         reg = <0x01c06000 0x1000>;
 335                         interrupts = <11>;
 336                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 337                         clock-names = "ahb", "mod";
 338                         dmas = <&dma 1 9>, <&dma 1 8>;
 339                         dma-names = "rx", "tx";
 340                         status = "disabled";
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                 };
 344
 345                 emac: ethernet@01c0b000 {
 346                         compatible = "allwinner,sun4i-a10-emac";
 347                         reg = <0x01c0b000 0x1000>;
 348                         interrupts = <55>;
 349                         clocks = <&ahb_gates 17>;
 350                         status = "disabled";
 351                 };
 352
 353                 mdio@01c0b080 {
 354                         compatible = "allwinner,sun4i-a10-mdio";
 355                         reg = <0x01c0b080 0x14>;
 356                         status = "disabled";
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                 };
 360
 361                 mmc0: mmc@01c0f000 {
 362                         compatible = "allwinner,sun5i-a13-mmc";
 363                         reg = <0x01c0f000 0x1000>;
 364                         clocks = <&ahb_gates 8>,
 365                                  <&mmc0_clk 0>,
 366                                  <&mmc0_clk 1>,
 367                                  <&mmc0_clk 2>;
 368                         clock-names = "ahb",
 369                                       "mmc",
 370                                       "output",
 371                                       "sample";
 372                         interrupts = <32>;
 373                         status = "disabled";
 374                 };
 375
 376                 mmc1: mmc@01c10000 {
 377                         compatible = "allwinner,sun5i-a13-mmc";
 378                         reg = <0x01c10000 0x1000>;
 379                         clocks = <&ahb_gates 9>,
 380                                  <&mmc1_clk 0>,
 381                                  <&mmc1_clk 1>,
 382                                  <&mmc1_clk 2>;
 383                         clock-names = "ahb",
 384                                       "mmc",
 385                                       "output",
 386                                       "sample";
 387                         interrupts = <33>;
 388                         status = "disabled";
 389                 };
 390
 391                 mmc2: mmc@01c11000 {
 392                         compatible = "allwinner,sun5i-a13-mmc";
 393                         reg = <0x01c11000 0x1000>;
 394                         clocks = <&ahb_gates 10>,
 395                                  <&mmc2_clk 0>,
 396                                  <&mmc2_clk 1>,
 397                                  <&mmc2_clk 2>;
 398                         clock-names = "ahb",
 399                                       "mmc",
 400                                       "output",
 401                                       "sample";
 402                         interrupts = <34>;
 403                         status = "disabled";
 404                 };
 405
 406                 usbphy: phy@01c13400 {
 407                         #phy-cells = <1>;
 408                         compatible = "allwinner,sun5i-a13-usb-phy";
 409                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 410                         reg-names = "phy_ctrl", "pmu1";
 411                         clocks = <&usb_clk 8>;
 412                         clock-names = "usb_phy";
 413                         resets = <&usb_clk 0>, <&usb_clk 1>;
 414                         reset-names = "usb0_reset", "usb1_reset";
 415                         status = "disabled";
 416                 };
 417
 418                 ehci0: usb@01c14000 {
 419                         compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
 420                         reg = <0x01c14000 0x100>;
 421                         interrupts = <39>;
 422                         clocks = <&ahb_gates 1>;
 423                         phys = <&usbphy 1>;
 424                         phy-names = "usb";
 425                         status = "disabled";
 426                 };
 427
 428                 ohci0: usb@01c14400 {
 429                         compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
 430                         reg = <0x01c14400 0x100>;
 431                         interrupts = <40>;
 432                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 433                         phys = <&usbphy 1>;
 434                         phy-names = "usb";
 435                         status = "disabled";
 436                 };
 437
 438                 spi2: spi@01c17000 {
 439                         compatible = "allwinner,sun4i-a10-spi";
 440                         reg = <0x01c17000 0x1000>;
 441                         interrupts = <12>;
 442                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 443                         clock-names = "ahb", "mod";
 444                         dmas = <&dma 1 29>, <&dma 1 28>;
 445                         dma-names = "rx", "tx";
 446                         status = "disabled";
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                 };
 450
 451                 intc: interrupt-controller@01c20400 {
 452                         compatible = "allwinner,sun4i-a10-ic";
 453                         reg = <0x01c20400 0x400>;
 454                         interrupt-controller;
 455                         #interrupt-cells = <1>;
 456                 };
 457
 458                 pio: pinctrl@01c20800 {
 459                         compatible = "allwinner,sun5i-a10s-pinctrl";
 460                         reg = <0x01c20800 0x400>;
 461                         interrupts = <28>;
 462                         clocks = <&apb0_gates 5>;
 463                         gpio-controller;
 464                         interrupt-controller;
 465                         #interrupt-cells = <2>;
 466                         #size-cells = <0>;
 467                         #gpio-cells = <3>;
 468
 469                         uart0_pins_a: uart0@0 {
 470                                 allwinner,pins = "PB19", "PB20";
 471                                 allwinner,function = "uart0";
 472                                 allwinner,drive = <0>;
 473                                 allwinner,pull = <0>;
 474                         };
 475
 476                         uart2_pins_a: uart2@0 {
 477                                 allwinner,pins = "PC18", "PC19";
 478                                 allwinner,function = "uart2";
 479                                 allwinner,drive = <0>;
 480                                 allwinner,pull = <0>;
 481                         };
 482
 483                         uart3_pins_a: uart3@0 {
 484                                 allwinner,pins = "PG9", "PG10";
 485                                 allwinner,function = "uart3";
 486                                 allwinner,drive = <0>;
 487                                 allwinner,pull = <0>;
 488                         };
 489
 490                         emac_pins_a: emac0@0 {
 491                                 allwinner,pins = "PA0", "PA1", "PA2",
 492                                                 "PA3", "PA4", "PA5", "PA6",
 493                                                 "PA7", "PA8", "PA9", "PA10",
 494                                                 "PA11", "PA12", "PA13", "PA14",
 495                                                 "PA15", "PA16";
 496                                 allwinner,function = "emac";
 497                                 allwinner,drive = <0>;
 498                                 allwinner,pull = <0>;
 499                         };
 500
 501                         i2c0_pins_a: i2c0@0 {
 502                                 allwinner,pins = "PB0", "PB1";
 503                                 allwinner,function = "i2c0";
 504                                 allwinner,drive = <0>;
 505                                 allwinner,pull = <0>;
 506                         };
 507
 508                         i2c1_pins_a: i2c1@0 {
 509                                 allwinner,pins = "PB15", "PB16";
 510                                 allwinner,function = "i2c1";
 511                                 allwinner,drive = <0>;
 512                                 allwinner,pull = <0>;
 513                         };
 514
 515                         i2c2_pins_a: i2c2@0 {
 516                                 allwinner,pins = "PB17", "PB18";
 517                                 allwinner,function = "i2c2";
 518                                 allwinner,drive = <0>;
 519                                 allwinner,pull = <0>;
 520                         };
 521
 522                         mmc0_pins_a: mmc0@0 {
 523                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 524                                 allwinner,function = "mmc0";
 525                                 allwinner,drive = <2>;
 526                                 allwinner,pull = <0>;
 527                         };
 528
 529                         mmc1_pins_a: mmc1@0 {
 530                                 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
 531                                 allwinner,function = "mmc1";
 532                                 allwinner,drive = <2>;
 533                                 allwinner,pull = <0>;
 534                         };
 535                 };
 536
 537                 timer@01c20c00 {
 538                         compatible = "allwinner,sun4i-a10-timer";
 539                         reg = <0x01c20c00 0x90>;
 540                         interrupts = <22>;
 541                         clocks = <&osc24M>;
 542                 };
 543
 544                 wdt: watchdog@01c20c90 {
 545                         compatible = "allwinner,sun4i-a10-wdt";
 546                         reg = <0x01c20c90 0x10>;
 547                 };
 548
 549                 sid: eeprom@01c23800 {
 550                         compatible = "allwinner,sun4i-a10-sid";
 551                         reg = <0x01c23800 0x10>;
 552                 };
 553
 554                 rtp: rtp@01c25000 {
 555                         compatible = "allwinner,sun4i-a10-ts";
 556                         reg = <0x01c25000 0x100>;
 557                         interrupts = <29>;
 558                 };
 559
 560                 uart0: serial@01c28000 {
 561                         compatible = "snps,dw-apb-uart";
 562                         reg = <0x01c28000 0x400>;
 563                         interrupts = <1>;
 564                         reg-shift = <2>;
 565                         reg-io-width = <4>;
 566                         clocks = <&apb1_gates 16>;
 567                         status = "disabled";
 568                 };
 569
 570                 uart1: serial@01c28400 {
 571                         compatible = "snps,dw-apb-uart";
 572                         reg = <0x01c28400 0x400>;
 573                         interrupts = <2>;
 574                         reg-shift = <2>;
 575                         reg-io-width = <4>;
 576                         clocks = <&apb1_gates 17>;
 577                         status = "disabled";
 578                 };
 579
 580                 uart2: serial@01c28800 {
 581                         compatible = "snps,dw-apb-uart";
 582                         reg = <0x01c28800 0x400>;
 583                         interrupts = <3>;
 584                         reg-shift = <2>;
 585                         reg-io-width = <4>;
 586                         clocks = <&apb1_gates 18>;
 587                         status = "disabled";
 588                 };
 589
 590                 uart3: serial@01c28c00 {
 591                         compatible = "snps,dw-apb-uart";
 592                         reg = <0x01c28c00 0x400>;
 593                         interrupts = <4>;
 594                         reg-shift = <2>;
 595                         reg-io-width = <4>;
 596                         clocks = <&apb1_gates 19>;
 597                         status = "disabled";
 598                 };
 599
 600                 i2c0: i2c@01c2ac00 {
 601                         #address-cells = <1>;
 602                         #size-cells = <0>;
 603                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 604                         reg = <0x01c2ac00 0x400>;
 605                         interrupts = <7>;
 606                         clocks = <&apb1_gates 0>;
 607                         status = "disabled";
 608                 };
 609
 610                 i2c1: i2c@01c2b000 {
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 614                         reg = <0x01c2b000 0x400>;
 615                         interrupts = <8>;
 616                         clocks = <&apb1_gates 1>;
 617                         status = "disabled";
 618                 };
 619
 620                 i2c2: i2c@01c2b400 {
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 624                         reg = <0x01c2b400 0x400>;
 625                         interrupts = <9>;
 626                         clocks = <&apb1_gates 2>;
 627                         status = "disabled";
 628                 };
 629
 630                 timer@01c60000 {
 631                         compatible = "allwinner,sun5i-a13-hstimer";
 632                         reg = <0x01c60000 0x1000>;
 633                         interrupts = <82>, <83>;
 634                         clocks = <&ahb_gates 28>;
 635                 };
 636         };
 637 };