2 * ARM Ltd. Versatile Express
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
13 model = "V2P-CA15_CA7";
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17 interrupt-parent = <&gic>;
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
38 compatible = "arm,cortex-a15";
40 cci-control-port = <&cci_control1>;
41 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
42 capacity-dmips-mhz = <1024>;
47 compatible = "arm,cortex-a15";
49 cci-control-port = <&cci_control1>;
50 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
51 capacity-dmips-mhz = <1024>;
56 compatible = "arm,cortex-a7";
58 cci-control-port = <&cci_control2>;
59 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
60 capacity-dmips-mhz = <516>;
65 compatible = "arm,cortex-a7";
67 cci-control-port = <&cci_control2>;
68 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
69 capacity-dmips-mhz = <516>;
74 compatible = "arm,cortex-a7";
76 cci-control-port = <&cci_control2>;
77 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
78 capacity-dmips-mhz = <516>;
82 CLUSTER_SLEEP_BIG: cluster-sleep-big {
83 compatible = "arm,idle-state";
85 entry-latency-us = <1000>;
86 exit-latency-us = <700>;
87 min-residency-us = <2000>;
90 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
91 compatible = "arm,idle-state";
93 entry-latency-us = <1000>;
94 exit-latency-us = <500>;
95 min-residency-us = <2500>;
101 device_type = "memory";
102 reg = <0 0x80000000 0 0x40000000>;
106 compatible = "arm,sp805", "arm,primecell";
107 reg = <0 0x2a490000 0 0x1000>;
108 interrupts = <0 98 4>;
109 clocks = <&oscclk6a>, <&oscclk6a>;
110 clock-names = "wdogclk", "apb_pclk";
114 compatible = "arm,hdlcd";
115 reg = <0 0x2b000000 0 0x1000>;
116 interrupts = <0 85 4>;
117 clocks = <&hdlcd_clk>;
118 clock-names = "pxlclk";
121 memory-controller@2b0a0000 {
122 compatible = "arm,pl341", "arm,primecell";
123 reg = <0 0x2b0a0000 0 0x1000>;
124 clocks = <&oscclk6a>;
125 clock-names = "apb_pclk";
128 gic: interrupt-controller@2c001000 {
129 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
130 #interrupt-cells = <3>;
131 #address-cells = <0>;
132 interrupt-controller;
133 reg = <0 0x2c001000 0 0x1000>,
134 <0 0x2c002000 0 0x2000>,
135 <0 0x2c004000 0 0x2000>,
136 <0 0x2c006000 0 0x2000>;
137 interrupts = <1 9 0xf04>;
141 compatible = "arm,cci-400";
142 #address-cells = <1>;
144 reg = <0 0x2c090000 0 0x1000>;
145 ranges = <0x0 0x0 0x2c090000 0x10000>;
147 cci_control1: slave-if@4000 {
148 compatible = "arm,cci-400-ctrl-if";
149 interface-type = "ace";
150 reg = <0x4000 0x1000>;
153 cci_control2: slave-if@5000 {
154 compatible = "arm,cci-400-ctrl-if";
155 interface-type = "ace";
156 reg = <0x5000 0x1000>;
160 compatible = "arm,cci-400-pmu,r0";
161 reg = <0x9000 0x5000>;
162 interrupts = <0 105 4>,
170 memory-controller@7ffd0000 {
171 compatible = "arm,pl354", "arm,primecell";
172 reg = <0 0x7ffd0000 0 0x1000>;
173 interrupts = <0 86 4>,
175 clocks = <&oscclk6a>;
176 clock-names = "apb_pclk";
180 compatible = "arm,pl330", "arm,primecell";
181 reg = <0 0x7ff00000 0 0x1000>;
182 interrupts = <0 92 4>,
187 clocks = <&oscclk6a>;
188 clock-names = "apb_pclk";
192 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
193 reg = <0 0x7fff0000 0 0x1000>;
194 interrupts = <0 95 4>;
198 compatible = "arm,armv7-timer";
199 interrupts = <1 13 0xf08>,
206 compatible = "arm,cortex-a15-pmu";
207 interrupts = <0 68 4>,
209 interrupt-affinity = <&cpu0>,
214 compatible = "arm,cortex-a7-pmu";
215 interrupts = <0 128 4>,
218 interrupt-affinity = <&cpu2>,
224 /* Reference 24MHz clock */
225 compatible = "fixed-clock";
227 clock-frequency = <24000000>;
228 clock-output-names = "oscclk6a";
232 compatible = "arm,vexpress,config-bus";
233 arm,vexpress,config-bridge = <&v2m_sysreg>;
236 /* A15 PLL 0 reference clock */
237 compatible = "arm,vexpress-osc";
238 arm,vexpress-sysreg,func = <1 0>;
239 freq-range = <17000000 50000000>;
241 clock-output-names = "oscclk0";
245 /* A15 PLL 1 reference clock */
246 compatible = "arm,vexpress-osc";
247 arm,vexpress-sysreg,func = <1 1>;
248 freq-range = <17000000 50000000>;
250 clock-output-names = "oscclk1";
254 /* A7 PLL 0 reference clock */
255 compatible = "arm,vexpress-osc";
256 arm,vexpress-sysreg,func = <1 2>;
257 freq-range = <17000000 50000000>;
259 clock-output-names = "oscclk2";
263 /* A7 PLL 1 reference clock */
264 compatible = "arm,vexpress-osc";
265 arm,vexpress-sysreg,func = <1 3>;
266 freq-range = <17000000 50000000>;
268 clock-output-names = "oscclk3";
272 /* External AXI master clock */
273 compatible = "arm,vexpress-osc";
274 arm,vexpress-sysreg,func = <1 4>;
275 freq-range = <20000000 40000000>;
277 clock-output-names = "oscclk4";
281 /* HDLCD PLL reference clock */
282 compatible = "arm,vexpress-osc";
283 arm,vexpress-sysreg,func = <1 5>;
284 freq-range = <23750000 165000000>;
286 clock-output-names = "oscclk5";
290 /* Static memory controller clock */
291 compatible = "arm,vexpress-osc";
292 arm,vexpress-sysreg,func = <1 6>;
293 freq-range = <20000000 40000000>;
295 clock-output-names = "oscclk6";
299 /* SYS PLL reference clock */
300 compatible = "arm,vexpress-osc";
301 arm,vexpress-sysreg,func = <1 7>;
302 freq-range = <17000000 50000000>;
304 clock-output-names = "oscclk7";
308 /* DDR2 PLL reference clock */
309 compatible = "arm,vexpress-osc";
310 arm,vexpress-sysreg,func = <1 8>;
311 freq-range = <20000000 50000000>;
313 clock-output-names = "oscclk8";
317 /* A15 CPU core voltage */
318 compatible = "arm,vexpress-volt";
319 arm,vexpress-sysreg,func = <2 0>;
320 regulator-name = "A15 Vcore";
321 regulator-min-microvolt = <800000>;
322 regulator-max-microvolt = <1050000>;
328 /* A7 CPU core voltage */
329 compatible = "arm,vexpress-volt";
330 arm,vexpress-sysreg,func = <2 1>;
331 regulator-name = "A7 Vcore";
332 regulator-min-microvolt = <800000>;
333 regulator-max-microvolt = <1050000>;
339 /* Total current for the two A15 cores */
340 compatible = "arm,vexpress-amp";
341 arm,vexpress-sysreg,func = <3 0>;
346 /* Total current for the three A7 cores */
347 compatible = "arm,vexpress-amp";
348 arm,vexpress-sysreg,func = <3 1>;
353 /* DCC internal temperature */
354 compatible = "arm,vexpress-temp";
355 arm,vexpress-sysreg,func = <4 0>;
360 /* Total power for the two A15 cores */
361 compatible = "arm,vexpress-power";
362 arm,vexpress-sysreg,func = <12 0>;
367 /* Total power for the three A7 cores */
368 compatible = "arm,vexpress-power";
369 arm,vexpress-sysreg,func = <12 1>;
374 /* Total energy for the two A15 cores */
375 compatible = "arm,vexpress-energy";
376 arm,vexpress-sysreg,func = <13 0>, <13 1>;
381 /* Total energy for the three A7 cores */
382 compatible = "arm,vexpress-energy";
383 arm,vexpress-sysreg,func = <13 2>, <13 3>;
389 compatible = "arm,coresight-etb10", "arm,primecell";
390 reg = <0 0x20010000 0 0x1000>;
392 clocks = <&oscclk6a>;
393 clock-names = "apb_pclk";
395 etb_in_port: endpoint {
397 remote-endpoint = <&replicator_out_port0>;
403 compatible = "arm,coresight-tpiu", "arm,primecell";
404 reg = <0 0x20030000 0 0x1000>;
406 clocks = <&oscclk6a>;
407 clock-names = "apb_pclk";
409 tpiu_in_port: endpoint {
411 remote-endpoint = <&replicator_out_port1>;
417 /* non-configurable replicators don't show up on the
418 * AMBA bus. As such no need to add "arm,primecell".
420 compatible = "arm,coresight-replicator";
423 #address-cells = <1>;
426 /* replicator output ports */
429 replicator_out_port0: endpoint {
430 remote-endpoint = <&etb_in_port>;
436 replicator_out_port1: endpoint {
437 remote-endpoint = <&tpiu_in_port>;
441 /* replicator input port */
444 replicator_in_port0: endpoint {
446 remote-endpoint = <&funnel_out_port0>;
453 compatible = "arm,coresight-funnel", "arm,primecell";
454 reg = <0 0x20040000 0 0x1000>;
456 clocks = <&oscclk6a>;
457 clock-names = "apb_pclk";
459 #address-cells = <1>;
462 /* funnel output port */
465 funnel_out_port0: endpoint {
467 <&replicator_in_port0>;
471 /* funnel input ports */
474 funnel_in_port0: endpoint {
476 remote-endpoint = <&ptm0_out_port>;
482 funnel_in_port1: endpoint {
484 remote-endpoint = <&ptm1_out_port>;
490 funnel_in_port2: endpoint {
492 remote-endpoint = <&etm0_out_port>;
496 /* Input port #3 is for ITM, not supported here */
500 funnel_in_port4: endpoint {
502 remote-endpoint = <&etm1_out_port>;
508 funnel_in_port5: endpoint {
510 remote-endpoint = <&etm2_out_port>;
517 compatible = "arm,coresight-etm3x", "arm,primecell";
518 reg = <0 0x2201c000 0 0x1000>;
521 clocks = <&oscclk6a>;
522 clock-names = "apb_pclk";
524 ptm0_out_port: endpoint {
525 remote-endpoint = <&funnel_in_port0>;
531 compatible = "arm,coresight-etm3x", "arm,primecell";
532 reg = <0 0x2201d000 0 0x1000>;
535 clocks = <&oscclk6a>;
536 clock-names = "apb_pclk";
538 ptm1_out_port: endpoint {
539 remote-endpoint = <&funnel_in_port1>;
545 compatible = "arm,coresight-etm3x", "arm,primecell";
546 reg = <0 0x2203c000 0 0x1000>;
549 clocks = <&oscclk6a>;
550 clock-names = "apb_pclk";
552 etm0_out_port: endpoint {
553 remote-endpoint = <&funnel_in_port2>;
559 compatible = "arm,coresight-etm3x", "arm,primecell";
560 reg = <0 0x2203d000 0 0x1000>;
563 clocks = <&oscclk6a>;
564 clock-names = "apb_pclk";
566 etm1_out_port: endpoint {
567 remote-endpoint = <&funnel_in_port4>;
573 compatible = "arm,coresight-etm3x", "arm,primecell";
574 reg = <0 0x2203e000 0 0x1000>;
577 clocks = <&oscclk6a>;
578 clock-names = "apb_pclk";
580 etm2_out_port: endpoint {
581 remote-endpoint = <&funnel_in_port5>;
587 compatible = "simple-bus";
589 #address-cells = <2>;
591 ranges = <0 0 0 0x08000000 0x04000000>,
592 <1 0 0 0x14000000 0x04000000>,
593 <2 0 0 0x18000000 0x04000000>,
594 <3 0 0 0x1c000000 0x04000000>,
595 <4 0 0 0x0c000000 0x04000000>,
596 <5 0 0 0x10000000 0x04000000>;
598 #interrupt-cells = <1>;
599 interrupt-map-mask = <0 0 63>;
600 interrupt-map = <0 0 0 &gic 0 0 4>,
610 <0 0 10 &gic 0 10 4>,
611 <0 0 11 &gic 0 11 4>,
612 <0 0 12 &gic 0 12 4>,
613 <0 0 13 &gic 0 13 4>,
614 <0 0 14 &gic 0 14 4>,
615 <0 0 15 &gic 0 15 4>,
616 <0 0 16 &gic 0 16 4>,
617 <0 0 17 &gic 0 17 4>,
618 <0 0 18 &gic 0 18 4>,
619 <0 0 19 &gic 0 19 4>,
620 <0 0 20 &gic 0 20 4>,
621 <0 0 21 &gic 0 21 4>,
622 <0 0 22 &gic 0 22 4>,
623 <0 0 23 &gic 0 23 4>,
624 <0 0 24 &gic 0 24 4>,
625 <0 0 25 &gic 0 25 4>,
626 <0 0 26 &gic 0 26 4>,
627 <0 0 27 &gic 0 27 4>,
628 <0 0 28 &gic 0 28 4>,
629 <0 0 29 &gic 0 29 4>,
630 <0 0 30 &gic 0 30 4>,
631 <0 0 31 &gic 0 31 4>,
632 <0 0 32 &gic 0 32 4>,
633 <0 0 33 &gic 0 33 4>,
634 <0 0 34 &gic 0 34 4>,
635 <0 0 35 &gic 0 35 4>,
636 <0 0 36 &gic 0 36 4>,
637 <0 0 37 &gic 0 37 4>,
638 <0 0 38 &gic 0 38 4>,
639 <0 0 39 &gic 0 39 4>,
640 <0 0 40 &gic 0 40 4>,
641 <0 0 41 &gic 0 41 4>,
642 <0 0 42 &gic 0 42 4>;
644 /include/ "vexpress-v2m-rs1.dtsi"
647 site2: hsb@40000000 {
648 compatible = "simple-bus";
649 #address-cells = <1>;
651 ranges = <0 0 0x40000000 0x3fef0000>;
652 #interrupt-cells = <1>;
653 interrupt-map-mask = <0 3>;
654 interrupt-map = <0 0 &gic 0 36 4>,