arch/arm/include/asm/tlbflush.h

   1 /*
   2  *  arch/arm/include/asm/tlbflush.h
   3  *
   4  *  Copyright (C) 1999-2003 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_TLBFLUSH_H
  11 #define _ASMARM_TLBFLUSH_H
  12
  13
  14 #ifndef CONFIG_MMU
  15
  16 #define tlb_flush(tlb)  ((void) tlb)
  17
  18 #else /* CONFIG_MMU */
  19
  20 #include <asm/glue.h>
  21
  22 #define TLB_V3_PAGE     (1 << 0)
  23 #define TLB_V4_U_PAGE   (1 << 1)
  24 #define TLB_V4_D_PAGE   (1 << 2)
  25 #define TLB_V4_I_PAGE   (1 << 3)
  26 #define TLB_V6_U_PAGE   (1 << 4)
  27 #define TLB_V6_D_PAGE   (1 << 5)
  28 #define TLB_V6_I_PAGE   (1 << 6)
  29
  30 #define TLB_V3_FULL     (1 << 8)
  31 #define TLB_V4_U_FULL   (1 << 9)
  32 #define TLB_V4_D_FULL   (1 << 10)
  33 #define TLB_V4_I_FULL   (1 << 11)
  34 #define TLB_V6_U_FULL   (1 << 12)
  35 #define TLB_V6_D_FULL   (1 << 13)
  36 #define TLB_V6_I_FULL   (1 << 14)
  37
  38 #define TLB_V6_U_ASID   (1 << 16)
  39 #define TLB_V6_D_ASID   (1 << 17)
  40 #define TLB_V6_I_ASID   (1 << 18)
  41
  42 #define TLB_BTB         (1 << 28)
  43
  44 /* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
  45 #define TLB_V7_UIS_PAGE (1 << 19)
  46 #define TLB_V7_UIS_FULL (1 << 20)
  47 #define TLB_V7_UIS_ASID (1 << 21)
  48
  49 #define TLB_L2CLEAN_FR  (1 << 29)               /* Feroceon */
  50 #define TLB_DCLEAN      (1 << 30)
  51 #define TLB_WB          (1 << 31)
  52
  53 /*
  54  *      MMU TLB Model
  55  *      =============
  56  *
  57  *      We have the following to choose from:
  58  *        v3    - ARMv3
  59  *        v4    - ARMv4 without write buffer
  60  *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
  61  *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  62  *        fr    - Feroceon (v4wbi with non-outer-cacheable page table walks)
  63  *        fa    - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB))
  64  *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  65  *        v7wbi - identical to v6wbi
  66  */
  67 #undef _TLB
  68 #undef MULTI_TLB
  69
  70 #define v3_tlb_flags    (TLB_V3_FULL | TLB_V3_PAGE)
  71
  72 #ifdef CONFIG_CPU_TLB_V3
  73 # define v3_possible_flags      v3_tlb_flags
  74 # define v3_always_flags        v3_tlb_flags
  75 # ifdef _TLB
  76 #  define MULTI_TLB 1
  77 # else
  78 #  define _TLB v3
  79 # endif
  80 #else
  81 # define v3_possible_flags      0
  82 # define v3_always_flags        (-1UL)
  83 #endif
  84
  85 #define v4_tlb_flags    (TLB_V4_U_FULL | TLB_V4_U_PAGE)
  86
  87 #ifdef CONFIG_CPU_TLB_V4WT
  88 # define v4_possible_flags      v4_tlb_flags
  89 # define v4_always_flags        v4_tlb_flags
  90 # ifdef _TLB
  91 #  define MULTI_TLB 1
  92 # else
  93 #  define _TLB v4
  94 # endif
  95 #else
  96 # define v4_possible_flags      0
  97 # define v4_always_flags        (-1UL)
  98 #endif
  99
 100 #define fa_tlb_flags    (TLB_WB | TLB_BTB | TLB_DCLEAN | \
 101                          TLB_V4_U_FULL | TLB_V4_U_PAGE)
 102
 103 #ifdef CONFIG_CPU_TLB_FA
 104 # define fa_possible_flags      fa_tlb_flags
 105 # define fa_always_flags        fa_tlb_flags
 106 # ifdef _TLB
 107 #  define MULTI_TLB 1
 108 # else
 109 #  define _TLB fa
 110 # endif
 111 #else
 112 # define fa_possible_flags      0
 113 # define fa_always_flags        (-1UL)
 114 #endif
 115
 116 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
 117                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
 118                          TLB_V4_I_PAGE | TLB_V4_D_PAGE)
 119
 120 #ifdef CONFIG_CPU_TLB_V4WBI
 121 # define v4wbi_possible_flags   v4wbi_tlb_flags
 122 # define v4wbi_always_flags     v4wbi_tlb_flags
 123 # ifdef _TLB
 124 #  define MULTI_TLB 1
 125 # else
 126 #  define _TLB v4wbi
 127 # endif
 128 #else
 129 # define v4wbi_possible_flags   0
 130 # define v4wbi_always_flags     (-1UL)
 131 #endif
 132
 133 #define fr_tlb_flags    (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
 134                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
 135                          TLB_V4_I_PAGE | TLB_V4_D_PAGE)
 136
 137 #ifdef CONFIG_CPU_TLB_FEROCEON
 138 # define fr_possible_flags      fr_tlb_flags
 139 # define fr_always_flags        fr_tlb_flags
 140 # ifdef _TLB
 141 #  define MULTI_TLB 1
 142 # else
 143 #  define _TLB v4wbi
 144 # endif
 145 #else
 146 # define fr_possible_flags      0
 147 # define fr_always_flags        (-1UL)
 148 #endif
 149
 150 #define v4wb_tlb_flags  (TLB_WB | TLB_DCLEAN | \
 151                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
 152                          TLB_V4_D_PAGE)
 153
 154 #ifdef CONFIG_CPU_TLB_V4WB
 155 # define v4wb_possible_flags    v4wb_tlb_flags
 156 # define v4wb_always_flags      v4wb_tlb_flags
 157 # ifdef _TLB
 158 #  define MULTI_TLB 1
 159 # else
 160 #  define _TLB v4wb
 161 # endif
 162 #else
 163 # define v4wb_possible_flags    0
 164 # define v4wb_always_flags      (-1UL)
 165 #endif
 166
 167 #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 168                          TLB_V6_I_FULL | TLB_V6_D_FULL | \
 169                          TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
 170                          TLB_V6_I_ASID | TLB_V6_D_ASID)
 171
 172 #ifdef CONFIG_CPU_TLB_V6
 173 # define v6wbi_possible_flags   v6wbi_tlb_flags
 174 # define v6wbi_always_flags     v6wbi_tlb_flags
 175 # ifdef _TLB
 176 #  define MULTI_TLB 1
 177 # else
 178 #  define _TLB v6wbi
 179 # endif
 180 #else
 181 # define v6wbi_possible_flags   0
 182 # define v6wbi_always_flags     (-1UL)
 183 #endif
 184
 185 #ifdef CONFIG_SMP
 186 #define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 187                          TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
 188 #else
 189 #define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 190                          TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
 191 #endif
 192
 193 #ifdef CONFIG_CPU_TLB_V7
 194 # define v7wbi_possible_flags   v7wbi_tlb_flags
 195 # define v7wbi_always_flags     v7wbi_tlb_flags
 196 # ifdef _TLB
 197 #  define MULTI_TLB 1
 198 # else
 199 #  define _TLB v7wbi
 200 # endif
 201 #else
 202 # define v7wbi_possible_flags   0
 203 # define v7wbi_always_flags     (-1UL)
 204 #endif
 205
 206 #ifndef _TLB
 207 #error Unknown TLB model
 208 #endif
 209
 210 #ifndef __ASSEMBLY__
 211
 212 #include <linux/sched.h>
 213
 214 struct cpu_tlb_fns {
 215         void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
 216         void (*flush_kern_range)(unsigned long, unsigned long);
 217         unsigned long tlb_flags;
 218 };
 219
 220 /*
 221  * Select the calling method
 222  */
 223 #ifdef MULTI_TLB
 224
 225 #define __cpu_flush_user_tlb_range      cpu_tlb.flush_user_range
 226 #define __cpu_flush_kern_tlb_range      cpu_tlb.flush_kern_range
 227
 228 #else
 229
 230 #define __cpu_flush_user_tlb_range      __glue(_TLB,_flush_user_tlb_range)
 231 #define __cpu_flush_kern_tlb_range      __glue(_TLB,_flush_kern_tlb_range)
 232
 233 extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
 234 extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
 235
 236 #endif
 237
 238 extern struct cpu_tlb_fns cpu_tlb;
 239
 240 #define __cpu_tlb_flags                 cpu_tlb.tlb_flags
 241
 242 /*
 243  *      TLB Management
 244  *      ==============
 245  *
 246  *      The arch/arm/mm/tlb-*.S files implement these methods.
 247  *
 248  *      The TLB specific code is expected to perform whatever tests it
 249  *      needs to determine if it should invalidate the TLB for each
 250  *      call.  Start addresses are inclusive and end addresses are
 251  *      exclusive; it is safe to round these addresses down.
 252  *
 253  *      flush_tlb_all()
 254  *
 255  *              Invalidate the entire TLB.
 256  *
 257  *      flush_tlb_mm(mm)
 258  *
 259  *              Invalidate all TLB entries in a particular address
 260  *              space.
 261  *              - mm    - mm_struct describing address space
 262  *
 263  *      flush_tlb_range(mm,start,end)
 264  *
 265  *              Invalidate a range of TLB entries in the specified
 266  *              address space.
 267  *              - mm    - mm_struct describing address space
 268  *              - start - start address (may not be aligned)
 269  *              - end   - end address (exclusive, may not be aligned)
 270  *
 271  *      flush_tlb_page(vaddr,vma)
 272  *
 273  *              Invalidate the specified page in the specified address range.
 274  *              - vaddr - virtual address (may not be aligned)
 275  *              - vma   - vma_struct describing address range
 276  *
 277  *      flush_kern_tlb_page(kaddr)
 278  *
 279  *              Invalidate the TLB entry for the specified page.  The address
 280  *              will be in the kernels virtual memory space.  Current uses
 281  *              only require the D-TLB to be invalidated.
 282  *              - kaddr - Kernel virtual memory address
 283  */
 284
 285 /*
 286  * We optimise the code below by:
 287  *  - building a set of TLB flags that might be set in __cpu_tlb_flags
 288  *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
 289  *  - if we're going to need __cpu_tlb_flags, access it once and only once
 290  *
 291  * This allows us to build optimal assembly for the single-CPU type case,
 292  * and as close to optimal given the compiler constrants for multi-CPU
 293  * case.  We could do better for the multi-CPU case if the compiler
 294  * implemented the "%?" method, but this has been discontinued due to too
 295  * many people getting it wrong.
 296  */
 297 #define possible_tlb_flags      (v3_possible_flags | \
 298                                  v4_possible_flags | \
 299                                  v4wbi_possible_flags | \
 300                                  fr_possible_flags | \
 301                                  v4wb_possible_flags | \
 302                                  fa_possible_flags | \
 303                                  v6wbi_possible_flags | \
 304                                  v7wbi_possible_flags)
 305
 306 #define always_tlb_flags        (v3_always_flags & \
 307                                  v4_always_flags & \
 308                                  v4wbi_always_flags & \
 309                                  fr_always_flags & \
 310                                  v4wb_always_flags & \
 311                                  fa_always_flags & \
 312                                  v6wbi_always_flags & \
 313                                  v7wbi_always_flags)
 314
 315 #define tlb_flag(f)     ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
 316
 317 static inline void local_flush_tlb_all(void)
 318 {
 319         const int zero = 0;
 320         const unsigned int __tlb_flag = __cpu_tlb_flags;
 321
 322         if (tlb_flag(TLB_WB))
 323                 dsb();
 324
 325         if (tlb_flag(TLB_V3_FULL))
 326                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
 327         if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
 328                 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
 329         if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
 330                 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
 331         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
 332                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 333         if (tlb_flag(TLB_V7_UIS_FULL))
 334                 asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
 335
 336         if (tlb_flag(TLB_BTB)) {
 337                 /* flush the branch target cache */
 338                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 339                 dsb();
 340                 isb();
 341         }
 342 }
 343
 344 static inline void local_flush_tlb_mm(struct mm_struct *mm)
 345 {
 346         const int zero = 0;
 347         const int asid = ASID(mm);
 348         const unsigned int __tlb_flag = __cpu_tlb_flags;
 349
 350         if (tlb_flag(TLB_WB))
 351                 dsb();
 352
 353         if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
 354                 if (tlb_flag(TLB_V3_FULL))
 355                         asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
 356                 if (tlb_flag(TLB_V4_U_FULL))
 357                         asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
 358                 if (tlb_flag(TLB_V4_D_FULL))
 359                         asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
 360                 if (tlb_flag(TLB_V4_I_FULL))
 361                         asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 362         }
 363         put_cpu();
 364
 365         if (tlb_flag(TLB_V6_U_ASID))
 366                 asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
 367         if (tlb_flag(TLB_V6_D_ASID))
 368                 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
 369         if (tlb_flag(TLB_V6_I_ASID))
 370                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
 371         if (tlb_flag(TLB_V7_UIS_ASID))
 372                 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
 373
 374         if (tlb_flag(TLB_BTB)) {
 375                 /* flush the branch target cache */
 376                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 377                 dsb();
 378         }
 379 }
 380
 381 static inline void
 382 local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 383 {
 384         const int zero = 0;
 385         const unsigned int __tlb_flag = __cpu_tlb_flags;
 386
 387         uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
 388
 389         if (tlb_flag(TLB_WB))
 390                 dsb();
 391
 392         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
 393                 if (tlb_flag(TLB_V3_PAGE))
 394                         asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
 395                 if (tlb_flag(TLB_V4_U_PAGE))
 396                         asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
 397                 if (tlb_flag(TLB_V4_D_PAGE))
 398                         asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
 399                 if (tlb_flag(TLB_V4_I_PAGE))
 400                         asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 401                 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
 402                         asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 403         }
 404
 405         if (tlb_flag(TLB_V6_U_PAGE))
 406                 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
 407         if (tlb_flag(TLB_V6_D_PAGE))
 408                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
 409         if (tlb_flag(TLB_V6_I_PAGE))
 410                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 411         if (tlb_flag(TLB_V7_UIS_PAGE))
 412                 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
 413
 414         if (tlb_flag(TLB_BTB)) {
 415                 /* flush the branch target cache */
 416                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 417                 dsb();
 418         }
 419 }
 420
 421 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
 422 {
 423         const int zero = 0;
 424         const unsigned int __tlb_flag = __cpu_tlb_flags;
 425
 426         kaddr &= PAGE_MASK;
 427
 428         if (tlb_flag(TLB_WB))
 429                 dsb();
 430
 431         if (tlb_flag(TLB_V3_PAGE))
 432                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
 433         if (tlb_flag(TLB_V4_U_PAGE))
 434                 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
 435         if (tlb_flag(TLB_V4_D_PAGE))
 436                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
 437         if (tlb_flag(TLB_V4_I_PAGE))
 438                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 439         if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
 440                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 441
 442         if (tlb_flag(TLB_V6_U_PAGE))
 443                 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
 444         if (tlb_flag(TLB_V6_D_PAGE))
 445                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
 446         if (tlb_flag(TLB_V6_I_PAGE))
 447                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 448         if (tlb_flag(TLB_V7_UIS_PAGE))
 449                 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
 450
 451         if (tlb_flag(TLB_BTB)) {
 452                 /* flush the branch target cache */
 453                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 454                 dsb();
 455                 isb();
 456         }
 457 }
 458
 459 /*
 460  *      flush_pmd_entry
 461  *
 462  *      Flush a PMD entry (word aligned, or double-word aligned) to
 463  *      RAM if the TLB for the CPU we are running on requires this.
 464  *      This is typically used when we are creating PMD entries.
 465  *
 466  *      clean_pmd_entry
 467  *
 468  *      Clean (but don't drain the write buffer) if the CPU requires
 469  *      these operations.  This is typically used when we are removing
 470  *      PMD entries.
 471  */
 472 static inline void flush_pmd_entry(pmd_t *pmd)
 473 {
 474         const unsigned int __tlb_flag = __cpu_tlb_flags;
 475
 476         if (tlb_flag(TLB_DCLEAN))
 477                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
 478                         : : "r" (pmd) : "cc");
 479
 480         if (tlb_flag(TLB_L2CLEAN_FR))
 481                 asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
 482                         : : "r" (pmd) : "cc");
 483
 484         if (tlb_flag(TLB_WB))
 485                 dsb();
 486 }
 487
 488 static inline void clean_pmd_entry(pmd_t *pmd)
 489 {
 490         const unsigned int __tlb_flag = __cpu_tlb_flags;
 491
 492         if (tlb_flag(TLB_DCLEAN))
 493                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
 494                         : : "r" (pmd) : "cc");
 495
 496         if (tlb_flag(TLB_L2CLEAN_FR))
 497                 asm("mcr        p15, 1, %0, c15, c9, 1  @ L2 flush_pmd"
 498                         : : "r" (pmd) : "cc");
 499 }
 500
 501 #undef tlb_flag
 502 #undef always_tlb_flags
 503 #undef possible_tlb_flags
 504
 505 /*
 506  * Convert calls to our calling convention.
 507  */
 508 #define local_flush_tlb_range(vma,start,end)    __cpu_flush_user_tlb_range(start,end,vma)
 509 #define local_flush_tlb_kernel_range(s,e)       __cpu_flush_kern_tlb_range(s,e)
 510
 511 #ifndef CONFIG_SMP
 512 #define flush_tlb_all           local_flush_tlb_all
 513 #define flush_tlb_mm            local_flush_tlb_mm
 514 #define flush_tlb_page          local_flush_tlb_page
 515 #define flush_tlb_kernel_page   local_flush_tlb_kernel_page
 516 #define flush_tlb_range         local_flush_tlb_range
 517 #define flush_tlb_kernel_range  local_flush_tlb_kernel_range
 518 #else
 519 extern void flush_tlb_all(void);
 520 extern void flush_tlb_mm(struct mm_struct *mm);
 521 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
 522 extern void flush_tlb_kernel_page(unsigned long kaddr);
 523 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 524 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 525 #endif
 526
 527 /*
 528  * if PG_dcache_dirty is set for the page, we need to ensure that any
 529  * cache entries for the kernels virtual memory range are written
 530  * back to the page.
 531  */
 532 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
 533
 534 #endif
 535
 536 #endif /* CONFIG_MMU */
 537
 538 #endif