]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/arm/mach-at91/at91rm9200_devices.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:


74f1eaf97801a9d262595ccae018003221c015b9
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-at91 / at91rm9200_devices.c
1 /*
2 * arch/arm/mach-at91/at91rm9200_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
15
16 #include <linux/dma-mapping.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/machine.h>
19 #include <linux/platform_device.h>
20 #include <linux/i2c-gpio.h>
21
22 #include <mach/at91rm9200.h>
23 #include <mach/at91rm9200_mc.h>
24 #include <mach/at91_ramc.h>
25 #include <mach/hardware.h>
26
27 #include "board.h"
28 #include "generic.h"
29 #include "gpio.h"
30
31
32 /* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37 static u64 ohci_dmamask = DMA_BIT_MASK(32);
38 static struct at91_usbh_data usbh_data;
39
40 static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91RM9200_UHP_BASE,
43 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
48 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51 };
52
53 static struct platform_device at91rm9200_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63 };
64
65 void __init at91_add_device_usbh(struct at91_usbh_data *data)
66 {
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable overcurrent notification */
73 for (i = 0; i < data->ports; i++) {
74 if (gpio_is_valid(data->overcurrent_pin[i]))
75 at91_set_gpio_input(data->overcurrent_pin[i], 1);
76 }
77
78 usbh_data = *data;
79 platform_device_register(&at91rm9200_usbh_device);
80 }
81 #else
82 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 #endif
84
85
86 /* --------------------------------------------------------------------
87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */
89
90 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
91 static struct at91_udc_data udc_data;
92
93 static struct resource udc_resources[] = {
94 [0] = {
95 .start = AT91RM9200_BASE_UDP,
96 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
97 .flags = IORESOURCE_MEM,
98 },
99 [1] = {
100 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
101 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
102 .flags = IORESOURCE_IRQ,
103 },
104 };
105
106 static struct platform_device at91rm9200_udc_device = {
107 .name = "at91_udc",
108 .id = -1,
109 .dev = {
110 .platform_data = &udc_data,
111 },
112 .resource = udc_resources,
113 .num_resources = ARRAY_SIZE(udc_resources),
114 };
115
116 void __init at91_add_device_udc(struct at91_udc_data *data)
117 {
118 if (!data)
119 return;
120
121 if (gpio_is_valid(data->vbus_pin)) {
122 at91_set_gpio_input(data->vbus_pin, 0);
123 at91_set_deglitch(data->vbus_pin, 1);
124 }
125 if (gpio_is_valid(data->pullup_pin))
126 at91_set_gpio_output(data->pullup_pin, 0);
127
128 udc_data = *data;
129 platform_device_register(&at91rm9200_udc_device);
130 }
131 #else
132 void __init at91_add_device_udc(struct at91_udc_data *data) {}
133 #endif
134
135
136 /* --------------------------------------------------------------------
137 * Ethernet
138 * -------------------------------------------------------------------- */
139
140 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
141 static u64 eth_dmamask = DMA_BIT_MASK(32);
142 static struct macb_platform_data eth_data;
143
144 static struct resource eth_resources[] = {
145 [0] = {
146 .start = AT91RM9200_BASE_EMAC,
147 .end = AT91RM9200_BASE_EMAC + SZ_16K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
152 .end = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
153 .flags = IORESOURCE_IRQ,
154 },
155 };
156
157 static struct platform_device at91rm9200_eth_device = {
158 .name = "at91_ether",
159 .id = -1,
160 .dev = {
161 .dma_mask = &eth_dmamask,
162 .coherent_dma_mask = DMA_BIT_MASK(32),
163 .platform_data = &eth_data,
164 },
165 .resource = eth_resources,
166 .num_resources = ARRAY_SIZE(eth_resources),
167 };
168
169 void __init at91_add_device_eth(struct macb_platform_data *data)
170 {
171 if (!data)
172 return;
173
174 if (gpio_is_valid(data->phy_irq_pin)) {
175 at91_set_gpio_input(data->phy_irq_pin, 0);
176 at91_set_deglitch(data->phy_irq_pin, 1);
177 }
178
179 /* Pins used for MII and RMII */
180 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
181 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
182 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
183 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
184 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
185 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
186 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
187 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
188 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
189 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
190
191 if (!data->is_rmii) {
192 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
193 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
194 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
195 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
196 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
197 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
198 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
199 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
200 }
201
202 eth_data = *data;
203 platform_device_register(&at91rm9200_eth_device);
204 }
205 #else
206 void __init at91_add_device_eth(struct macb_platform_data *data) {}
207 #endif
208
209
210 /* --------------------------------------------------------------------
211 * Compact Flash / PCMCIA
212 * -------------------------------------------------------------------- */
213
214 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
215 static struct at91_cf_data cf_data;
216
217 #define CF_BASE AT91_CHIPSELECT_4
218
219 static struct resource cf_resources[] = {
220 [0] = {
221 .start = CF_BASE,
222 /* ties up CS4, CS5 and CS6 */
223 .end = CF_BASE + (0x30000000 - 1),
224 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
225 },
226 };
227
228 static struct platform_device at91rm9200_cf_device = {
229 .name = "at91_cf",
230 .id = -1,
231 .dev = {
232 .platform_data = &cf_data,
233 },
234 .resource = cf_resources,
235 .num_resources = ARRAY_SIZE(cf_resources),
236 };
237
238 void __init at91_add_device_cf(struct at91_cf_data *data)
239 {
240 unsigned int csa;
241
242 if (!data)
243 return;
244
245 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
246
247 /* CF takes over CS4, CS5, CS6 */
248 csa = at91_ramc_read(0, AT91_EBI_CSA);
249 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
250
251 /*
252 * Static memory controller timing adjustments.
253 * REVISIT: these timings are in terms of MCK cycles, so
254 * when MCK changes (cpufreq etc) so must these values...
255 */
256 at91_ramc_write(0, AT91_SMC_CSR(4),
257 AT91_SMC_ACSS_STD
258 | AT91_SMC_DBW_16
259 | AT91_SMC_BAT
260 | AT91_SMC_WSEN
261 | AT91_SMC_NWS_(32) /* wait states */
262 | AT91_SMC_RWSETUP_(6) /* setup time */
263 | AT91_SMC_RWHOLD_(4) /* hold time */
264 );
265
266 /* input/irq */
267 if (gpio_is_valid(data->irq_pin)) {
268 at91_set_gpio_input(data->irq_pin, 1);
269 at91_set_deglitch(data->irq_pin, 1);
270 }
271 at91_set_gpio_input(data->det_pin, 1);
272 at91_set_deglitch(data->det_pin, 1);
273
274 /* outputs, initially off */
275 if (gpio_is_valid(data->vcc_pin))
276 at91_set_gpio_output(data->vcc_pin, 0);
277 at91_set_gpio_output(data->rst_pin, 0);
278
279 /* force poweron defaults for these pins ... */
280 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
281 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
282 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
283 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
284
285 /* nWAIT is _not_ a default setting */
286 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
287
288 cf_data = *data;
289 platform_device_register(&at91rm9200_cf_device);
290 }
291 #else
292 void __init at91_add_device_cf(struct at91_cf_data *data) {}
293 #endif
294
295
296 /* --------------------------------------------------------------------
297 * MMC / SD
298 * -------------------------------------------------------------------- */
299
300 #if IS_ENABLED(CONFIG_MMC_ATMELMCI)
301 static u64 mmc_dmamask = DMA_BIT_MASK(32);
302 static struct mci_platform_data mmc_data;
303
304 static struct resource mmc_resources[] = {
305 [0] = {
306 .start = AT91RM9200_BASE_MCI,
307 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
308 .flags = IORESOURCE_MEM,
309 },
310 [1] = {
311 .start = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
312 .end = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
313 .flags = IORESOURCE_IRQ,
314 },
315 };
316
317 static struct platform_device at91rm9200_mmc_device = {
318 .name = "atmel_mci",
319 .id = -1,
320 .dev = {
321 .dma_mask = &mmc_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 .platform_data = &mmc_data,
324 },
325 .resource = mmc_resources,
326 .num_resources = ARRAY_SIZE(mmc_resources),
327 };
328
329 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
330 {
331 unsigned int i;
332 unsigned int slot_count = 0;
333
334 if (!data)
335 return;
336
337 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
338
339 if (!data->slot[i].bus_width)
340 continue;
341
342 /* input/irq */
343 if (gpio_is_valid(data->slot[i].detect_pin)) {
344 at91_set_gpio_input(data->slot[i].detect_pin, 1);
345 at91_set_deglitch(data->slot[i].detect_pin, 1);
346 }
347 if (gpio_is_valid(data->slot[i].wp_pin))
348 at91_set_gpio_input(data->slot[i].wp_pin, 1);
349
350 switch (i) {
351 case 0: /* slot A */
352 /* CMD */
353 at91_set_A_periph(AT91_PIN_PA28, 1);
354 /* DAT0, maybe DAT1..DAT3 */
355 at91_set_A_periph(AT91_PIN_PA29, 1);
356 if (data->slot[i].bus_width == 4) {
357 at91_set_B_periph(AT91_PIN_PB3, 1);
358 at91_set_B_periph(AT91_PIN_PB4, 1);
359 at91_set_B_periph(AT91_PIN_PB5, 1);
360 }
361 slot_count++;
362 break;
363 case 1: /* slot B */
364 /* CMD */
365 at91_set_B_periph(AT91_PIN_PA8, 1);
366 /* DAT0, maybe DAT1..DAT3 */
367 at91_set_B_periph(AT91_PIN_PA9, 1);
368 if (data->slot[i].bus_width == 4) {
369 at91_set_B_periph(AT91_PIN_PA10, 1);
370 at91_set_B_periph(AT91_PIN_PA11, 1);
371 at91_set_B_periph(AT91_PIN_PA12, 1);
372 }
373 slot_count++;
374 break;
375 default:
376 printk(KERN_ERR
377 "AT91: SD/MMC slot %d not available\n", i);
378 break;
379 }
380 if (slot_count) {
381 /* CLK */
382 at91_set_A_periph(AT91_PIN_PA27, 0);
383
384 mmc_data = *data;
385 platform_device_register(&at91rm9200_mmc_device);
386 }
387 }
388
389 }
390 #else
391 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
392 #endif
393
394
395 /* --------------------------------------------------------------------
396 * NAND / SmartMedia
397 * -------------------------------------------------------------------- */
398
399 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
400 static struct atmel_nand_data nand_data;
401
402 #define NAND_BASE AT91_CHIPSELECT_3
403
404 static struct resource nand_resources[] = {
405 {
406 .start = NAND_BASE,
407 .end = NAND_BASE + SZ_256M - 1,
408 .flags = IORESOURCE_MEM,
409 }
410 };
411
412 static struct platform_device at91rm9200_nand_device = {
413 .name = "atmel_nand",
414 .id = -1,
415 .dev = {
416 .platform_data = &nand_data,
417 },
418 .resource = nand_resources,
419 .num_resources = ARRAY_SIZE(nand_resources),
420 };
421
422 void __init at91_add_device_nand(struct atmel_nand_data *data)
423 {
424 unsigned int csa;
425
426 if (!data)
427 return;
428
429 /* enable the address range of CS3 */
430 csa = at91_ramc_read(0, AT91_EBI_CSA);
431 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
432
433 /* set the bus interface characteristics */
434 at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
435 | AT91_SMC_NWS_(5)
436 | AT91_SMC_TDF_(1)
437 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
438 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
439 );
440
441 /* enable pin */
442 if (gpio_is_valid(data->enable_pin))
443 at91_set_gpio_output(data->enable_pin, 1);
444
445 /* ready/busy pin */
446 if (gpio_is_valid(data->rdy_pin))
447 at91_set_gpio_input(data->rdy_pin, 1);
448
449 /* card detect pin */
450 if (gpio_is_valid(data->det_pin))
451 at91_set_gpio_input(data->det_pin, 1);
452
453 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
454 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
455
456 nand_data = *data;
457 platform_device_register(&at91rm9200_nand_device);
458 }
459 #else
460 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
461 #endif
462
463
464 /* --------------------------------------------------------------------
465 * TWI (i2c)
466 * -------------------------------------------------------------------- */
467
468 /*
469 * Prefer the GPIO code since the TWI controller isn't robust
470 * (gets overruns and underruns under load) and can only issue
471 * repeated STARTs in one scenario (the driver doesn't yet handle them).
472 */
473 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
474
475 static struct i2c_gpio_platform_data pdata = {
476 .sda_pin = AT91_PIN_PA25,
477 .sda_is_open_drain = 1,
478 .scl_pin = AT91_PIN_PA26,
479 .scl_is_open_drain = 1,
480 .udelay = 2, /* ~100 kHz */
481 };
482
483 static struct platform_device at91rm9200_twi_device = {
484 .name = "i2c-gpio",
485 .id = 0,
486 .dev.platform_data = &pdata,
487 };
488
489 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
490 {
491 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */
492 at91_set_multi_drive(AT91_PIN_PA25, 1);
493
494 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */
495 at91_set_multi_drive(AT91_PIN_PA26, 1);
496
497 i2c_register_board_info(0, devices, nr_devices);
498 platform_device_register(&at91rm9200_twi_device);
499 }
500
501 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
502
503 static struct resource twi_resources[] = {
504 [0] = {
505 .start = AT91RM9200_BASE_TWI,
506 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
507 .flags = IORESOURCE_MEM,
508 },
509 [1] = {
510 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
511 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
512 .flags = IORESOURCE_IRQ,
513 },
514 };
515
516 static struct platform_device at91rm9200_twi_device = {
517 .name = "i2c-at91rm9200",
518 .id = 0,
519 .resource = twi_resources,
520 .num_resources = ARRAY_SIZE(twi_resources),
521 };
522
523 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
524 {
525 /* pins used for TWI interface */
526 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
527 at91_set_multi_drive(AT91_PIN_PA25, 1);
528
529 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
530 at91_set_multi_drive(AT91_PIN_PA26, 1);
531
532 i2c_register_board_info(0, devices, nr_devices);
533 platform_device_register(&at91rm9200_twi_device);
534 }
535 #else
536 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
537 #endif
538
539
540 /* --------------------------------------------------------------------
541 * SPI
542 * -------------------------------------------------------------------- */
543
544 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
545 static u64 spi_dmamask = DMA_BIT_MASK(32);
546
547 static struct resource spi_resources[] = {
548 [0] = {
549 .start = AT91RM9200_BASE_SPI,
550 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
555 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
556 .flags = IORESOURCE_IRQ,
557 },
558 };
559
560 static struct platform_device at91rm9200_spi_device = {
561 .name = "atmel_spi",
562 .id = 0,
563 .dev = {
564 .dma_mask = &spi_dmamask,
565 .coherent_dma_mask = DMA_BIT_MASK(32),
566 },
567 .resource = spi_resources,
568 .num_resources = ARRAY_SIZE(spi_resources),
569 };
570
571 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
572
573 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
574 {
575 int i;
576 unsigned long cs_pin;
577
578 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
579 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
580 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
581
582 /* Enable SPI chip-selects */
583 for (i = 0; i < nr_devices; i++) {
584 if (devices[i].controller_data)
585 cs_pin = (unsigned long) devices[i].controller_data;
586 else
587 cs_pin = spi_standard_cs[devices[i].chip_select];
588
589 if (devices[i].chip_select == 0) /* for CS0 errata */
590 at91_set_A_periph(cs_pin, 0);
591 else
592 at91_set_gpio_output(cs_pin, 1);
593
594
595 /* pass chip-select pin to driver */
596 devices[i].controller_data = (void *) cs_pin;
597 }
598
599 spi_register_board_info(devices, nr_devices);
600 platform_device_register(&at91rm9200_spi_device);
601 }
602 #else
603 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
604 #endif
605
606
607 /* --------------------------------------------------------------------
608 * Timer/Counter blocks
609 * -------------------------------------------------------------------- */
610
611 #ifdef CONFIG_ATMEL_TCLIB
612
613 static struct resource tcb0_resources[] = {
614 [0] = {
615 .start = AT91RM9200_BASE_TCB0,
616 .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
617 .flags = IORESOURCE_MEM,
618 },
619 [1] = {
620 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
621 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
622 .flags = IORESOURCE_IRQ,
623 },
624 [2] = {
625 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
626 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
627 .flags = IORESOURCE_IRQ,
628 },
629 [3] = {
630 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
631 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
632 .flags = IORESOURCE_IRQ,
633 },
634 };
635
636 static struct platform_device at91rm9200_tcb0_device = {
637 .name = "atmel_tcb",
638 .id = 0,
639 .resource = tcb0_resources,
640 .num_resources = ARRAY_SIZE(tcb0_resources),
641 };
642
643 static struct resource tcb1_resources[] = {
644 [0] = {
645 .start = AT91RM9200_BASE_TCB1,
646 .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
651 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
652 .flags = IORESOURCE_IRQ,
653 },
654 [2] = {
655 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
656 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
657 .flags = IORESOURCE_IRQ,
658 },
659 [3] = {
660 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
661 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
662 .flags = IORESOURCE_IRQ,
663 },
664 };
665
666 static struct platform_device at91rm9200_tcb1_device = {
667 .name = "atmel_tcb",
668 .id = 1,
669 .resource = tcb1_resources,
670 .num_resources = ARRAY_SIZE(tcb1_resources),
671 };
672
673 static void __init at91_add_device_tc(void)
674 {
675 platform_device_register(&at91rm9200_tcb0_device);
676 platform_device_register(&at91rm9200_tcb1_device);
677 }
678 #else
679 static void __init at91_add_device_tc(void) { }
680 #endif
681
682
683 /* --------------------------------------------------------------------
684 * RTC
685 * -------------------------------------------------------------------- */
686
687 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
688 static struct resource rtc_resources[] = {
689 [0] = {
690 .start = AT91RM9200_BASE_RTC,
691 .end = AT91RM9200_BASE_RTC + SZ_256 - 1,
692 .flags = IORESOURCE_MEM,
693 },
694 [1] = {
695 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
696 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
697 .flags = IORESOURCE_IRQ,
698 },
699 };
700
701 static struct platform_device at91rm9200_rtc_device = {
702 .name = "at91_rtc",
703 .id = -1,
704 .resource = rtc_resources,
705 .num_resources = ARRAY_SIZE(rtc_resources),
706 };
707
708 static void __init at91_add_device_rtc(void)
709 {
710 platform_device_register(&at91rm9200_rtc_device);
711 }
712 #else
713 static void __init at91_add_device_rtc(void) {}
714 #endif
715
716
717 /* --------------------------------------------------------------------
718 * Watchdog
719 * -------------------------------------------------------------------- */
720
721 #if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
722 static struct platform_device at91rm9200_wdt_device = {
723 .name = "at91_wdt",
724 .id = -1,
725 .num_resources = 0,
726 };
727
728 static void __init at91_add_device_watchdog(void)
729 {
730 platform_device_register(&at91rm9200_wdt_device);
731 }
732 #else
733 static void __init at91_add_device_watchdog(void) {}
734 #endif
735
736
737 /* --------------------------------------------------------------------
738 * SSC -- Synchronous Serial Controller
739 * -------------------------------------------------------------------- */
740
741 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
742 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
743
744 static struct resource ssc0_resources[] = {
745 [0] = {
746 .start = AT91RM9200_BASE_SSC0,
747 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
748 .flags = IORESOURCE_MEM,
749 },
750 [1] = {
751 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
752 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
753 .flags = IORESOURCE_IRQ,
754 },
755 };
756
757 static struct platform_device at91rm9200_ssc0_device = {
758 .name = "at91rm9200_ssc",
759 .id = 0,
760 .dev = {
761 .dma_mask = &ssc0_dmamask,
762 .coherent_dma_mask = DMA_BIT_MASK(32),
763 },
764 .resource = ssc0_resources,
765 .num_resources = ARRAY_SIZE(ssc0_resources),
766 };
767
768 static inline void configure_ssc0_pins(unsigned pins)
769 {
770 if (pins & ATMEL_SSC_TF)
771 at91_set_A_periph(AT91_PIN_PB0, 1);
772 if (pins & ATMEL_SSC_TK)
773 at91_set_A_periph(AT91_PIN_PB1, 1);
774 if (pins & ATMEL_SSC_TD)
775 at91_set_A_periph(AT91_PIN_PB2, 1);
776 if (pins & ATMEL_SSC_RD)
777 at91_set_A_periph(AT91_PIN_PB3, 1);
778 if (pins & ATMEL_SSC_RK)
779 at91_set_A_periph(AT91_PIN_PB4, 1);
780 if (pins & ATMEL_SSC_RF)
781 at91_set_A_periph(AT91_PIN_PB5, 1);
782 }
783
784 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
785
786 static struct resource ssc1_resources[] = {
787 [0] = {
788 .start = AT91RM9200_BASE_SSC1,
789 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
790 .flags = IORESOURCE_MEM,
791 },
792 [1] = {
793 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
794 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
795 .flags = IORESOURCE_IRQ,
796 },
797 };
798
799 static struct platform_device at91rm9200_ssc1_device = {
800 .name = "at91rm9200_ssc",
801 .id = 1,
802 .dev = {
803 .dma_mask = &ssc1_dmamask,
804 .coherent_dma_mask = DMA_BIT_MASK(32),
805 },
806 .resource = ssc1_resources,
807 .num_resources = ARRAY_SIZE(ssc1_resources),
808 };
809
810 static inline void configure_ssc1_pins(unsigned pins)
811 {
812 if (pins & ATMEL_SSC_TF)
813 at91_set_A_periph(AT91_PIN_PB6, 1);
814 if (pins & ATMEL_SSC_TK)
815 at91_set_A_periph(AT91_PIN_PB7, 1);
816 if (pins & ATMEL_SSC_TD)
817 at91_set_A_periph(AT91_PIN_PB8, 1);
818 if (pins & ATMEL_SSC_RD)
819 at91_set_A_periph(AT91_PIN_PB9, 1);
820 if (pins & ATMEL_SSC_RK)
821 at91_set_A_periph(AT91_PIN_PB10, 1);
822 if (pins & ATMEL_SSC_RF)
823 at91_set_A_periph(AT91_PIN_PB11, 1);
824 }
825
826 static u64 ssc2_dmamask = DMA_BIT_MASK(32);
827
828 static struct resource ssc2_resources[] = {
829 [0] = {
830 .start = AT91RM9200_BASE_SSC2,
831 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
832 .flags = IORESOURCE_MEM,
833 },
834 [1] = {
835 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
836 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
837 .flags = IORESOURCE_IRQ,
838 },
839 };
840
841 static struct platform_device at91rm9200_ssc2_device = {
842 .name = "at91rm9200_ssc",
843 .id = 2,
844 .dev = {
845 .dma_mask = &ssc2_dmamask,
846 .coherent_dma_mask = DMA_BIT_MASK(32),
847 },
848 .resource = ssc2_resources,
849 .num_resources = ARRAY_SIZE(ssc2_resources),
850 };
851
852 static inline void configure_ssc2_pins(unsigned pins)
853 {
854 if (pins & ATMEL_SSC_TF)
855 at91_set_A_periph(AT91_PIN_PB12, 1);
856 if (pins & ATMEL_SSC_TK)
857 at91_set_A_periph(AT91_PIN_PB13, 1);
858 if (pins & ATMEL_SSC_TD)
859 at91_set_A_periph(AT91_PIN_PB14, 1);
860 if (pins & ATMEL_SSC_RD)
861 at91_set_A_periph(AT91_PIN_PB15, 1);
862 if (pins & ATMEL_SSC_RK)
863 at91_set_A_periph(AT91_PIN_PB16, 1);
864 if (pins & ATMEL_SSC_RF)
865 at91_set_A_periph(AT91_PIN_PB17, 1);
866 }
867
868 /*
869 * SSC controllers are accessed through library code, instead of any
870 * kind of all-singing/all-dancing driver. For example one could be
871 * used by a particular I2S audio codec's driver, while another one
872 * on the same system might be used by a custom data capture driver.
873 */
874 void __init at91_add_device_ssc(unsigned id, unsigned pins)
875 {
876 struct platform_device *pdev;
877
878 /*
879 * NOTE: caller is responsible for passing information matching
880 * "pins" to whatever will be using each particular controller.
881 */
882 switch (id) {
883 case AT91RM9200_ID_SSC0:
884 pdev = &at91rm9200_ssc0_device;
885 configure_ssc0_pins(pins);
886 break;
887 case AT91RM9200_ID_SSC1:
888 pdev = &at91rm9200_ssc1_device;
889 configure_ssc1_pins(pins);
890 break;
891 case AT91RM9200_ID_SSC2:
892 pdev = &at91rm9200_ssc2_device;
893 configure_ssc2_pins(pins);
894 break;
895 default:
896 return;
897 }
898
899 platform_device_register(pdev);
900 }
901
902 #else
903 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
904 #endif
905
906
907 /* --------------------------------------------------------------------
908 * UART
909 * -------------------------------------------------------------------- */
910
911 #if defined(CONFIG_SERIAL_ATMEL)
912 static struct resource dbgu_resources[] = {
913 [0] = {
914 .start = AT91RM9200_BASE_DBGU,
915 .end = AT91RM9200_BASE_DBGU + SZ_512 - 1,
916 .flags = IORESOURCE_MEM,
917 },
918 [1] = {
919 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
920 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
921 .flags = IORESOURCE_IRQ,
922 },
923 };
924
925 static struct atmel_uart_data dbgu_data = {
926 .use_dma_tx = 0,
927 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
928 };
929
930 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
931
932 static struct platform_device at91rm9200_dbgu_device = {
933 .name = "atmel_usart",
934 .id = 0,
935 .dev = {
936 .dma_mask = &dbgu_dmamask,
937 .coherent_dma_mask = DMA_BIT_MASK(32),
938 .platform_data = &dbgu_data,
939 },
940 .resource = dbgu_resources,
941 .num_resources = ARRAY_SIZE(dbgu_resources),
942 };
943
944 static inline void configure_dbgu_pins(void)
945 {
946 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
947 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
948 }
949
950 static struct resource uart0_resources[] = {
951 [0] = {
952 .start = AT91RM9200_BASE_US0,
953 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
954 .flags = IORESOURCE_MEM,
955 },
956 [1] = {
957 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
958 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
959 .flags = IORESOURCE_IRQ,
960 },
961 };
962
963 static struct atmel_uart_data uart0_data = {
964 .use_dma_tx = 1,
965 .use_dma_rx = 1,
966 };
967
968 static struct gpiod_lookup_table uart0_gpios_table = {
969 .dev_id = "atmel_usart",
970 .table = {
971 GPIO_LOOKUP("pioA", 21, "rts", GPIO_ACTIVE_LOW),
972 { },
973 },
974 };
975
976 static u64 uart0_dmamask = DMA_BIT_MASK(32);
977
978 static struct platform_device at91rm9200_uart0_device = {
979 .name = "atmel_usart",
980 .id = 1,
981 .dev = {
982 .dma_mask = &uart0_dmamask,
983 .coherent_dma_mask = DMA_BIT_MASK(32),
984 .platform_data = &uart0_data,
985 },
986 .resource = uart0_resources,
987 .num_resources = ARRAY_SIZE(uart0_resources),
988 };
989
990 static inline void configure_usart0_pins(unsigned pins)
991 {
992 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
993 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
994
995 if (pins & ATMEL_UART_CTS)
996 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
997
998 if (pins & ATMEL_UART_RTS) {
999 /*
1000 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
1001 * We need to drive the pin manually. The serial driver will driver
1002 * this to high when initializing.
1003 */
1004 gpiod_add_lookup_table(&uart0_gpios_table);
1005 }
1006 }
1007
1008 static struct resource uart1_resources[] = {
1009 [0] = {
1010 .start = AT91RM9200_BASE_US1,
1011 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
1012 .flags = IORESOURCE_MEM,
1013 },
1014 [1] = {
1015 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1016 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1017 .flags = IORESOURCE_IRQ,
1018 },
1019 };
1020
1021 static struct atmel_uart_data uart1_data = {
1022 .use_dma_tx = 1,
1023 .use_dma_rx = 1,
1024 };
1025
1026 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1027
1028 static struct platform_device at91rm9200_uart1_device = {
1029 .name = "atmel_usart",
1030 .id = 2,
1031 .dev = {
1032 .dma_mask = &uart1_dmamask,
1033 .coherent_dma_mask = DMA_BIT_MASK(32),
1034 .platform_data = &uart1_data,
1035 },
1036 .resource = uart1_resources,
1037 .num_resources = ARRAY_SIZE(uart1_resources),
1038 };
1039
1040 static inline void configure_usart1_pins(unsigned pins)
1041 {
1042 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
1043 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
1044
1045 if (pins & ATMEL_UART_RI)
1046 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
1047 if (pins & ATMEL_UART_DTR)
1048 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
1049 if (pins & ATMEL_UART_DCD)
1050 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
1051 if (pins & ATMEL_UART_CTS)
1052 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
1053 if (pins & ATMEL_UART_DSR)
1054 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
1055 if (pins & ATMEL_UART_RTS)
1056 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
1057 }
1058
1059 static struct resource uart2_resources[] = {
1060 [0] = {
1061 .start = AT91RM9200_BASE_US2,
1062 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
1063 .flags = IORESOURCE_MEM,
1064 },
1065 [1] = {
1066 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1067 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1068 .flags = IORESOURCE_IRQ,
1069 },
1070 };
1071
1072 static struct atmel_uart_data uart2_data = {
1073 .use_dma_tx = 1,
1074 .use_dma_rx = 1,
1075 };
1076
1077 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1078
1079 static struct platform_device at91rm9200_uart2_device = {
1080 .name = "atmel_usart",
1081 .id = 3,
1082 .dev = {
1083 .dma_mask = &uart2_dmamask,
1084 .coherent_dma_mask = DMA_BIT_MASK(32),
1085 .platform_data = &uart2_data,
1086 },
1087 .resource = uart2_resources,
1088 .num_resources = ARRAY_SIZE(uart2_resources),
1089 };
1090
1091 static inline void configure_usart2_pins(unsigned pins)
1092 {
1093 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
1094 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
1095
1096 if (pins & ATMEL_UART_CTS)
1097 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
1098 if (pins & ATMEL_UART_RTS)
1099 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
1100 }
1101
1102 static struct resource uart3_resources[] = {
1103 [0] = {
1104 .start = AT91RM9200_BASE_US3,
1105 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
1106 .flags = IORESOURCE_MEM,
1107 },
1108 [1] = {
1109 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1110 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1111 .flags = IORESOURCE_IRQ,
1112 },
1113 };
1114
1115 static struct atmel_uart_data uart3_data = {
1116 .use_dma_tx = 1,
1117 .use_dma_rx = 1,
1118 };
1119
1120 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1121
1122 static struct platform_device at91rm9200_uart3_device = {
1123 .name = "atmel_usart",
1124 .id = 4,
1125 .dev = {
1126 .dma_mask = &uart3_dmamask,
1127 .coherent_dma_mask = DMA_BIT_MASK(32),
1128 .platform_data = &uart3_data,
1129 },
1130 .resource = uart3_resources,
1131 .num_resources = ARRAY_SIZE(uart3_resources),
1132 };
1133
1134 static inline void configure_usart3_pins(unsigned pins)
1135 {
1136 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
1137 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
1138
1139 if (pins & ATMEL_UART_CTS)
1140 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
1141 if (pins & ATMEL_UART_RTS)
1142 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
1143 }
1144
1145 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1146
1147 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1148 {
1149 struct platform_device *pdev;
1150 struct atmel_uart_data *pdata;
1151
1152 switch (id) {
1153 case 0: /* DBGU */
1154 pdev = &at91rm9200_dbgu_device;
1155 configure_dbgu_pins();
1156 break;
1157 case AT91RM9200_ID_US0:
1158 pdev = &at91rm9200_uart0_device;
1159 configure_usart0_pins(pins);
1160 break;
1161 case AT91RM9200_ID_US1:
1162 pdev = &at91rm9200_uart1_device;
1163 configure_usart1_pins(pins);
1164 break;
1165 case AT91RM9200_ID_US2:
1166 pdev = &at91rm9200_uart2_device;
1167 configure_usart2_pins(pins);
1168 break;
1169 case AT91RM9200_ID_US3:
1170 pdev = &at91rm9200_uart3_device;
1171 configure_usart3_pins(pins);
1172 break;
1173 default:
1174 return;
1175 }
1176 pdata = pdev->dev.platform_data;
1177 pdata->num = portnr; /* update to mapped ID */
1178
1179 if (portnr < ATMEL_MAX_UART)
1180 at91_uarts[portnr] = pdev;
1181 }
1182
1183 void __init at91_add_device_serial(void)
1184 {
1185 int i;
1186
1187 for (i = 0; i < ATMEL_MAX_UART; i++) {
1188 if (at91_uarts[i])
1189 platform_device_register(at91_uarts[i]);
1190 }
1191 }
1192 #else
1193 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1194 void __init at91_add_device_serial(void) {}
1195 #endif
1196
1197
1198 /* -------------------------------------------------------------------- */
1199
1200 /*
1201 * These devices are always present and don't need any board-specific
1202 * setup.
1203 */
1204 static int __init at91_add_standard_devices(void)
1205 {
1206 at91_add_device_rtc();
1207 at91_add_device_watchdog();
1208 at91_add_device_tc();
1209 return 0;
1210 }
1211
1212 arch_initcall(at91_add_standard_devices);
Ubuntu Artful kernel mirror