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1 /*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14 #include <linux/clk/at91_pmc.h>
15
16 #include <asm/proc-fns.h>
17 #include <asm/irq.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/system_misc.h>
21 #include <mach/at91sam9263.h>
22 #include <mach/hardware.h>
23
24 #include "at91_aic.h"
25 #include "at91_rstc.h"
26 #include "soc.h"
27 #include "generic.h"
28 #include "clock.h"
29 #include "sam9_smc.h"
30 #include "pm.h"
31
32 /* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35
36 /*
37 * The peripheral clocks.
38 */
39 static struct clk pioA_clk = {
40 .name = "pioA_clk",
41 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
42 .type = CLK_TYPE_PERIPHERAL,
43 };
44 static struct clk pioB_clk = {
45 .name = "pioB_clk",
46 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
47 .type = CLK_TYPE_PERIPHERAL,
48 };
49 static struct clk pioCDE_clk = {
50 .name = "pioCDE_clk",
51 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
52 .type = CLK_TYPE_PERIPHERAL,
53 };
54 static struct clk usart0_clk = {
55 .name = "usart0_clk",
56 .pmc_mask = 1 << AT91SAM9263_ID_US0,
57 .type = CLK_TYPE_PERIPHERAL,
58 };
59 static struct clk usart1_clk = {
60 .name = "usart1_clk",
61 .pmc_mask = 1 << AT91SAM9263_ID_US1,
62 .type = CLK_TYPE_PERIPHERAL,
63 };
64 static struct clk usart2_clk = {
65 .name = "usart2_clk",
66 .pmc_mask = 1 << AT91SAM9263_ID_US2,
67 .type = CLK_TYPE_PERIPHERAL,
68 };
69 static struct clk mmc0_clk = {
70 .name = "mci0_clk",
71 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
72 .type = CLK_TYPE_PERIPHERAL,
73 };
74 static struct clk mmc1_clk = {
75 .name = "mci1_clk",
76 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
77 .type = CLK_TYPE_PERIPHERAL,
78 };
79 static struct clk can_clk = {
80 .name = "can_clk",
81 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
82 .type = CLK_TYPE_PERIPHERAL,
83 };
84 static struct clk twi_clk = {
85 .name = "twi_clk",
86 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
87 .type = CLK_TYPE_PERIPHERAL,
88 };
89 static struct clk spi0_clk = {
90 .name = "spi0_clk",
91 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
93 };
94 static struct clk spi1_clk = {
95 .name = "spi1_clk",
96 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
98 };
99 static struct clk ssc0_clk = {
100 .name = "ssc0_clk",
101 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
102 .type = CLK_TYPE_PERIPHERAL,
103 };
104 static struct clk ssc1_clk = {
105 .name = "ssc1_clk",
106 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
107 .type = CLK_TYPE_PERIPHERAL,
108 };
109 static struct clk ac97_clk = {
110 .name = "ac97_clk",
111 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
112 .type = CLK_TYPE_PERIPHERAL,
113 };
114 static struct clk tcb_clk = {
115 .name = "tcb_clk",
116 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
117 .type = CLK_TYPE_PERIPHERAL,
118 };
119 static struct clk pwm_clk = {
120 .name = "pwm_clk",
121 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
122 .type = CLK_TYPE_PERIPHERAL,
123 };
124 static struct clk macb_clk = {
125 .name = "pclk",
126 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
127 .type = CLK_TYPE_PERIPHERAL,
128 };
129 static struct clk dma_clk = {
130 .name = "dma_clk",
131 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
132 .type = CLK_TYPE_PERIPHERAL,
133 };
134 static struct clk twodge_clk = {
135 .name = "2dge_clk",
136 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
137 .type = CLK_TYPE_PERIPHERAL,
138 };
139 static struct clk udc_clk = {
140 .name = "udc_clk",
141 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
142 .type = CLK_TYPE_PERIPHERAL,
143 };
144 static struct clk isi_clk = {
145 .name = "isi_clk",
146 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
147 .type = CLK_TYPE_PERIPHERAL,
148 };
149 static struct clk lcdc_clk = {
150 .name = "lcdc_clk",
151 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
152 .type = CLK_TYPE_PERIPHERAL,
153 };
154 static struct clk ohci_clk = {
155 .name = "ohci_clk",
156 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
157 .type = CLK_TYPE_PERIPHERAL,
158 };
159
160 static struct clk *periph_clocks[] __initdata = {
161 &pioA_clk,
162 &pioB_clk,
163 &pioCDE_clk,
164 &usart0_clk,
165 &usart1_clk,
166 &usart2_clk,
167 &mmc0_clk,
168 &mmc1_clk,
169 &can_clk,
170 &twi_clk,
171 &spi0_clk,
172 &spi1_clk,
173 &ssc0_clk,
174 &ssc1_clk,
175 &ac97_clk,
176 &tcb_clk,
177 &pwm_clk,
178 &macb_clk,
179 &twodge_clk,
180 &udc_clk,
181 &isi_clk,
182 &lcdc_clk,
183 &dma_clk,
184 &ohci_clk,
185 // irq0 .. irq1
186 };
187
188 static struct clk_lookup periph_clocks_lookups[] = {
189 /* One additional fake clock for macb_hclk */
190 CLKDEV_CON_ID("hclk", &macb_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
195 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
196 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
197 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
198 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
199 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
200 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
201 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
202 /* fake hclk clock */
203 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
204 CLKDEV_CON_ID("pioA", &pioA_clk),
205 CLKDEV_CON_ID("pioB", &pioB_clk),
206 CLKDEV_CON_ID("pioC", &pioCDE_clk),
207 CLKDEV_CON_ID("pioD", &pioCDE_clk),
208 CLKDEV_CON_ID("pioE", &pioCDE_clk),
209 /* more usart lookup table for DT entries */
210 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
211 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
212 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
213 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
214 /* more tc lookup table for DT entries */
215 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
216 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
219 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
220 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
226 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
227 };
228
229 static struct clk_lookup usart_clocks_lookups[] = {
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
234 };
235
236 /*
237 * The four programmable clocks.
238 * You must configure pin multiplexing to bring these signals out.
239 */
240 static struct clk pck0 = {
241 .name = "pck0",
242 .pmc_mask = AT91_PMC_PCK0,
243 .type = CLK_TYPE_PROGRAMMABLE,
244 .id = 0,
245 };
246 static struct clk pck1 = {
247 .name = "pck1",
248 .pmc_mask = AT91_PMC_PCK1,
249 .type = CLK_TYPE_PROGRAMMABLE,
250 .id = 1,
251 };
252 static struct clk pck2 = {
253 .name = "pck2",
254 .pmc_mask = AT91_PMC_PCK2,
255 .type = CLK_TYPE_PROGRAMMABLE,
256 .id = 2,
257 };
258 static struct clk pck3 = {
259 .name = "pck3",
260 .pmc_mask = AT91_PMC_PCK3,
261 .type = CLK_TYPE_PROGRAMMABLE,
262 .id = 3,
263 };
264
265 static void __init at91sam9263_register_clocks(void)
266 {
267 int i;
268
269 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
270 clk_register(periph_clocks[i]);
271
272 clkdev_add_table(periph_clocks_lookups,
273 ARRAY_SIZE(periph_clocks_lookups));
274 clkdev_add_table(usart_clocks_lookups,
275 ARRAY_SIZE(usart_clocks_lookups));
276
277 clk_register(&pck0);
278 clk_register(&pck1);
279 clk_register(&pck2);
280 clk_register(&pck3);
281 }
282
283 /* --------------------------------------------------------------------
284 * GPIO
285 * -------------------------------------------------------------------- */
286
287 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
288 {
289 .id = AT91SAM9263_ID_PIOA,
290 .regbase = AT91SAM9263_BASE_PIOA,
291 }, {
292 .id = AT91SAM9263_ID_PIOB,
293 .regbase = AT91SAM9263_BASE_PIOB,
294 }, {
295 .id = AT91SAM9263_ID_PIOCDE,
296 .regbase = AT91SAM9263_BASE_PIOC,
297 }, {
298 .id = AT91SAM9263_ID_PIOCDE,
299 .regbase = AT91SAM9263_BASE_PIOD,
300 }, {
301 .id = AT91SAM9263_ID_PIOCDE,
302 .regbase = AT91SAM9263_BASE_PIOE,
303 }
304 };
305
306 /* --------------------------------------------------------------------
307 * AT91SAM9263 processor initialization
308 * -------------------------------------------------------------------- */
309
310 static void __init at91sam9263_map_io(void)
311 {
312 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
313 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
314 }
315
316 static void __init at91sam9263_ioremap_registers(void)
317 {
318 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
319 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
320 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
321 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
322 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
323 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
324 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
325 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
326 at91_pm_set_standby(at91sam9_sdram_standby);
327 }
328
329 static void __init at91sam9263_initialize(void)
330 {
331 arm_pm_idle = at91sam9_idle;
332 arm_pm_restart = at91sam9_alt_restart;
333
334 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
335 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
336
337 /* Register GPIO subsystem */
338 at91_gpio_init(at91sam9263_gpio, 5);
339 }
340
341 /* --------------------------------------------------------------------
342 * Interrupt initialization
343 * -------------------------------------------------------------------- */
344
345 /*
346 * The default interrupt priority levels (0 = lowest, 7 = highest).
347 */
348 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
349 7, /* Advanced Interrupt Controller (FIQ) */
350 7, /* System Peripherals */
351 1, /* Parallel IO Controller A */
352 1, /* Parallel IO Controller B */
353 1, /* Parallel IO Controller C, D and E */
354 0,
355 0,
356 5, /* USART 0 */
357 5, /* USART 1 */
358 5, /* USART 2 */
359 0, /* Multimedia Card Interface 0 */
360 0, /* Multimedia Card Interface 1 */
361 3, /* CAN */
362 6, /* Two-Wire Interface */
363 5, /* Serial Peripheral Interface 0 */
364 5, /* Serial Peripheral Interface 1 */
365 4, /* Serial Synchronous Controller 0 */
366 4, /* Serial Synchronous Controller 1 */
367 5, /* AC97 Controller */
368 0, /* Timer Counter 0, 1 and 2 */
369 0, /* Pulse Width Modulation Controller */
370 3, /* Ethernet */
371 0,
372 0, /* 2D Graphic Engine */
373 2, /* USB Device Port */
374 0, /* Image Sensor Interface */
375 3, /* LDC Controller */
376 0, /* DMA Controller */
377 0,
378 2, /* USB Host port */
379 0, /* Advanced Interrupt Controller (IRQ0) */
380 0, /* Advanced Interrupt Controller (IRQ1) */
381 };
382
383 AT91_SOC_START(at91sam9263)
384 .map_io = at91sam9263_map_io,
385 .default_irq_priority = at91sam9263_default_irq_priority,
386 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
387 .ioremap_registers = at91sam9263_ioremap_registers,
388 .register_clocks = at91sam9263_register_clocks,
389 .init = at91sam9263_initialize,
390 AT91_SOC_END