arch/arm/mach-at91/at91sam9rl.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9rl.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *  Copyright (C) 2007 Atmel Corporation
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive for
   9  * more details.
  10  */
  11
  12 #include <linux/module.h>
  13
  14 #include <asm/proc-fns.h>
  15 #include <asm/irq.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <asm/system_misc.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91_dbgu.h>
  21 #include <mach/at91sam9rl.h>
  22 #include <mach/at91_pmc.h>
  23 #include <mach/hardware.h>
  24
  25 #include "at91_aic.h"
  26 #include "at91_rstc.h"
  27 #include "soc.h"
  28 #include "generic.h"
  29 #include "clock.h"
  30 #include "sam9_smc.h"
  31 #include "pm.h"
  32
  33 /* --------------------------------------------------------------------
  34  *  Clocks
  35  * -------------------------------------------------------------------- */
  36
  37 /*
  38  * The peripheral clocks.
  39  */
  40 static struct clk pioA_clk = {
  41         .name           = "pioA_clk",
  42         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
  43         .type           = CLK_TYPE_PERIPHERAL,
  44 };
  45 static struct clk pioB_clk = {
  46         .name           = "pioB_clk",
  47         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
  48         .type           = CLK_TYPE_PERIPHERAL,
  49 };
  50 static struct clk pioC_clk = {
  51         .name           = "pioC_clk",
  52         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk pioD_clk = {
  56         .name           = "pioD_clk",
  57         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60 static struct clk usart0_clk = {
  61         .name           = "usart0_clk",
  62         .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
  63         .type           = CLK_TYPE_PERIPHERAL,
  64 };
  65 static struct clk usart1_clk = {
  66         .name           = "usart1_clk",
  67         .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk usart2_clk = {
  71         .name           = "usart2_clk",
  72         .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk usart3_clk = {
  76         .name           = "usart3_clk",
  77         .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk mmc_clk = {
  81         .name           = "mci_clk",
  82         .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk twi0_clk = {
  86         .name           = "twi0_clk",
  87         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk twi1_clk = {
  91         .name           = "twi1_clk",
  92         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk spi_clk = {
  96         .name           = "spi_clk",
  97         .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk ssc0_clk = {
 101         .name           = "ssc0_clk",
 102         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk ssc1_clk = {
 106         .name           = "ssc1_clk",
 107         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk tc0_clk = {
 111         .name           = "tc0_clk",
 112         .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk tc1_clk = {
 116         .name           = "tc1_clk",
 117         .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk tc2_clk = {
 121         .name           = "tc2_clk",
 122         .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk pwm_clk = {
 126         .name           = "pwm_clk",
 127         .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk tsc_clk = {
 131         .name           = "tsc_clk",
 132         .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135 static struct clk dma_clk = {
 136         .name           = "dma_clk",
 137         .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
 138         .type           = CLK_TYPE_PERIPHERAL,
 139 };
 140 static struct clk udphs_clk = {
 141         .name           = "udphs_clk",
 142         .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
 143         .type           = CLK_TYPE_PERIPHERAL,
 144 };
 145 static struct clk lcdc_clk = {
 146         .name           = "lcdc_clk",
 147         .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
 148         .type           = CLK_TYPE_PERIPHERAL,
 149 };
 150 static struct clk ac97_clk = {
 151         .name           = "ac97_clk",
 152         .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155
 156 static struct clk *periph_clocks[] __initdata = {
 157         &pioA_clk,
 158         &pioB_clk,
 159         &pioC_clk,
 160         &pioD_clk,
 161         &usart0_clk,
 162         &usart1_clk,
 163         &usart2_clk,
 164         &usart3_clk,
 165         &mmc_clk,
 166         &twi0_clk,
 167         &twi1_clk,
 168         &spi_clk,
 169         &ssc0_clk,
 170         &ssc1_clk,
 171         &tc0_clk,
 172         &tc1_clk,
 173         &tc2_clk,
 174         &pwm_clk,
 175         &tsc_clk,
 176         &dma_clk,
 177         &udphs_clk,
 178         &lcdc_clk,
 179         &ac97_clk,
 180         // irq0
 181 };
 182
 183 static struct clk_lookup periph_clocks_lookups[] = {
 184         CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
 185         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 186         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 187         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 188         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 189         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 190         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 191         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 192         CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
 193         CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
 194         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
 195         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
 196         CLKDEV_CON_ID("pioA", &pioA_clk),
 197         CLKDEV_CON_ID("pioB", &pioB_clk),
 198         CLKDEV_CON_ID("pioC", &pioC_clk),
 199         CLKDEV_CON_ID("pioD", &pioD_clk),
 200 };
 201
 202 static struct clk_lookup usart_clocks_lookups[] = {
 203         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 204         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 205         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 206         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 207         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 208 };
 209
 210 /*
 211  * The two programmable clocks.
 212  * You must configure pin multiplexing to bring these signals out.
 213  */
 214 static struct clk pck0 = {
 215         .name           = "pck0",
 216         .pmc_mask       = AT91_PMC_PCK0,
 217         .type           = CLK_TYPE_PROGRAMMABLE,
 218         .id             = 0,
 219 };
 220 static struct clk pck1 = {
 221         .name           = "pck1",
 222         .pmc_mask       = AT91_PMC_PCK1,
 223         .type           = CLK_TYPE_PROGRAMMABLE,
 224         .id             = 1,
 225 };
 226
 227 static void __init at91sam9rl_register_clocks(void)
 228 {
 229         int i;
 230
 231         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 232                 clk_register(periph_clocks[i]);
 233
 234         clkdev_add_table(periph_clocks_lookups,
 235                          ARRAY_SIZE(periph_clocks_lookups));
 236         clkdev_add_table(usart_clocks_lookups,
 237                          ARRAY_SIZE(usart_clocks_lookups));
 238
 239         clk_register(&pck0);
 240         clk_register(&pck1);
 241 }
 242
 243 /* --------------------------------------------------------------------
 244  *  GPIO
 245  * -------------------------------------------------------------------- */
 246
 247 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
 248         {
 249                 .id             = AT91SAM9RL_ID_PIOA,
 250                 .regbase        = AT91SAM9RL_BASE_PIOA,
 251         }, {
 252                 .id             = AT91SAM9RL_ID_PIOB,
 253                 .regbase        = AT91SAM9RL_BASE_PIOB,
 254         }, {
 255                 .id             = AT91SAM9RL_ID_PIOC,
 256                 .regbase        = AT91SAM9RL_BASE_PIOC,
 257         }, {
 258                 .id             = AT91SAM9RL_ID_PIOD,
 259                 .regbase        = AT91SAM9RL_BASE_PIOD,
 260         }
 261 };
 262
 263 /* --------------------------------------------------------------------
 264  *  AT91SAM9RL processor initialization
 265  * -------------------------------------------------------------------- */
 266
 267 static void __init at91sam9rl_map_io(void)
 268 {
 269         unsigned long sram_size;
 270
 271         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 272                 case AT91_CIDR_SRAMSIZ_32K:
 273                         sram_size = 2 * SZ_16K;
 274                         break;
 275                 case AT91_CIDR_SRAMSIZ_16K:
 276                 default:
 277                         sram_size = SZ_16K;
 278         }
 279
 280         /* Map SRAM */
 281         at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
 282 }
 283
 284 static void __init at91sam9rl_ioremap_registers(void)
 285 {
 286         at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
 287         at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
 288         at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
 289         at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
 290         at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
 291         at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
 292         at91_pm_set_standby(at91sam9_sdram_standby);
 293 }
 294
 295 static void __init at91sam9rl_initialize(void)
 296 {
 297         arm_pm_idle = at91sam9_idle;
 298         arm_pm_restart = at91sam9_alt_restart;
 299
 300         at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
 301         at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
 302
 303         /* Register GPIO subsystem */
 304         at91_gpio_init(at91sam9rl_gpio, 4);
 305 }
 306
 307 /* --------------------------------------------------------------------
 308  *  Interrupt initialization
 309  * -------------------------------------------------------------------- */
 310
 311 /*
 312  * The default interrupt priority levels (0 = lowest, 7 = highest).
 313  */
 314 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 315         7,      /* Advanced Interrupt Controller */
 316         7,      /* System Peripherals */
 317         1,      /* Parallel IO Controller A */
 318         1,      /* Parallel IO Controller B */
 319         1,      /* Parallel IO Controller C */
 320         1,      /* Parallel IO Controller D */
 321         5,      /* USART 0 */
 322         5,      /* USART 1 */
 323         5,      /* USART 2 */
 324         5,      /* USART 3 */
 325         0,      /* Multimedia Card Interface */
 326         6,      /* Two-Wire Interface 0 */
 327         6,      /* Two-Wire Interface 1 */
 328         5,      /* Serial Peripheral Interface */
 329         4,      /* Serial Synchronous Controller 0 */
 330         4,      /* Serial Synchronous Controller 1 */
 331         0,      /* Timer Counter 0 */
 332         0,      /* Timer Counter 1 */
 333         0,      /* Timer Counter 2 */
 334         0,
 335         0,      /* Touch Screen Controller */
 336         0,      /* DMA Controller */
 337         2,      /* USB Device High speed port */
 338         2,      /* LCD Controller */
 339         6,      /* AC97 Controller */
 340         0,
 341         0,
 342         0,
 343         0,
 344         0,
 345         0,
 346         0,      /* Advanced Interrupt Controller */
 347 };
 348
 349 AT91_SOC_START(at91sam9rl)
 350         .map_io = at91sam9rl_map_io,
 351         .default_irq_priority = at91sam9rl_default_irq_priority,
 352         .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
 353         .ioremap_registers = at91sam9rl_ioremap_registers,
 354         .register_clocks = at91sam9rl_register_clocks,
 355         .init = at91sam9rl_initialize,
 356 AT91_SOC_END