arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11 #include <linux/pm.h>
  12 #include <linux/of_address.h>
  13 #include <linux/pinctrl/machine.h>
  14 #include <linux/clk/at91_pmc.h>
  15
  16 #include <asm/system_misc.h>
  17 #include <asm/mach/map.h>
  18
  19 #include <mach/hardware.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91_dbgu.h>
  22
  23 #include "at91_shdwc.h"
  24 #include "soc.h"
  25 #include "generic.h"
  26 #include "pm.h"
  27
  28 struct at91_init_soc __initdata at91_boot_soc;
  29
  30 struct at91_socinfo at91_soc_initdata;
  31 EXPORT_SYMBOL(at91_soc_initdata);
  32
  33 void __init at91rm9200_set_type(int type)
  34 {
  35         if (type == ARCH_REVISON_9200_PQFP)
  36                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  37         else
  38                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  39
  40         pr_info("AT91: filled in soc subtype: %s\n",
  41                 at91_get_soc_subtype(&at91_soc_initdata));
  42 }
  43
  44 void __init at91_init_irq_default(void)
  45 {
  46         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  47 }
  48
  49 void __init at91_init_interrupts(unsigned int *priority)
  50 {
  51         /* Initialize the AIC interrupt controller */
  52         if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
  53                 at91_aic_init(priority, at91_boot_soc.extern_irq);
  54
  55         /* Enable GPIO interrupts */
  56         at91_gpio_irq_setup();
  57 }
  58
  59 void __iomem *at91_ramc_base[2];
  60 EXPORT_SYMBOL_GPL(at91_ramc_base);
  61
  62 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  63 {
  64         if (id < 0 || id > 1) {
  65                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  66                 BUG();
  67         }
  68         at91_ramc_base[id] = ioremap(addr, size);
  69         if (!at91_ramc_base[id])
  70                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
  71 }
  72
  73 static struct map_desc sram_desc[2] __initdata;
  74
  75 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  76 {
  77         struct map_desc *desc = &sram_desc[bank];
  78
  79         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  80         if (bank > 0)
  81                 desc->virtual -= sram_desc[bank - 1].length;
  82
  83         desc->pfn = __phys_to_pfn(base);
  84         desc->length = length;
  85         desc->type = MT_MEMORY_RWX_NONCACHED;
  86
  87         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  88                 base, length, desc->virtual);
  89
  90         iotable_init(desc, 1);
  91 }
  92
  93 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  94         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  95         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  96         .length         = SZ_16K,
  97         .type           = MT_DEVICE,
  98 };
  99
 100 static void __init soc_detect(u32 dbgu_base)
 101 {
 102         u32 cidr, socid;
 103
 104         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 105         socid = cidr & ~AT91_CIDR_VERSION;
 106
 107         switch (socid) {
 108         case ARCH_ID_AT91RM9200:
 109                 at91_soc_initdata.type = AT91_SOC_RM9200;
 110                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
 111                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 112                 at91_boot_soc = at91rm9200_soc;
 113                 break;
 114
 115         case ARCH_ID_AT91SAM9260:
 116                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 117                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 118                 at91_boot_soc = at91sam9260_soc;
 119                 break;
 120
 121         case ARCH_ID_AT91SAM9261:
 122                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 123                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 124                 at91_boot_soc = at91sam9261_soc;
 125                 break;
 126
 127         case ARCH_ID_AT91SAM9263:
 128                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 129                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 130                 at91_boot_soc = at91sam9263_soc;
 131                 break;
 132
 133         case ARCH_ID_AT91SAM9G20:
 134                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 135                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 136                 at91_boot_soc = at91sam9260_soc;
 137                 break;
 138
 139         case ARCH_ID_AT91SAM9G45:
 140                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 141                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 142                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 143                 at91_boot_soc = at91sam9g45_soc;
 144                 break;
 145
 146         case ARCH_ID_AT91SAM9RL64:
 147                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 148                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 149                 at91_boot_soc = at91sam9rl_soc;
 150                 break;
 151
 152         case ARCH_ID_AT91SAM9X5:
 153                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 154                 at91_boot_soc = at91sam9x5_soc;
 155                 break;
 156
 157         case ARCH_ID_AT91SAM9N12:
 158                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 159                 at91_boot_soc = at91sam9n12_soc;
 160                 break;
 161
 162         case ARCH_ID_SAMA5D3:
 163                 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 164                 at91_boot_soc = sama5d3_soc;
 165                 break;
 166         }
 167
 168         /* at91sam9g10 */
 169         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 170                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 171                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 172                 at91_boot_soc = at91sam9261_soc;
 173         }
 174         /* at91sam9xe */
 175         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 176                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 177                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 178                 at91_boot_soc = at91sam9260_soc;
 179         }
 180
 181         if (!at91_soc_is_detected())
 182                 return;
 183
 184         at91_soc_initdata.cidr = cidr;
 185
 186         /* sub version of soc */
 187         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 188
 189         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 190                 switch (at91_soc_initdata.exid) {
 191                 case ARCH_EXID_AT91SAM9M10:
 192                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 193                         break;
 194                 case ARCH_EXID_AT91SAM9G46:
 195                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 196                         break;
 197                 case ARCH_EXID_AT91SAM9M11:
 198                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 199                         break;
 200                 }
 201         }
 202
 203         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 204                 switch (at91_soc_initdata.exid) {
 205                 case ARCH_EXID_AT91SAM9G15:
 206                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 207                         break;
 208                 case ARCH_EXID_AT91SAM9G35:
 209                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 210                         break;
 211                 case ARCH_EXID_AT91SAM9X35:
 212                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 213                         break;
 214                 case ARCH_EXID_AT91SAM9G25:
 215                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 216                         break;
 217                 case ARCH_EXID_AT91SAM9X25:
 218                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 219                         break;
 220                 }
 221         }
 222
 223         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 224                 switch (at91_soc_initdata.exid) {
 225                 case ARCH_EXID_SAMA5D31:
 226                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 227                         break;
 228                 case ARCH_EXID_SAMA5D33:
 229                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 230                         break;
 231                 case ARCH_EXID_SAMA5D34:
 232                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 233                         break;
 234                 case ARCH_EXID_SAMA5D35:
 235                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 236                         break;
 237                 case ARCH_EXID_SAMA5D36:
 238                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 239                         break;
 240                 }
 241         }
 242 }
 243
 244 static const char *soc_name[] = {
 245         [AT91_SOC_RM9200]       = "at91rm9200",
 246         [AT91_SOC_SAM9260]      = "at91sam9260",
 247         [AT91_SOC_SAM9261]      = "at91sam9261",
 248         [AT91_SOC_SAM9263]      = "at91sam9263",
 249         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 250         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 251         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 252         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 253         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 254         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 255         [AT91_SOC_SAMA5D3]      = "sama5d3",
 256         [AT91_SOC_UNKNOWN]      = "Unknown",
 257 };
 258
 259 const char *at91_get_soc_type(struct at91_socinfo *c)
 260 {
 261         return soc_name[c->type];
 262 }
 263 EXPORT_SYMBOL(at91_get_soc_type);
 264
 265 static const char *soc_subtype_name[] = {
 266         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 267         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 268         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 269         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 270         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 271         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 272         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 273         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 274         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 275         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 276         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 277         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 278         [AT91_SOC_SAMA5D31]     = "sama5d31",
 279         [AT91_SOC_SAMA5D33]     = "sama5d33",
 280         [AT91_SOC_SAMA5D34]     = "sama5d34",
 281         [AT91_SOC_SAMA5D35]     = "sama5d35",
 282         [AT91_SOC_SAMA5D36]     = "sama5d36",
 283         [AT91_SOC_SUBTYPE_NONE] = "None",
 284         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 285 };
 286
 287 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 288 {
 289         return soc_subtype_name[c->subtype];
 290 }
 291 EXPORT_SYMBOL(at91_get_soc_subtype);
 292
 293 void __init at91_map_io(void)
 294 {
 295         /* Map peripherals */
 296         iotable_init(&at91_io_desc, 1);
 297
 298         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 299         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 300
 301         soc_detect(AT91_BASE_DBGU0);
 302         if (!at91_soc_is_detected())
 303                 soc_detect(AT91_BASE_DBGU1);
 304
 305         if (!at91_soc_is_detected())
 306                 panic("AT91: Impossible to detect the SOC type");
 307
 308         pr_info("AT91: Detected soc type: %s\n",
 309                 at91_get_soc_type(&at91_soc_initdata));
 310         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 311                 pr_info("AT91: Detected soc subtype: %s\n",
 312                         at91_get_soc_subtype(&at91_soc_initdata));
 313
 314         if (!at91_soc_is_enabled())
 315                 panic("AT91: Soc not enabled");
 316
 317         if (at91_boot_soc.map_io)
 318                 at91_boot_soc.map_io();
 319 }
 320
 321 void __iomem *at91_shdwc_base = NULL;
 322
 323 static void at91sam9_poweroff(void)
 324 {
 325         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 326 }
 327
 328 void __init at91_ioremap_shdwc(u32 base_addr)
 329 {
 330         at91_shdwc_base = ioremap(base_addr, 16);
 331         if (!at91_shdwc_base)
 332                 panic("Impossible to ioremap at91_shdwc_base\n");
 333         pm_power_off = at91sam9_poweroff;
 334 }
 335
 336 void __iomem *at91_rstc_base;
 337
 338 void __init at91_ioremap_rstc(u32 base_addr)
 339 {
 340         at91_rstc_base = ioremap(base_addr, 16);
 341         if (!at91_rstc_base)
 342                 panic("Impossible to ioremap at91_rstc_base\n");
 343 }
 344
 345 void __iomem *at91_matrix_base;
 346 EXPORT_SYMBOL_GPL(at91_matrix_base);
 347
 348 void __init at91_ioremap_matrix(u32 base_addr)
 349 {
 350         at91_matrix_base = ioremap(base_addr, 512);
 351         if (!at91_matrix_base)
 352                 panic("Impossible to ioremap at91_matrix_base\n");
 353 }
 354
 355 #if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
 356 static struct of_device_id rstc_ids[] = {
 357         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
 358         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
 359         { /*sentinel*/ }
 360 };
 361
 362 static void at91_dt_rstc(void)
 363 {
 364         struct device_node *np;
 365         const struct of_device_id *of_id;
 366
 367         np = of_find_matching_node(NULL, rstc_ids);
 368         if (!np)
 369                 panic("unable to find compatible rstc node in dtb\n");
 370
 371         at91_rstc_base = of_iomap(np, 0);
 372         if (!at91_rstc_base)
 373                 panic("unable to map rstc cpu registers\n");
 374
 375         of_id = of_match_node(rstc_ids, np);
 376         if (!of_id)
 377                 panic("AT91: rtsc no restart function available\n");
 378
 379         arm_pm_restart = of_id->data;
 380
 381         of_node_put(np);
 382 }
 383
 384 static struct of_device_id ramc_ids[] = {
 385         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 386         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 387         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 388         { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
 389         { /*sentinel*/ }
 390 };
 391
 392 static void at91_dt_ramc(void)
 393 {
 394         struct device_node *np;
 395         const struct of_device_id *of_id;
 396
 397         np = of_find_matching_node(NULL, ramc_ids);
 398         if (!np)
 399                 panic("unable to find compatible ram controller node in dtb\n");
 400
 401         at91_ramc_base[0] = of_iomap(np, 0);
 402         if (!at91_ramc_base[0])
 403                 panic("unable to map ramc[0] cpu registers\n");
 404         /* the controller may have 2 banks */
 405         at91_ramc_base[1] = of_iomap(np, 1);
 406
 407         of_id = of_match_node(ramc_ids, np);
 408         if (!of_id)
 409                 pr_warn("AT91: ramc no standby function available\n");
 410         else
 411                 at91_pm_set_standby(of_id->data);
 412
 413         of_node_put(np);
 414 }
 415
 416 static struct of_device_id shdwc_ids[] = {
 417         { .compatible = "atmel,at91sam9260-shdwc", },
 418         { .compatible = "atmel,at91sam9rl-shdwc", },
 419         { .compatible = "atmel,at91sam9x5-shdwc", },
 420         { /*sentinel*/ }
 421 };
 422
 423 static const char *shdwc_wakeup_modes[] = {
 424         [AT91_SHDW_WKMODE0_NONE]        = "none",
 425         [AT91_SHDW_WKMODE0_HIGH]        = "high",
 426         [AT91_SHDW_WKMODE0_LOW]         = "low",
 427         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
 428 };
 429
 430 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
 431 {
 432         const char *pm;
 433         int err, i;
 434
 435         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
 436         if (err < 0)
 437                 return AT91_SHDW_WKMODE0_ANYLEVEL;
 438
 439         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
 440                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
 441                         return i;
 442
 443         return -ENODEV;
 444 }
 445
 446 static void at91_dt_shdwc(void)
 447 {
 448         struct device_node *np;
 449         int wakeup_mode;
 450         u32 reg;
 451         u32 mode = 0;
 452
 453         np = of_find_matching_node(NULL, shdwc_ids);
 454         if (!np) {
 455                 pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
 456                 return;
 457         }
 458
 459         at91_shdwc_base = of_iomap(np, 0);
 460         if (!at91_shdwc_base)
 461                 panic("AT91: unable to map shdwc cpu registers\n");
 462
 463         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
 464         if (wakeup_mode < 0) {
 465                 pr_warn("AT91: shdwc unknown wakeup mode\n");
 466                 goto end;
 467         }
 468
 469         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
 470                 if (reg > AT91_SHDW_CPTWK0_MAX) {
 471                         pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
 472                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
 473                         reg = AT91_SHDW_CPTWK0_MAX;
 474                 }
 475                 mode |= AT91_SHDW_CPTWK0_(reg);
 476         }
 477
 478         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
 479                         mode |= AT91_SHDW_RTCWKEN;
 480
 481         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
 482                         mode |= AT91_SHDW_RTTWKEN;
 483
 484         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
 485
 486 end:
 487         pm_power_off = at91sam9_poweroff;
 488
 489         of_node_put(np);
 490 }
 491
 492 void __init at91rm9200_dt_initialize(void)
 493 {
 494         at91_dt_ramc();
 495
 496         /* Init clock subsystem */
 497         at91_dt_clock_init();
 498
 499         /* Register the processor-specific clocks */
 500         if (at91_boot_soc.register_clocks)
 501                 at91_boot_soc.register_clocks();
 502
 503         at91_boot_soc.init();
 504 }
 505
 506 void __init at91_dt_initialize(void)
 507 {
 508         at91_dt_rstc();
 509         at91_dt_ramc();
 510         at91_dt_shdwc();
 511
 512         /* Init clock subsystem */
 513         at91_dt_clock_init();
 514
 515         /* Register the processor-specific clocks */
 516         if (at91_boot_soc.register_clocks)
 517                 at91_boot_soc.register_clocks();
 518
 519         if (at91_boot_soc.init)
 520                 at91_boot_soc.init();
 521 }
 522 #endif
 523
 524 void __init at91_initialize(unsigned long main_clock)
 525 {
 526         at91_boot_soc.ioremap_registers();
 527
 528         /* Init clock subsystem */
 529         at91_clock_init(main_clock);
 530
 531         /* Register the processor-specific clocks */
 532         at91_boot_soc.register_clocks();
 533
 534         at91_boot_soc.init();
 535
 536         pinctrl_provide_dummies();
 537 }