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Merge branch 'samsung/soc' into next/soc2
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-exynos / common.c
1 /*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/io.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22
23 #include <asm/proc-fns.h>
24 #include <asm/exception.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/hardware/gic.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h>
29 #include <asm/cacheflush.h>
30
31 #include <mach/regs-irq.h>
32 #include <mach/regs-pmu.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/pmu.h>
35
36 #include <plat/cpu.h>
37 #include <plat/clock.h>
38 #include <plat/devs.h>
39 #include <plat/pm.h>
40 #include <plat/sdhci.h>
41 #include <plat/gpio-cfg.h>
42 #include <plat/adc-core.h>
43 #include <plat/fb-core.h>
44 #include <plat/fimc-core.h>
45 #include <plat/iic-core.h>
46 #include <plat/tv-core.h>
47 #include <plat/regs-serial.h>
48
49 #include "common.h"
50 #define L2_AUX_VAL 0x7C470001
51 #define L2_AUX_MASK 0xC200ffff
52
53 static const char name_exynos4210[] = "EXYNOS4210";
54 static const char name_exynos4212[] = "EXYNOS4212";
55 static const char name_exynos4412[] = "EXYNOS4412";
56 static const char name_exynos5250[] = "EXYNOS5250";
57
58 static void exynos4_map_io(void);
59 static void exynos5_map_io(void);
60 static void exynos4_init_clocks(int xtal);
61 static void exynos5_init_clocks(int xtal);
62 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
63 static int exynos_init(void);
64
65 static struct cpu_table cpu_ids[] __initdata = {
66 {
67 .idcode = EXYNOS4210_CPU_ID,
68 .idmask = EXYNOS4_CPU_MASK,
69 .map_io = exynos4_map_io,
70 .init_clocks = exynos4_init_clocks,
71 .init_uarts = exynos_init_uarts,
72 .init = exynos_init,
73 .name = name_exynos4210,
74 }, {
75 .idcode = EXYNOS4212_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos_init_uarts,
80 .init = exynos_init,
81 .name = name_exynos4212,
82 }, {
83 .idcode = EXYNOS4412_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
87 .init_uarts = exynos_init_uarts,
88 .init = exynos_init,
89 .name = name_exynos4412,
90 }, {
91 .idcode = EXYNOS5250_SOC_ID,
92 .idmask = EXYNOS5_SOC_MASK,
93 .map_io = exynos5_map_io,
94 .init_clocks = exynos5_init_clocks,
95 .init_uarts = exynos_init_uarts,
96 .init = exynos_init,
97 .name = name_exynos5250,
98 },
99 };
100
101 /* Initial IO mappings */
102
103 static struct map_desc exynos_iodesc[] __initdata = {
104 {
105 .virtual = (unsigned long)S5P_VA_CHIPID,
106 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 },
110 };
111
112 static struct map_desc exynos4_iodesc[] __initdata = {
113 {
114 .virtual = (unsigned long)S3C_VA_SYS,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
116 .length = SZ_64K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S3C_VA_TIMER,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
121 .length = SZ_16K,
122 .type = MT_DEVICE,
123 }, {
124 .virtual = (unsigned long)S3C_VA_WATCHDOG,
125 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
126 .length = SZ_4K,
127 .type = MT_DEVICE,
128 }, {
129 .virtual = (unsigned long)S5P_VA_SROMC,
130 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
131 .length = SZ_4K,
132 .type = MT_DEVICE,
133 }, {
134 .virtual = (unsigned long)S5P_VA_SYSTIMER,
135 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
136 .length = SZ_4K,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = (unsigned long)S5P_VA_PMU,
140 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
141 .length = SZ_64K,
142 .type = MT_DEVICE,
143 }, {
144 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
146 .length = SZ_4K,
147 .type = MT_DEVICE,
148 }, {
149 .virtual = (unsigned long)S5P_VA_GIC_CPU,
150 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
151 .length = SZ_64K,
152 .type = MT_DEVICE,
153 }, {
154 .virtual = (unsigned long)S5P_VA_GIC_DIST,
155 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
156 .length = SZ_64K,
157 .type = MT_DEVICE,
158 }, {
159 .virtual = (unsigned long)S3C_VA_UART,
160 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
161 .length = SZ_512K,
162 .type = MT_DEVICE,
163 }, {
164 .virtual = (unsigned long)S5P_VA_CMU,
165 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
166 .length = SZ_128K,
167 .type = MT_DEVICE,
168 }, {
169 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
170 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
171 .length = SZ_8K,
172 .type = MT_DEVICE,
173 }, {
174 .virtual = (unsigned long)S5P_VA_L2CC,
175 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
176 .length = SZ_4K,
177 .type = MT_DEVICE,
178 }, {
179 .virtual = (unsigned long)S5P_VA_GPIO1,
180 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
181 .length = SZ_4K,
182 .type = MT_DEVICE,
183 }, {
184 .virtual = (unsigned long)S5P_VA_GPIO2,
185 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
186 .length = SZ_4K,
187 .type = MT_DEVICE,
188 }, {
189 .virtual = (unsigned long)S5P_VA_GPIO3,
190 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
191 .length = SZ_256,
192 .type = MT_DEVICE,
193 }, {
194 .virtual = (unsigned long)S5P_VA_DMC0,
195 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
196 .length = SZ_64K,
197 .type = MT_DEVICE,
198 }, {
199 .virtual = (unsigned long)S5P_VA_DMC1,
200 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
201 .length = SZ_64K,
202 .type = MT_DEVICE,
203 }, {
204 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
205 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
206 .length = SZ_4K,
207 .type = MT_DEVICE,
208 },
209 };
210
211 static struct map_desc exynos4_iodesc0[] __initdata = {
212 {
213 .virtual = (unsigned long)S5P_VA_SYSRAM,
214 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
215 .length = SZ_4K,
216 .type = MT_DEVICE,
217 },
218 };
219
220 static struct map_desc exynos4_iodesc1[] __initdata = {
221 {
222 .virtual = (unsigned long)S5P_VA_SYSRAM,
223 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
224 .length = SZ_4K,
225 .type = MT_DEVICE,
226 },
227 };
228
229 static struct map_desc exynos5_iodesc[] __initdata = {
230 {
231 .virtual = (unsigned long)S3C_VA_SYS,
232 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
233 .length = SZ_64K,
234 .type = MT_DEVICE,
235 }, {
236 .virtual = (unsigned long)S3C_VA_TIMER,
237 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
238 .length = SZ_16K,
239 .type = MT_DEVICE,
240 }, {
241 .virtual = (unsigned long)S3C_VA_WATCHDOG,
242 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
243 .length = SZ_4K,
244 .type = MT_DEVICE,
245 }, {
246 .virtual = (unsigned long)S5P_VA_SROMC,
247 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
248 .length = SZ_4K,
249 .type = MT_DEVICE,
250 }, {
251 .virtual = (unsigned long)S5P_VA_SYSTIMER,
252 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
253 .length = SZ_4K,
254 .type = MT_DEVICE,
255 }, {
256 .virtual = (unsigned long)S5P_VA_SYSRAM,
257 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
258 .length = SZ_4K,
259 .type = MT_DEVICE,
260 }, {
261 .virtual = (unsigned long)S5P_VA_CMU,
262 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
263 .length = 144 * SZ_1K,
264 .type = MT_DEVICE,
265 }, {
266 .virtual = (unsigned long)S5P_VA_PMU,
267 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
268 .length = SZ_64K,
269 .type = MT_DEVICE,
270 }, {
271 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
272 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
273 .length = SZ_4K,
274 .type = MT_DEVICE,
275 }, {
276 .virtual = (unsigned long)S3C_VA_UART,
277 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
278 .length = SZ_512K,
279 .type = MT_DEVICE,
280 }, {
281 .virtual = (unsigned long)S5P_VA_GIC_CPU,
282 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
283 .length = SZ_64K,
284 .type = MT_DEVICE,
285 }, {
286 .virtual = (unsigned long)S5P_VA_GIC_DIST,
287 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
288 .length = SZ_64K,
289 .type = MT_DEVICE,
290 },
291 };
292
293 void exynos4_restart(char mode, const char *cmd)
294 {
295 __raw_writel(0x1, S5P_SWRESET);
296 }
297
298 void exynos5_restart(char mode, const char *cmd)
299 {
300 __raw_writel(0x1, EXYNOS_SWRESET);
301 }
302
303 /*
304 * exynos_map_io
305 *
306 * register the standard cpu IO areas
307 */
308
309 void __init exynos_init_io(struct map_desc *mach_desc, int size)
310 {
311 /* initialize the io descriptors we need for initialization */
312 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
313 if (mach_desc)
314 iotable_init(mach_desc, size);
315
316 /* detect cpu id and rev. */
317 s5p_init_cpu(S5P_VA_CHIPID);
318
319 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
320 }
321
322 static void __init exynos4_map_io(void)
323 {
324 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
325
326 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
327 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
328 else
329 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
330
331 /* initialize device information early */
332 exynos4_default_sdhci0();
333 exynos4_default_sdhci1();
334 exynos4_default_sdhci2();
335 exynos4_default_sdhci3();
336
337 s3c_adc_setname("samsung-adc-v3");
338
339 s3c_fimc_setname(0, "exynos4-fimc");
340 s3c_fimc_setname(1, "exynos4-fimc");
341 s3c_fimc_setname(2, "exynos4-fimc");
342 s3c_fimc_setname(3, "exynos4-fimc");
343
344 /* The I2C bus controllers are directly compatible with s3c2440 */
345 s3c_i2c0_setname("s3c2440-i2c");
346 s3c_i2c1_setname("s3c2440-i2c");
347 s3c_i2c2_setname("s3c2440-i2c");
348
349 s5p_fb_setname(0, "exynos4-fb");
350 s5p_hdmi_setname("exynos4-hdmi");
351 }
352
353 static void __init exynos5_map_io(void)
354 {
355 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
356
357 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
358 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
359 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
360 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
361
362 /* The I2C bus controllers are directly compatible with s3c2440 */
363 s3c_i2c0_setname("s3c2440-i2c");
364 s3c_i2c1_setname("s3c2440-i2c");
365 s3c_i2c2_setname("s3c2440-i2c");
366 }
367
368 static void __init exynos4_init_clocks(int xtal)
369 {
370 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
371
372 s3c24xx_register_baseclocks(xtal);
373 s5p_register_clocks(xtal);
374
375 if (soc_is_exynos4210())
376 exynos4210_register_clocks();
377 else if (soc_is_exynos4212() || soc_is_exynos4412())
378 exynos4212_register_clocks();
379
380 exynos4_register_clocks();
381 exynos4_setup_clocks();
382 }
383
384 static void __init exynos5_init_clocks(int xtal)
385 {
386 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
387
388 s3c24xx_register_baseclocks(xtal);
389 s5p_register_clocks(xtal);
390
391 exynos5_register_clocks();
392 exynos5_setup_clocks();
393 }
394
395 #define COMBINER_ENABLE_SET 0x0
396 #define COMBINER_ENABLE_CLEAR 0x4
397 #define COMBINER_INT_STATUS 0xC
398
399 static DEFINE_SPINLOCK(irq_controller_lock);
400
401 struct combiner_chip_data {
402 unsigned int irq_offset;
403 unsigned int irq_mask;
404 void __iomem *base;
405 };
406
407 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
408
409 static inline void __iomem *combiner_base(struct irq_data *data)
410 {
411 struct combiner_chip_data *combiner_data =
412 irq_data_get_irq_chip_data(data);
413
414 return combiner_data->base;
415 }
416
417 static void combiner_mask_irq(struct irq_data *data)
418 {
419 u32 mask = 1 << (data->irq % 32);
420
421 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
422 }
423
424 static void combiner_unmask_irq(struct irq_data *data)
425 {
426 u32 mask = 1 << (data->irq % 32);
427
428 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
429 }
430
431 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
432 {
433 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
434 struct irq_chip *chip = irq_get_chip(irq);
435 unsigned int cascade_irq, combiner_irq;
436 unsigned long status;
437
438 chained_irq_enter(chip, desc);
439
440 spin_lock(&irq_controller_lock);
441 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
442 spin_unlock(&irq_controller_lock);
443 status &= chip_data->irq_mask;
444
445 if (status == 0)
446 goto out;
447
448 combiner_irq = __ffs(status);
449
450 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
451 if (unlikely(cascade_irq >= NR_IRQS))
452 do_bad_IRQ(cascade_irq, desc);
453 else
454 generic_handle_irq(cascade_irq);
455
456 out:
457 chained_irq_exit(chip, desc);
458 }
459
460 static struct irq_chip combiner_chip = {
461 .name = "COMBINER",
462 .irq_mask = combiner_mask_irq,
463 .irq_unmask = combiner_unmask_irq,
464 };
465
466 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
467 {
468 unsigned int max_nr;
469
470 if (soc_is_exynos5250())
471 max_nr = EXYNOS5_MAX_COMBINER_NR;
472 else
473 max_nr = EXYNOS4_MAX_COMBINER_NR;
474
475 if (combiner_nr >= max_nr)
476 BUG();
477 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
478 BUG();
479 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
480 }
481
482 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
483 unsigned int irq_start)
484 {
485 unsigned int i;
486 unsigned int max_nr;
487
488 if (soc_is_exynos5250())
489 max_nr = EXYNOS5_MAX_COMBINER_NR;
490 else
491 max_nr = EXYNOS4_MAX_COMBINER_NR;
492
493 if (combiner_nr >= max_nr)
494 BUG();
495
496 combiner_data[combiner_nr].base = base;
497 combiner_data[combiner_nr].irq_offset = irq_start;
498 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
499
500 /* Disable all interrupts */
501
502 __raw_writel(combiner_data[combiner_nr].irq_mask,
503 base + COMBINER_ENABLE_CLEAR);
504
505 /* Setup the Linux IRQ subsystem */
506
507 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
508 + MAX_IRQ_IN_COMBINER; i++) {
509 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
510 irq_set_chip_data(i, &combiner_data[combiner_nr]);
511 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
512 }
513 }
514
515 #ifdef CONFIG_OF
516 static const struct of_device_id exynos4_dt_irq_match[] = {
517 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
518 {},
519 };
520 #endif
521
522 void __init exynos4_init_irq(void)
523 {
524 int irq;
525 unsigned int gic_bank_offset;
526
527 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
528
529 if (!of_have_populated_dt())
530 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
531 #ifdef CONFIG_OF
532 else
533 of_irq_init(exynos4_dt_irq_match);
534 #endif
535
536 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
537
538 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
539 COMBINER_IRQ(irq, 0));
540 combiner_cascade_irq(irq, IRQ_SPI(irq));
541 }
542
543 /*
544 * The parameters of s5p_init_irq() are for VIC init.
545 * Theses parameters should be NULL and 0 because EXYNOS4
546 * uses GIC instead of VIC.
547 */
548 s5p_init_irq(NULL, 0);
549 }
550
551 void __init exynos5_init_irq(void)
552 {
553 int irq;
554
555 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
556
557 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
558 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
559 COMBINER_IRQ(irq, 0));
560 combiner_cascade_irq(irq, IRQ_SPI(irq));
561 }
562
563 /*
564 * The parameters of s5p_init_irq() are for VIC init.
565 * Theses parameters should be NULL and 0 because EXYNOS4
566 * uses GIC instead of VIC.
567 */
568 s5p_init_irq(NULL, 0);
569 }
570
571 struct bus_type exynos4_subsys = {
572 .name = "exynos4-core",
573 .dev_name = "exynos4-core",
574 };
575
576 struct bus_type exynos5_subsys = {
577 .name = "exynos5-core",
578 .dev_name = "exynos5-core",
579 };
580
581 static struct device exynos4_dev = {
582 .bus = &exynos4_subsys,
583 };
584
585 static struct device exynos5_dev = {
586 .bus = &exynos5_subsys,
587 };
588
589 static int __init exynos_core_init(void)
590 {
591 if (soc_is_exynos5250())
592 return subsys_system_register(&exynos5_subsys, NULL);
593 else
594 return subsys_system_register(&exynos4_subsys, NULL);
595 }
596 core_initcall(exynos_core_init);
597
598 #ifdef CONFIG_CACHE_L2X0
599 static int __init exynos4_l2x0_cache_init(void)
600 {
601 if (soc_is_exynos5250())
602 return 0;
603
604 int ret;
605 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
606 if (!ret) {
607 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
608 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
609 return 0;
610 }
611
612 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
613 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
614 /* TAG, Data Latency Control: 2 cycles */
615 l2x0_saved_regs.tag_latency = 0x110;
616
617 if (soc_is_exynos4212() || soc_is_exynos4412())
618 l2x0_saved_regs.data_latency = 0x120;
619 else
620 l2x0_saved_regs.data_latency = 0x110;
621
622 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
623 l2x0_saved_regs.pwr_ctrl =
624 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
625
626 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
627
628 __raw_writel(l2x0_saved_regs.tag_latency,
629 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
630 __raw_writel(l2x0_saved_regs.data_latency,
631 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
632
633 /* L2X0 Prefetch Control */
634 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
635 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
636
637 /* L2X0 Power Control */
638 __raw_writel(l2x0_saved_regs.pwr_ctrl,
639 S5P_VA_L2CC + L2X0_POWER_CTRL);
640
641 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
642 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
643 }
644
645 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
646 return 0;
647 }
648 early_initcall(exynos4_l2x0_cache_init);
649 #endif
650
651 static int __init exynos5_l2_cache_init(void)
652 {
653 unsigned int val;
654
655 if (!soc_is_exynos5250())
656 return 0;
657
658 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
659 "bic %0, %0, #(1 << 2)\n" /* cache disable */
660 "mcr p15, 0, %0, c1, c0, 0\n"
661 "mrc p15, 1, %0, c9, c0, 2\n"
662 : "=r"(val));
663
664 val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
665
666 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
667 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
668 "orr %0, %0, #(1 << 2)\n" /* cache enable */
669 "mcr p15, 0, %0, c1, c0, 0\n"
670 : : "r"(val));
671
672 return 0;
673 }
674 early_initcall(exynos5_l2_cache_init);
675
676 static int __init exynos_init(void)
677 {
678 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
679
680 if (soc_is_exynos5250())
681 return device_register(&exynos5_dev);
682 else
683 return device_register(&exynos4_dev);
684 }
685
686 /* uart registration process */
687
688 static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
689 {
690 struct s3c2410_uartcfg *tcfg = cfg;
691 u32 ucnt;
692
693 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
694 tcfg->has_fracval = 1;
695
696 if (soc_is_exynos5250())
697 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
698 else
699 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
700 }
701
702 static void __iomem *exynos_eint_base;
703
704 static DEFINE_SPINLOCK(eint_lock);
705
706 static unsigned int eint0_15_data[16];
707
708 static inline int exynos4_irq_to_gpio(unsigned int irq)
709 {
710 if (irq < IRQ_EINT(0))
711 return -EINVAL;
712
713 irq -= IRQ_EINT(0);
714 if (irq < 8)
715 return EXYNOS4_GPX0(irq);
716
717 irq -= 8;
718 if (irq < 8)
719 return EXYNOS4_GPX1(irq);
720
721 irq -= 8;
722 if (irq < 8)
723 return EXYNOS4_GPX2(irq);
724
725 irq -= 8;
726 if (irq < 8)
727 return EXYNOS4_GPX3(irq);
728
729 return -EINVAL;
730 }
731
732 static inline int exynos5_irq_to_gpio(unsigned int irq)
733 {
734 if (irq < IRQ_EINT(0))
735 return -EINVAL;
736
737 irq -= IRQ_EINT(0);
738 if (irq < 8)
739 return EXYNOS5_GPX0(irq);
740
741 irq -= 8;
742 if (irq < 8)
743 return EXYNOS5_GPX1(irq);
744
745 irq -= 8;
746 if (irq < 8)
747 return EXYNOS5_GPX2(irq);
748
749 irq -= 8;
750 if (irq < 8)
751 return EXYNOS5_GPX3(irq);
752
753 return -EINVAL;
754 }
755
756 static unsigned int exynos4_eint0_15_src_int[16] = {
757 EXYNOS4_IRQ_EINT0,
758 EXYNOS4_IRQ_EINT1,
759 EXYNOS4_IRQ_EINT2,
760 EXYNOS4_IRQ_EINT3,
761 EXYNOS4_IRQ_EINT4,
762 EXYNOS4_IRQ_EINT5,
763 EXYNOS4_IRQ_EINT6,
764 EXYNOS4_IRQ_EINT7,
765 EXYNOS4_IRQ_EINT8,
766 EXYNOS4_IRQ_EINT9,
767 EXYNOS4_IRQ_EINT10,
768 EXYNOS4_IRQ_EINT11,
769 EXYNOS4_IRQ_EINT12,
770 EXYNOS4_IRQ_EINT13,
771 EXYNOS4_IRQ_EINT14,
772 EXYNOS4_IRQ_EINT15,
773 };
774
775 static unsigned int exynos5_eint0_15_src_int[16] = {
776 EXYNOS5_IRQ_EINT0,
777 EXYNOS5_IRQ_EINT1,
778 EXYNOS5_IRQ_EINT2,
779 EXYNOS5_IRQ_EINT3,
780 EXYNOS5_IRQ_EINT4,
781 EXYNOS5_IRQ_EINT5,
782 EXYNOS5_IRQ_EINT6,
783 EXYNOS5_IRQ_EINT7,
784 EXYNOS5_IRQ_EINT8,
785 EXYNOS5_IRQ_EINT9,
786 EXYNOS5_IRQ_EINT10,
787 EXYNOS5_IRQ_EINT11,
788 EXYNOS5_IRQ_EINT12,
789 EXYNOS5_IRQ_EINT13,
790 EXYNOS5_IRQ_EINT14,
791 EXYNOS5_IRQ_EINT15,
792 };
793 static inline void exynos_irq_eint_mask(struct irq_data *data)
794 {
795 u32 mask;
796
797 spin_lock(&eint_lock);
798 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
799 mask |= EINT_OFFSET_BIT(data->irq);
800 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
801 spin_unlock(&eint_lock);
802 }
803
804 static void exynos_irq_eint_unmask(struct irq_data *data)
805 {
806 u32 mask;
807
808 spin_lock(&eint_lock);
809 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
810 mask &= ~(EINT_OFFSET_BIT(data->irq));
811 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
812 spin_unlock(&eint_lock);
813 }
814
815 static inline void exynos_irq_eint_ack(struct irq_data *data)
816 {
817 __raw_writel(EINT_OFFSET_BIT(data->irq),
818 EINT_PEND(exynos_eint_base, data->irq));
819 }
820
821 static void exynos_irq_eint_maskack(struct irq_data *data)
822 {
823 exynos_irq_eint_mask(data);
824 exynos_irq_eint_ack(data);
825 }
826
827 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
828 {
829 int offs = EINT_OFFSET(data->irq);
830 int shift;
831 u32 ctrl, mask;
832 u32 newvalue = 0;
833
834 switch (type) {
835 case IRQ_TYPE_EDGE_RISING:
836 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
837 break;
838
839 case IRQ_TYPE_EDGE_FALLING:
840 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
841 break;
842
843 case IRQ_TYPE_EDGE_BOTH:
844 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
845 break;
846
847 case IRQ_TYPE_LEVEL_LOW:
848 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
849 break;
850
851 case IRQ_TYPE_LEVEL_HIGH:
852 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
853 break;
854
855 default:
856 printk(KERN_ERR "No such irq type %d", type);
857 return -EINVAL;
858 }
859
860 shift = (offs & 0x7) * 4;
861 mask = 0x7 << shift;
862
863 spin_lock(&eint_lock);
864 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
865 ctrl &= ~mask;
866 ctrl |= newvalue << shift;
867 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
868 spin_unlock(&eint_lock);
869
870 if (soc_is_exynos5250())
871 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
872 else
873 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
874
875 return 0;
876 }
877
878 static struct irq_chip exynos_irq_eint = {
879 .name = "exynos-eint",
880 .irq_mask = exynos_irq_eint_mask,
881 .irq_unmask = exynos_irq_eint_unmask,
882 .irq_mask_ack = exynos_irq_eint_maskack,
883 .irq_ack = exynos_irq_eint_ack,
884 .irq_set_type = exynos_irq_eint_set_type,
885 #ifdef CONFIG_PM
886 .irq_set_wake = s3c_irqext_wake,
887 #endif
888 };
889
890 /*
891 * exynos4_irq_demux_eint
892 *
893 * This function demuxes the IRQ from from EINTs 16 to 31.
894 * It is designed to be inlined into the specific handler
895 * s5p_irq_demux_eintX_Y.
896 *
897 * Each EINT pend/mask registers handle eight of them.
898 */
899 static inline void exynos_irq_demux_eint(unsigned int start)
900 {
901 unsigned int irq;
902
903 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
904 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
905
906 status &= ~mask;
907 status &= 0xff;
908
909 while (status) {
910 irq = fls(status) - 1;
911 generic_handle_irq(irq + start);
912 status &= ~(1 << irq);
913 }
914 }
915
916 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
917 {
918 struct irq_chip *chip = irq_get_chip(irq);
919 chained_irq_enter(chip, desc);
920 exynos_irq_demux_eint(IRQ_EINT(16));
921 exynos_irq_demux_eint(IRQ_EINT(24));
922 chained_irq_exit(chip, desc);
923 }
924
925 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
926 {
927 u32 *irq_data = irq_get_handler_data(irq);
928 struct irq_chip *chip = irq_get_chip(irq);
929
930 chained_irq_enter(chip, desc);
931 chip->irq_mask(&desc->irq_data);
932
933 if (chip->irq_ack)
934 chip->irq_ack(&desc->irq_data);
935
936 generic_handle_irq(*irq_data);
937
938 chip->irq_unmask(&desc->irq_data);
939 chained_irq_exit(chip, desc);
940 }
941
942 static int __init exynos_init_irq_eint(void)
943 {
944 int irq;
945
946 if (soc_is_exynos5250())
947 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
948 else
949 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
950
951 if (exynos_eint_base == NULL) {
952 pr_err("unable to ioremap for EINT base address\n");
953 return -ENOMEM;
954 }
955
956 for (irq = 0 ; irq <= 31 ; irq++) {
957 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
958 handle_level_irq);
959 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
960 }
961
962 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
963
964 for (irq = 0 ; irq <= 15 ; irq++) {
965 eint0_15_data[irq] = IRQ_EINT(irq);
966
967 if (soc_is_exynos5250()) {
968 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
969 &eint0_15_data[irq]);
970 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
971 exynos_irq_eint0_15);
972 } else {
973 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
974 &eint0_15_data[irq]);
975 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
976 exynos_irq_eint0_15);
977 }
978 }
979
980 return 0;
981 }
982 arch_initcall(exynos_init_irq_eint);
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