arch/arm/mach-s3c2440/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005,2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/device.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/clk.h>
  22 #include <linux/i2c.h>
  23
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/mach/irq.h>
  27
  28 #include <mach/osiris-map.h>
  29 #include <mach/osiris-cpld.h>
  30
  31 #include <mach/hardware.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/mach-types.h>
  35
  36 #include <asm/plat-s3c/regs-serial.h>
  37 #include <mach/regs-gpio.h>
  38 #include <mach/regs-mem.h>
  39 #include <mach/regs-lcd.h>
  40 #include <asm/plat-s3c/nand.h>
  41
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/partitions.h>
  46
  47 #include <asm/plat-s3c24xx/clock.h>
  48 #include <asm/plat-s3c24xx/devs.h>
  49 #include <asm/plat-s3c24xx/cpu.h>
  50
  51 /* onboard perihperal map */
  52
  53 static struct map_desc osiris_iodesc[] __initdata = {
  54   /* ISA IO areas (may be over-written later) */
  55
  56   {
  57           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  58           .pfn          = __phys_to_pfn(S3C2410_CS5),
  59           .length       = SZ_16M,
  60           .type         = MT_DEVICE,
  61   }, {
  62           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  63           .pfn          = __phys_to_pfn(S3C2410_CS5),
  64           .length       = SZ_16M,
  65           .type         = MT_DEVICE,
  66   },
  67
  68   /* CPLD control registers */
  69
  70   {
  71           .virtual      = (u32)OSIRIS_VA_CTRL0,
  72           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  73           .length       = SZ_16K,
  74           .type         = MT_DEVICE,
  75   }, {
  76           .virtual      = (u32)OSIRIS_VA_CTRL1,
  77           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  78           .length       = SZ_16K,
  79           .type         = MT_DEVICE,
  80   }, {
  81           .virtual      = (u32)OSIRIS_VA_CTRL2,
  82           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  83           .length       = SZ_16K,
  84           .type         = MT_DEVICE,
  85   }, {
  86           .virtual      = (u32)OSIRIS_VA_IDREG,
  87           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  88           .length       = SZ_16K,
  89           .type         = MT_DEVICE,
  90   },
  91 };
  92
  93 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  94 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  95 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  96
  97 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
  98         [0] = {
  99                 .name           = "uclk",
 100                 .divisor        = 1,
 101                 .min_baud       = 0,
 102                 .max_baud       = 0,
 103         },
 104         [1] = {
 105                 .name           = "pclk",
 106                 .divisor        = 1,
 107                 .min_baud       = 0,
 108                 .max_baud       = 0,
 109         }
 110 };
 111
 112 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 113         [0] = {
 114                 .hwport      = 0,
 115                 .flags       = 0,
 116                 .ucon        = UCON,
 117                 .ulcon       = ULCON,
 118                 .ufcon       = UFCON,
 119                 .clocks      = osiris_serial_clocks,
 120                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 121         },
 122         [1] = {
 123                 .hwport      = 1,
 124                 .flags       = 0,
 125                 .ucon        = UCON,
 126                 .ulcon       = ULCON,
 127                 .ufcon       = UFCON,
 128                 .clocks      = osiris_serial_clocks,
 129                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 130         },
 131         [2] = {
 132                 .hwport      = 2,
 133                 .flags       = 0,
 134                 .ucon        = UCON,
 135                 .ulcon       = ULCON,
 136                 .ufcon       = UFCON,
 137                 .clocks      = osiris_serial_clocks,
 138                 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
 139         }
 140 };
 141
 142 /* NAND Flash on Osiris board */
 143
 144 static int external_map[]   = { 2 };
 145 static int chip0_map[]      = { 0 };
 146 static int chip1_map[]      = { 1 };
 147
 148 static struct mtd_partition osiris_default_nand_part[] = {
 149         [0] = {
 150                 .name   = "Boot Agent",
 151                 .size   = SZ_16K,
 152                 .offset = 0,
 153         },
 154         [1] = {
 155                 .name   = "/boot",
 156                 .size   = SZ_4M - SZ_16K,
 157                 .offset = SZ_16K,
 158         },
 159         [2] = {
 160                 .name   = "user1",
 161                 .offset = SZ_4M,
 162                 .size   = SZ_32M - SZ_4M,
 163         },
 164         [3] = {
 165                 .name   = "user2",
 166                 .offset = SZ_32M,
 167                 .size   = MTDPART_SIZ_FULL,
 168         }
 169 };
 170
 171 static struct mtd_partition osiris_default_nand_part_large[] = {
 172         [0] = {
 173                 .name   = "Boot Agent",
 174                 .size   = SZ_128K,
 175                 .offset = 0,
 176         },
 177         [1] = {
 178                 .name   = "/boot",
 179                 .size   = SZ_4M - SZ_128K,
 180                 .offset = SZ_128K,
 181         },
 182         [2] = {
 183                 .name   = "user1",
 184                 .offset = SZ_4M,
 185                 .size   = SZ_32M - SZ_4M,
 186         },
 187         [3] = {
 188                 .name   = "user2",
 189                 .offset = SZ_32M,
 190                 .size   = MTDPART_SIZ_FULL,
 191         }
 192 };
 193
 194 /* the Osiris has 3 selectable slots for nand-flash, the two
 195  * on-board chip areas, as well as the external slot.
 196  *
 197  * Note, there is no current hot-plug support for the External
 198  * socket.
 199 */
 200
 201 static struct s3c2410_nand_set osiris_nand_sets[] = {
 202         [1] = {
 203                 .name           = "External",
 204                 .nr_chips       = 1,
 205                 .nr_map         = external_map,
 206                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 207                 .partitions     = osiris_default_nand_part,
 208         },
 209         [0] = {
 210                 .name           = "chip0",
 211                 .nr_chips       = 1,
 212                 .nr_map         = chip0_map,
 213                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 214                 .partitions     = osiris_default_nand_part,
 215         },
 216         [2] = {
 217                 .name           = "chip1",
 218                 .nr_chips       = 1,
 219                 .nr_map         = chip1_map,
 220                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 221                 .partitions     = osiris_default_nand_part,
 222         },
 223 };
 224
 225 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 226 {
 227         unsigned int tmp;
 228
 229         slot = set->nr_map[slot] & 3;
 230
 231         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 232                  slot, set, set->nr_map);
 233
 234         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 235         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 236         tmp |= slot;
 237
 238         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 239
 240         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 241 }
 242
 243 static struct s3c2410_platform_nand osiris_nand_info = {
 244         .tacls          = 25,
 245         .twrph0         = 60,
 246         .twrph1         = 60,
 247         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 248         .sets           = osiris_nand_sets,
 249         .select_chip    = osiris_nand_select,
 250 };
 251
 252 /* PCMCIA control and configuration */
 253
 254 static struct resource osiris_pcmcia_resource[] = {
 255         [0] = {
 256                 .start  = 0x0f000000,
 257                 .end    = 0x0f100000,
 258                 .flags  = IORESOURCE_MEM,
 259         },
 260         [1] = {
 261                 .start  = 0x0c000000,
 262                 .end    = 0x0c100000,
 263                 .flags  = IORESOURCE_MEM,
 264         }
 265 };
 266
 267 static struct platform_device osiris_pcmcia = {
 268         .name           = "osiris-pcmcia",
 269         .id             = -1,
 270         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 271         .resource       = osiris_pcmcia_resource,
 272 };
 273
 274 /* Osiris power management device */
 275
 276 #ifdef CONFIG_PM
 277 static unsigned char pm_osiris_ctrl0;
 278
 279 static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
 280 {
 281         unsigned int tmp;
 282
 283         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 284         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 285
 286         /* ensure correct NAND slot is selected on resume */
 287         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 288                 tmp |= 2;
 289
 290         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 291
 292         /* ensure that an nRESET is not generated on resume. */
 293         s3c2410_gpio_setpin(S3C2410_GPA21, 1);
 294         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
 295
 296         return 0;
 297 }
 298
 299 static int osiris_pm_resume(struct sys_device *sd)
 300 {
 301         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 302                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 303
 304         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 305
 306         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
 307
 308         return 0;
 309 }
 310
 311 #else
 312 #define osiris_pm_suspend NULL
 313 #define osiris_pm_resume NULL
 314 #endif
 315
 316 static struct sysdev_class osiris_pm_sysclass = {
 317         .name           = "mach-osiris",
 318         .suspend        = osiris_pm_suspend,
 319         .resume         = osiris_pm_resume,
 320 };
 321
 322 static struct sys_device osiris_pm_sysdev = {
 323         .cls            = &osiris_pm_sysclass,
 324 };
 325
 326 /* I2C devices fitted. */
 327
 328 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 329         {
 330                 I2C_BOARD_INFO("tps65011", 0x48),
 331                 .irq    = IRQ_EINT20,
 332         },
 333 };
 334
 335 /* Standard Osiris devices */
 336
 337 static struct platform_device *osiris_devices[] __initdata = {
 338         &s3c_device_i2c,
 339         &s3c_device_wdt,
 340         &s3c_device_nand,
 341         &osiris_pcmcia,
 342 };
 343
 344 static struct clk *osiris_clocks[] = {
 345         &s3c24xx_dclk0,
 346         &s3c24xx_dclk1,
 347         &s3c24xx_clkout0,
 348         &s3c24xx_clkout1,
 349         &s3c24xx_uclk,
 350 };
 351
 352 static void __init osiris_map_io(void)
 353 {
 354         unsigned long flags;
 355
 356         /* initialise the clocks */
 357
 358         s3c24xx_dclk0.parent = &clk_upll;
 359         s3c24xx_dclk0.rate   = 12*1000*1000;
 360
 361         s3c24xx_dclk1.parent = &clk_upll;
 362         s3c24xx_dclk1.rate   = 24*1000*1000;
 363
 364         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 365         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 366
 367         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 368
 369         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 370
 371         s3c_device_nand.dev.platform_data = &osiris_nand_info;
 372
 373         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 374         s3c24xx_init_clocks(0);
 375         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 376
 377         /* check for the newer revision boards with large page nand */
 378
 379         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 380                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 381                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 382                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 383                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 384         } else {
 385                 /* write-protect line to the NAND */
 386                 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 387         }
 388
 389         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 390
 391         local_irq_save(flags);
 392         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 393         local_irq_restore(flags);
 394 }
 395
 396 static void __init osiris_init(void)
 397 {
 398         sysdev_class_register(&osiris_pm_sysclass);
 399         sysdev_register(&osiris_pm_sysdev);
 400
 401         i2c_register_board_info(0, osiris_i2c_devs,
 402                                 ARRAY_SIZE(osiris_i2c_devs));
 403
 404         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 405 };
 406
 407 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 408         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 409         .phys_io        = S3C2410_PA_UART,
 410         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 411         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 412         .map_io         = osiris_map_io,
 413         .init_machine   = osiris_init,
 414         .init_irq       = s3c24xx_init_irq,
 415         .init_machine   = osiris_init,
 416         .timer          = &s3c24xx_timer,
 417 MACHINE_END