1 comment "Processor Type"
3 # Select CPU types depending on the architecture selected. This selects
4 # which CPUs we support in the kernel image, and the compiler instruction
14 select CPU_PABRT_LEGACY
16 A 32-bit RISC microprocessor based on the ARM7 processor core
17 which has no memory control unit and cache.
19 Say Y if you want support for the ARM7TDMI processor.
29 select CPU_COPY_V4WT if MMU
31 select CPU_PABRT_LEGACY
32 select CPU_THUMB_CAPABLE
33 select CPU_TLB_V4WT if MMU
35 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
36 MMU built around an ARM7TDMI core.
38 Say Y if you want support for the ARM720T processor.
49 select CPU_PABRT_LEGACY
50 select CPU_THUMB_CAPABLE
52 A 32-bit RISC processor with 8KB cache or 4KB variants,
53 write buffer and MPU(Protection Unit) built around
56 Say Y if you want support for the ARM740T processor.
66 select CPU_PABRT_LEGACY
68 A 32-bit RISC microprocessor based on the ARM9 processor core
69 which has no memory control unit and cache.
71 Say Y if you want support for the ARM9TDMI processor.
81 select CPU_COPY_V4WB if MMU
83 select CPU_PABRT_LEGACY
84 select CPU_THUMB_CAPABLE
85 select CPU_TLB_V4WBI if MMU
87 The ARM920T is licensed to be produced by numerous vendors,
88 and is used in the Cirrus EP93xx and the Samsung S3C2410.
90 Say Y if you want support for the ARM920T processor.
100 select CPU_COPY_V4WB if MMU
102 select CPU_PABRT_LEGACY
103 select CPU_THUMB_CAPABLE
104 select CPU_TLB_V4WBI if MMU
106 The ARM922T is a version of the ARM920T, but with smaller
107 instruction and data caches. It is used in Altera's
108 Excalibur XA device family and Micrel's KS8695 Centaur.
110 Say Y if you want support for the ARM922T processor.
118 select CPU_CACHE_V4WT
119 select CPU_CACHE_VIVT
120 select CPU_COPY_V4WB if MMU
122 select CPU_PABRT_LEGACY
123 select CPU_THUMB_CAPABLE
124 select CPU_TLB_V4WBI if MMU
126 The ARM925T is a mix between the ARM920T and ARM926T, but with
127 different instruction and data caches. It is used in TI's OMAP
130 Say Y if you want support for the ARM925T processor.
137 select CPU_ABRT_EV5TJ
138 select CPU_CACHE_VIVT
139 select CPU_COPY_V4WB if MMU
141 select CPU_PABRT_LEGACY
142 select CPU_THUMB_CAPABLE
143 select CPU_TLB_V4WBI if MMU
145 This is a variant of the ARM920. It has slightly different
146 instruction sequences for cache and TLB operations. Curiously,
147 there is no documentation on it at the ARM corporate website.
149 Say Y if you want support for the ARM926T processor.
158 select CPU_CACHE_VIVT
159 select CPU_COPY_FA if MMU
161 select CPU_PABRT_LEGACY
162 select CPU_TLB_FA if MMU
164 The FA526 is a version of the ARMv4 compatible processor with
165 Branch Target Buffer, Unified TLB and cache line size 16.
167 Say Y if you want support for the FA526 processor.
175 select CPU_ABRT_NOMMU
176 select CPU_CACHE_VIVT
178 select CPU_PABRT_LEGACY
179 select CPU_THUMB_CAPABLE
181 ARM940T is a member of the ARM9TDMI family of general-
182 purpose microprocessors with MPU and separate 4KB
183 instruction and 4KB data cases, each with a 4-word line
186 Say Y if you want support for the ARM940T processor.
194 select CPU_ABRT_NOMMU
195 select CPU_CACHE_VIVT
197 select CPU_PABRT_LEGACY
198 select CPU_THUMB_CAPABLE
200 ARM946E-S is a member of the ARM9E-S family of high-
201 performance, 32-bit system-on-chip processor solutions.
202 The TCM and ARMv5TE 32-bit instruction set is supported.
204 Say Y if you want support for the ARM946E-S processor.
207 # ARM1020 - needs validating
212 select CPU_CACHE_V4WT
213 select CPU_CACHE_VIVT
214 select CPU_COPY_V4WB if MMU
216 select CPU_PABRT_LEGACY
217 select CPU_THUMB_CAPABLE
218 select CPU_TLB_V4WBI if MMU
220 The ARM1020 is the 32K cached version of the ARM10 processor,
221 with an addition of a floating-point unit.
223 Say Y if you want support for the ARM1020 processor.
226 # ARM1020E - needs validating
232 select CPU_CACHE_V4WT
233 select CPU_CACHE_VIVT
234 select CPU_COPY_V4WB if MMU
236 select CPU_PABRT_LEGACY
237 select CPU_THUMB_CAPABLE
238 select CPU_TLB_V4WBI if MMU
245 select CPU_CACHE_VIVT
246 select CPU_COPY_V4WB if MMU # can probably do better
248 select CPU_PABRT_LEGACY
249 select CPU_THUMB_CAPABLE
250 select CPU_TLB_V4WBI if MMU
252 The ARM1022E is an implementation of the ARMv5TE architecture
253 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
254 embedded trace macrocell, and a floating-point unit.
256 Say Y if you want support for the ARM1022E processor.
263 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
264 select CPU_CACHE_VIVT
265 select CPU_COPY_V4WB if MMU # can probably do better
267 select CPU_PABRT_LEGACY
268 select CPU_THUMB_CAPABLE
269 select CPU_TLB_V4WBI if MMU
271 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
272 based upon the ARM10 integer core.
274 Say Y if you want support for the ARM1026EJ-S processor.
280 select CPU_32v3 if ARCH_RPC
281 select CPU_32v4 if !ARCH_RPC
283 select CPU_CACHE_V4WB
284 select CPU_CACHE_VIVT
285 select CPU_COPY_V4WB if MMU
287 select CPU_PABRT_LEGACY
288 select CPU_TLB_V4WB if MMU
290 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
291 is available at five speeds ranging from 100 MHz to 233 MHz.
292 More information is available at
293 <http://developer.intel.com/design/strong/sa110.htm>.
295 Say Y if you want support for the SA-110 processor.
303 select CPU_CACHE_V4WB
304 select CPU_CACHE_VIVT
306 select CPU_PABRT_LEGACY
307 select CPU_TLB_V4WB if MMU
314 select CPU_CACHE_VIVT
316 select CPU_PABRT_LEGACY
317 select CPU_THUMB_CAPABLE
318 select CPU_TLB_V4WBI if MMU
320 # XScale Core Version 3
325 select CPU_CACHE_VIVT
327 select CPU_PABRT_LEGACY
328 select CPU_THUMB_CAPABLE
329 select CPU_TLB_V4WBI if MMU
332 # Marvell PJ1 (Mohawk)
337 select CPU_CACHE_VIVT
338 select CPU_COPY_V4WB if MMU
340 select CPU_PABRT_LEGACY
341 select CPU_THUMB_CAPABLE
342 select CPU_TLB_V4WBI if MMU
349 select CPU_CACHE_VIVT
350 select CPU_COPY_FEROCEON if MMU
352 select CPU_PABRT_LEGACY
353 select CPU_THUMB_CAPABLE
354 select CPU_TLB_FEROCEON if MMU
356 config CPU_FEROCEON_OLD_ID
357 bool "Accept early Feroceon cores with an ARM926 ID"
358 depends on CPU_FEROCEON && !CPU_ARM926T
361 This enables the usage of some old Feroceon cores
362 for which the CPU ID is equal to the ARM926 ID.
363 Relevant for Feroceon-1850 and early Feroceon-2850.
381 select CPU_CACHE_VIPT
382 select CPU_COPY_V6 if MMU
384 select CPU_HAS_ASID if MMU
386 select CPU_THUMB_CAPABLE
387 select CPU_TLB_V6 if MMU
396 select CPU_CACHE_VIPT
397 select CPU_COPY_V6 if MMU
399 select CPU_HAS_ASID if MMU
401 select CPU_THUMB_CAPABLE
402 select CPU_TLB_V6 if MMU
411 select CPU_CACHE_VIPT
412 select CPU_COPY_V6 if MMU
413 select CPU_CP15_MMU if MMU
414 select CPU_CP15_MPU if !MMU
415 select CPU_HAS_ASID if MMU
417 select CPU_THUMB_CAPABLE
418 select CPU_TLB_V7 if MMU
424 select CPU_ABRT_NOMMU
427 select CPU_PABRT_LEGACY
432 select CPU_THUMB_CAPABLE
433 # There are no CPUs available with MMU that don't implement an ARM ISA:
436 Select this if your CPU doesn't support the 32 bit ARM instructions.
438 config CPU_THUMB_CAPABLE
441 Select this if your CPU can support Thumb mode.
443 # Figure out what processor architecture version we should be using.
444 # This defines the compiler instruction set which depends on the machine type.
447 select CPU_USE_DOMAINS if MMU
448 select NEED_KUSER_HELPERS
449 select TLS_REG_EMUL if SMP || !MMU
450 select CPU_NO_EFFICIENT_FFS
454 select CPU_USE_DOMAINS if MMU
455 select NEED_KUSER_HELPERS
456 select TLS_REG_EMUL if SMP || !MMU
457 select CPU_NO_EFFICIENT_FFS
461 select CPU_USE_DOMAINS if MMU
462 select NEED_KUSER_HELPERS
463 select TLS_REG_EMUL if SMP || !MMU
464 select CPU_NO_EFFICIENT_FFS
468 select CPU_USE_DOMAINS if MMU
469 select NEED_KUSER_HELPERS
470 select TLS_REG_EMUL if SMP || !MMU
474 select TLS_REG_EMUL if !CPU_32v6K && !MMU
486 config CPU_ABRT_NOMMU
501 config CPU_ABRT_EV5TJ
510 config CPU_PABRT_LEGACY
523 config CPU_CACHE_V4WT
526 config CPU_CACHE_V4WB
538 config CPU_CACHE_VIVT
541 config CPU_CACHE_VIPT
551 # The copy-page model
558 config CPU_COPY_FEROCEON
567 # This selects the TLB model
571 ARM Architecture Version 4 TLB with writethrough cache.
576 ARM Architecture Version 4 TLB with writeback cache.
581 ARM Architecture Version 4 TLB with writeback cache and invalidate
582 instruction cache entry.
584 config CPU_TLB_FEROCEON
587 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
592 Faraday ARM FA526 architecture, unified TLB with writeback cache
593 and invalidate instruction cache entry. Branch target buffer is
602 config VERIFY_PERMISSION_FAULT
609 This indicates whether the CPU has the ASID register; used to
610 tag TLB and possibly cache entries.
615 Processor has the CP15 register.
621 Processor has the CP15 register, which has MMU related registers.
627 Processor has the CP15 register, which has MPU related registers.
629 config CPU_USE_DOMAINS
632 This option enables or disables the use of domain switching
633 via the set_fs() function.
635 config CPU_V7M_NUM_IRQ
636 int "Number of external interrupts connected to the NVIC"
638 default 90 if ARCH_STM32
639 default 38 if ARCH_EFM32
640 default 112 if SOC_VF610
643 This option indicates the number of interrupts connected to the NVIC.
644 The value can be larger than the real number of interrupts supported
645 by the system, but must not be lower.
646 The default value is 240, corresponding to the maximum number of
647 interrupts supported by the NVIC on Cortex-M family.
649 If unsure, keep default value.
652 # CPU supports 36-bit I/O
657 comment "Processor Features"
660 bool "Support for the Large Physical Address Extension"
661 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
662 !CPU_32v4 && !CPU_32v3
664 Say Y if you have an ARMv7 processor supporting the LPAE page
665 table format and you would like to access memory beyond the
666 4GB limit. The resulting kernel image will not run on
667 processors without the LPA extension.
673 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
675 config ARCH_PHYS_ADDR_T_64BIT
678 config ARCH_DMA_ADDR_T_64BIT
682 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
683 depends on CPU_THUMB_CAPABLE
686 Say Y if you want to include kernel support for running user space
689 The Thumb instruction set is a compressed form of the standard ARM
690 instruction set resulting in smaller binaries at the expense of
691 slightly less efficient code.
693 If this option is disabled, and you run userspace that switches to
694 Thumb mode, signal handling will not work correctly, resulting in
695 segmentation faults or illegal instruction aborts.
697 If you don't know what this all is, saying Y is a safe choice.
700 bool "Enable ThumbEE CPU extension"
703 Say Y here if you have a CPU with the ThumbEE extension and code to
704 make use of it. Say N for code that can run on CPUs without ThumbEE.
711 Enable the kernel to make use of the ARM Virtualization
712 Extensions to install hypervisors without run-time firmware
715 A compliant bootloader is required in order to make maximum
716 use of this feature. Refer to Documentation/arm/Booting for
720 bool "Emulate SWP/SWPB instructions" if !SMP
723 select HAVE_PROC_CPU if PROC_FS
725 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
726 ARMv7 multiprocessing extensions introduce the ability to disable
727 these instructions, triggering an undefined instruction exception
728 when executed. Say Y here to enable software emulation of these
729 instructions for userspace (not kernel) using LDREX/STREX.
730 Also creates /proc/cpu/swp_emulation for statistics.
732 In some older versions of glibc [<=2.8] SWP is used during futex
733 trylock() operations with the assumption that the code will not
734 be preempted. This invalid assumption may be more likely to fail
735 with SWP emulation enabled, leading to deadlock of the user
738 NOTE: when accessing uncached shared regions, LDREX/STREX rely
739 on an external transaction monitoring block called a global
740 monitor to maintain update atomicity. If your system does not
741 implement a global monitor, this option can cause programs that
742 perform SWP operations to uncached memory to deadlock.
746 config CPU_BIG_ENDIAN
747 bool "Build big-endian kernel"
748 depends on ARCH_SUPPORTS_BIG_ENDIAN
750 Say Y if you plan on running a kernel in big-endian mode.
751 Note that your board must be properly built and your board
752 port must properly enable any big-endian related features
753 of your chipset/board/processor.
755 config CPU_ENDIAN_BE8
757 depends on CPU_BIG_ENDIAN
758 default CPU_V6 || CPU_V6K || CPU_V7
760 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
762 config CPU_ENDIAN_BE32
764 depends on CPU_BIG_ENDIAN
765 default !CPU_ENDIAN_BE8
767 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
769 config CPU_HIGH_VECTOR
770 depends on !MMU && CPU_CP15 && !CPU_ARM740T
771 bool "Select the High exception vector"
773 Say Y here to select high exception vector(0xFFFF0000~).
774 The exception vector can vary depending on the platform
775 design in nommu mode. If your platform needs to select
776 high exception vector, say Y.
777 Otherwise or if you are unsure, say N, and the low exception
778 vector (0x00000000~) will be used.
780 config CPU_ICACHE_DISABLE
781 bool "Disable I-Cache (I-bit)"
782 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
784 Say Y here to disable the processor instruction cache. Unless
785 you have a reason not to or are unsure, say N.
787 config CPU_DCACHE_DISABLE
788 bool "Disable D-Cache (C-bit)"
789 depends on (CPU_CP15 && !SMP) || CPU_V7M
791 Say Y here to disable the processor data cache. Unless
792 you have a reason not to or are unsure, say N.
794 config CPU_DCACHE_SIZE
796 depends on CPU_ARM740T || CPU_ARM946E
797 default 0x00001000 if CPU_ARM740T
798 default 0x00002000 # default size for ARM946E-S
800 Some cores are synthesizable to have various sized cache. For
801 ARM946E-S case, it can vary from 0KB to 1MB.
802 To support such cache operations, it is efficient to know the size
804 If your SoC is configured to have a different size, define the value
805 here with proper conditions.
807 config CPU_DCACHE_WRITETHROUGH
808 bool "Force write through D-cache"
809 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
810 default y if CPU_ARM925T
812 Say Y here to use the data cache in writethrough mode. Unless you
813 specifically require this or are unsure, say N.
815 config CPU_CACHE_ROUND_ROBIN
816 bool "Round robin I and D cache replacement algorithm"
817 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
819 Say Y here to use the predictable round-robin cache replacement
820 policy. Unless you specifically require this or are unsure, say N.
822 config CPU_BPREDICT_DISABLE
823 bool "Disable branch prediction"
824 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
826 Say Y here to disable branch prediction. If unsure, say N.
830 select NEED_KUSER_HELPERS
832 An SMP system using a pre-ARMv6 processor (there are apparently
833 a few prototypes like that in existence) and therefore access to
834 that required register must be emulated.
836 config NEED_KUSER_HELPERS
840 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
844 Warning: disabling this option may break user programs.
846 Provide kuser helpers in the vector page. The kernel provides
847 helper code to userspace in read only form at a fixed location
848 in the high vector page to allow userspace to be independent of
849 the CPU type fitted to the system. This permits binaries to be
850 run on ARMv4 through to ARMv7 without modification.
852 See Documentation/arm/kernel_user_helpers.txt for details.
854 However, the fixed address nature of these helpers can be used
855 by ROP (return orientated programming) authors when creating
858 If all of the binaries and libraries which run on your platform
859 are built specifically for your platform, and make no use of
860 these helpers, then you can turn this option off to hinder
861 such exploits. However, in that case, if a binary or library
862 relying on those helpers is run, it will receive a SIGILL signal,
863 which will terminate the program.
865 Say N here only if you are absolutely certain that you do not
866 need these helpers; otherwise, the safe option is to say Y.
869 bool "Enable VDSO for acceleration of some system calls"
870 depends on AEABI && MMU && CPU_V7
871 default y if ARM_ARCH_TIMER
872 select GENERIC_TIME_VSYSCALL
874 Place in the process address space an ELF shared object
875 providing fast implementations of gettimeofday and
876 clock_gettime. Systems that implement the ARM architected
877 timer will receive maximum benefit.
879 You must have glibc 2.22 or later for programs to seamlessly
880 take advantage of this.
882 config DMA_CACHE_RWFO
883 bool "Enable read/write for ownership DMA cache maintenance"
884 depends on CPU_V6K && SMP
887 The Snoop Control Unit on ARM11MPCore does not detect the
888 cache maintenance operations and the dma_{map,unmap}_area()
889 functions may leave stale cache entries on other CPUs. By
890 enabling this option, Read or Write For Ownership in the ARMv6
891 DMA cache maintenance functions is performed. These LDR/STR
892 instructions change the cache line state to shared or modified
893 so that the cache operation has the desired effect.
895 Note that the workaround is only valid on processors that do
896 not perform speculative loads into the D-cache. For such
897 processors, if cache maintenance operations are not broadcast
898 in hardware, other workarounds are needed (e.g. cache
899 maintenance broadcasting in software via FIQ).
904 config OUTER_CACHE_SYNC
908 The outer cache has a outer_cache_fns.sync function pointer
909 that can be used to drain the write buffer of the outer cache.
911 config CACHE_FEROCEON_L2
912 bool "Enable the Feroceon L2 cache controller"
913 depends on ARCH_MV78XX0 || ARCH_MVEBU
917 This option enables the Feroceon L2 cache controller.
919 config CACHE_FEROCEON_L2_WRITETHROUGH
920 bool "Force Feroceon L2 cache write through"
921 depends on CACHE_FEROCEON_L2
923 Say Y here to use the Feroceon L2 cache in writethrough mode.
924 Unless you specifically require this, say N for writeback mode.
926 config MIGHT_HAVE_CACHE_L2X0
929 This option should be selected by machines which have a L2x0
930 or PL310 cache controller, but where its use is optional.
932 The only effect of this option is to make CACHE_L2X0 and
933 related options available to the user for configuration.
935 Boards or SoCs which always require the cache controller
936 support to be present should select CACHE_L2X0 directly
937 instead of this option, thus preventing the user from
938 inadvertently configuring a broken kernel.
941 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
942 default MIGHT_HAVE_CACHE_L2X0
944 select OUTER_CACHE_SYNC
946 This option enables the L2x0 PrimeCell.
948 config CACHE_L2X0_PMU
949 bool "L2x0 performance monitor support" if CACHE_L2X0
950 depends on PERF_EVENTS
952 This option enables support for the performance monitoring features
953 of the L220 and PL310 outer cache controllers.
957 config PL310_ERRATA_588369
958 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
960 The PL310 L2 cache controller implements three types of Clean &
961 Invalidate maintenance operations: by Physical Address
962 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
963 They are architecturally defined to behave as the execution of a
964 clean operation followed immediately by an invalidate operation,
965 both performing to the same memory location. This functionality
966 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
967 as clean lines are not invalidated as a result of these operations.
969 config PL310_ERRATA_727915
970 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
972 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
973 operation (offset 0x7FC). This operation runs in background so that
974 PL310 can handle normal accesses while it is in progress. Under very
975 rare circumstances, due to this erratum, write data can be lost when
976 PL310 treats a cacheable write transaction during a Clean &
977 Invalidate by Way operation. Revisions prior to r3p1 are affected by
978 this errata (fixed in r3p1).
980 config PL310_ERRATA_753970
981 bool "PL310 errata: cache sync operation may be faulty"
983 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
985 Under some condition the effect of cache sync operation on
986 the store buffer still remains when the operation completes.
987 This means that the store buffer is always asked to drain and
988 this prevents it from merging any further writes. The workaround
989 is to replace the normal offset of cache sync operation (0x730)
990 by another offset targeting an unmapped PL310 register 0x740.
991 This has the same effect as the cache sync operation: store buffer
992 drain and waiting for all buffers empty.
994 config PL310_ERRATA_769419
995 bool "PL310 errata: no automatic Store Buffer drain"
997 On revisions of the PL310 prior to r3p2, the Store Buffer does
998 not automatically drain. This can cause normal, non-cacheable
999 writes to be retained when the memory system is idle, leading
1000 to suboptimal I/O performance for drivers using coherent DMA.
1001 This option adds a write barrier to the cpu_idle loop so that,
1002 on systems with an outer cache, the store buffer is drained
1007 config CACHE_TAUROS2
1008 bool "Enable the Tauros2 L2 cache controller"
1009 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
1013 This option enables the Tauros2 L2 cache controller (as
1016 config CACHE_UNIPHIER
1017 bool "Enable the UniPhier outer cache controller"
1018 depends on ARCH_UNIPHIER
1019 select ARM_L1_CACHE_SHIFT_7
1021 select OUTER_CACHE_SYNC
1023 This option enables the UniPhier outer cache (system cache)
1027 bool "Enable the L2 cache on XScale3"
1032 This option enables the L2 cache on XScale3.
1034 config ARM_L1_CACHE_SHIFT_6
1038 Setting ARM L1 cache line size to 64 Bytes.
1040 config ARM_L1_CACHE_SHIFT_7
1043 Setting ARM L1 cache line size to 128 Bytes.
1045 config ARM_L1_CACHE_SHIFT
1047 default 7 if ARM_L1_CACHE_SHIFT_7
1048 default 6 if ARM_L1_CACHE_SHIFT_6
1051 config ARM_DMA_MEM_BUFFERABLE
1052 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1053 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1055 Historically, the kernel has used strongly ordered mappings to
1056 provide DMA coherent memory. With the advent of ARMv7, mapping
1057 memory with differing types results in unpredictable behaviour,
1058 so on these CPUs, this option is forced on.
1060 Multiple mappings with differing attributes is also unpredictable
1061 on ARMv6 CPUs, but since they do not have aggressive speculative
1062 prefetch, no harm appears to occur.
1064 However, drivers may be missing the necessary barriers for ARMv6,
1065 and therefore turning this on may result in unpredictable driver
1066 behaviour. Therefore, we offer this as an option.
1068 On some of the beefier ARMv7-M machines (with DMA and write
1069 buffers) you likely want this enabled, while those that
1070 didn't need it until now also won't need it in the future.
1072 You are recommended say 'Y' here and debug any affected drivers.
1077 config ARCH_SUPPORTS_BIG_ENDIAN
1080 This option specifies the architecture can support big endian
1083 config DEBUG_ALIGN_RODATA
1084 bool "Make rodata strictly non-executable"
1085 depends on STRICT_KERNEL_RWX
1088 If this is set, rodata will be made explicitly non-executable. This
1089 provides protection on the rare chance that attackers might find and
1090 use ROP gadgets that exist in the rodata section. This adds an
1091 additional section-aligned split of rodata from kernel text so it
1092 can be made explicitly non-executable. This padding may waste memory
1093 space to gain the additional protection.