1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_MMAP_PGPROT
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_ELF_RANDOMIZE
20 select ARCH_HAS_FAST_MULTIPLIER
21 select ARCH_HAS_FORTIFY_SOURCE
22 select ARCH_HAS_GCOV_PROFILE_ALL
23 select ARCH_HAS_GIGANTIC_PAGE
25 select ARCH_HAS_KEEPINITRD
26 select ARCH_HAS_MEMBARRIER_SYNC_CORE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
32 select ARCH_HAS_STRICT_KERNEL_RWX
33 select ARCH_HAS_STRICT_MODULE_RWX
34 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35 select ARCH_HAS_SYNC_DMA_FOR_CPU
36 select ARCH_HAS_SYSCALL_WRAPPER
37 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39 select ARCH_HAVE_NMI_SAFE_CMPXCHG
40 select ARCH_INLINE_READ_LOCK if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
42 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
43 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
46 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
47 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
50 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
51 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
54 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
56 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
60 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
61 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
64 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
65 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
66 select ARCH_KEEP_MEMBLOCK
67 select ARCH_USE_CMPXCHG_LOCKREF
68 select ARCH_USE_QUEUED_RWLOCKS
69 select ARCH_USE_QUEUED_SPINLOCKS
70 select ARCH_SUPPORTS_MEMORY_FAILURE
71 select ARCH_SUPPORTS_ATOMIC_RMW
72 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
73 select ARCH_SUPPORTS_NUMA_BALANCING
74 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
75 select ARCH_WANT_FRAME_POINTERS
76 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
77 select ARCH_HAS_UBSAN_SANITIZE_ALL
81 select AUDIT_ARCH_COMPAT_GENERIC
82 select ARM_GIC_V2M if PCI
84 select ARM_GIC_V3_ITS if PCI
86 select BUILDTIME_EXTABLE_SORT
87 select CLONE_BACKWARDS
89 select CPU_PM if (SUSPEND || CPU_IDLE)
91 select DCACHE_WORD_ACCESS
92 select DMA_DIRECT_REMAP
95 select GENERIC_ALLOCATOR
96 select GENERIC_ARCH_TOPOLOGY
97 select GENERIC_CLOCKEVENTS
98 select GENERIC_CLOCKEVENTS_BROADCAST
99 select GENERIC_CPU_AUTOPROBE
100 select GENERIC_CPU_VULNERABILITIES
101 select GENERIC_EARLY_IOREMAP
102 select GENERIC_IDLE_POLL_SETUP
103 select GENERIC_IRQ_MULTI_HANDLER
104 select GENERIC_IRQ_PROBE
105 select GENERIC_IRQ_SHOW
106 select GENERIC_IRQ_SHOW_LEVEL
107 select GENERIC_PCI_IOMAP
108 select GENERIC_SCHED_CLOCK
109 select GENERIC_SMP_IDLE_THREAD
110 select GENERIC_STRNCPY_FROM_USER
111 select GENERIC_STRNLEN_USER
112 select GENERIC_TIME_VSYSCALL
113 select GENERIC_GETTIMEOFDAY
114 select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT && "$(CROSS_COMPILE_COMPAT)" != "")
115 select HANDLE_DOMAIN_IRQ
116 select HARDIRQS_SW_RESEND
118 select HAVE_ACPI_APEI if (ACPI && EFI)
119 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
120 select HAVE_ARCH_AUDITSYSCALL
121 select HAVE_ARCH_BITREVERSE
122 select HAVE_ARCH_HUGE_VMAP
123 select HAVE_ARCH_JUMP_LABEL
124 select HAVE_ARCH_JUMP_LABEL_RELATIVE
125 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
126 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
127 select HAVE_ARCH_KGDB
128 select HAVE_ARCH_MMAP_RND_BITS
129 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
130 select HAVE_ARCH_PREL32_RELOCATIONS
131 select HAVE_ARCH_SECCOMP_FILTER
132 select HAVE_ARCH_STACKLEAK
133 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
134 select HAVE_ARCH_TRACEHOOK
135 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
136 select HAVE_ARCH_VMAP_STACK
137 select HAVE_ARM_SMCCC
139 select HAVE_C_RECORDMCOUNT
140 select HAVE_CMPXCHG_DOUBLE
141 select HAVE_CMPXCHG_LOCAL
142 select HAVE_CONTEXT_TRACKING
143 select HAVE_DEBUG_BUGVERBOSE
144 select HAVE_DEBUG_KMEMLEAK
145 select HAVE_DMA_CONTIGUOUS
146 select HAVE_DYNAMIC_FTRACE
147 select HAVE_EFFICIENT_UNALIGNED_ACCESS
149 select HAVE_FTRACE_MCOUNT_RECORD
150 select HAVE_FUNCTION_TRACER
151 select HAVE_FUNCTION_GRAPH_TRACER
152 select HAVE_GCC_PLUGINS
153 select HAVE_HW_BREAKPOINT if PERF_EVENTS
154 select HAVE_IRQ_TIME_ACCOUNTING
155 select HAVE_MEMBLOCK_NODE_MAP if NUMA
157 select HAVE_PATA_PLATFORM
158 select HAVE_PERF_EVENTS
159 select HAVE_PERF_REGS
160 select HAVE_PERF_USER_STACK_DUMP
161 select HAVE_REGS_AND_STACK_ACCESS_API
162 select HAVE_FUNCTION_ARG_ACCESS_API
163 select HAVE_RCU_TABLE_FREE
165 select HAVE_STACKPROTECTOR
166 select HAVE_SYSCALL_TRACEPOINTS
168 select HAVE_KRETPROBES
169 select HAVE_GENERIC_VDSO
170 select IOMMU_DMA if IOMMU_SUPPORT
172 select IRQ_FORCED_THREADING
173 select MODULES_USE_ELF_RELA
174 select NEED_DMA_MAP_STATE
175 select NEED_SG_DMA_LENGTH
177 select OF_EARLY_FLATTREE
178 select PCI_DOMAINS_GENERIC if PCI
179 select PCI_ECAM if (ACPI && PCI)
180 select PCI_SYSCALL if PCI
186 select SYSCTL_EXCEPTION_TRACE
187 select THREAD_INFO_IN_TASK
189 ARM 64-bit (AArch64) Linux support.
197 config ARM64_PAGE_SHIFT
199 default 16 if ARM64_64K_PAGES
200 default 14 if ARM64_16K_PAGES
203 config ARM64_CONT_SHIFT
205 default 5 if ARM64_64K_PAGES
206 default 7 if ARM64_16K_PAGES
209 config ARCH_MMAP_RND_BITS_MIN
210 default 14 if ARM64_64K_PAGES
211 default 16 if ARM64_16K_PAGES
214 # max bits determined by the following formula:
215 # VA_BITS - PAGE_SHIFT - 3
216 config ARCH_MMAP_RND_BITS_MAX
217 default 19 if ARM64_VA_BITS=36
218 default 24 if ARM64_VA_BITS=39
219 default 27 if ARM64_VA_BITS=42
220 default 30 if ARM64_VA_BITS=47
221 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
222 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
223 default 33 if ARM64_VA_BITS=48
224 default 14 if ARM64_64K_PAGES
225 default 16 if ARM64_16K_PAGES
228 config ARCH_MMAP_RND_COMPAT_BITS_MIN
229 default 7 if ARM64_64K_PAGES
230 default 9 if ARM64_16K_PAGES
233 config ARCH_MMAP_RND_COMPAT_BITS_MAX
239 config STACKTRACE_SUPPORT
242 config ILLEGAL_POINTER_VALUE
244 default 0xdead000000000000
246 config LOCKDEP_SUPPORT
249 config TRACE_IRQFLAGS_SUPPORT
256 config GENERIC_BUG_RELATIVE_POINTERS
258 depends on GENERIC_BUG
260 config GENERIC_HWEIGHT
266 config GENERIC_CALIBRATE_DELAY
270 bool "Support DMA32 zone" if EXPERT
273 config ARCH_ENABLE_MEMORY_HOTPLUG
279 config KERNEL_MODE_NEON
282 config FIX_EARLYCON_MEM
285 config PGTABLE_LEVELS
287 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
288 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
289 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
290 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
291 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
292 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
294 config ARCH_SUPPORTS_UPROBES
297 config ARCH_PROC_KCORE_TEXT
300 source "arch/arm64/Kconfig.platforms"
302 menu "Kernel Features"
304 menu "ARM errata workarounds via the alternatives framework"
306 config ARM64_WORKAROUND_CLEAN_CACHE
309 config ARM64_ERRATUM_826319
310 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
312 select ARM64_WORKAROUND_CLEAN_CACHE
314 This option adds an alternative code sequence to work around ARM
315 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
316 AXI master interface and an L2 cache.
318 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
319 and is unable to accept a certain write via this interface, it will
320 not progress on read data presented on the read data channel and the
323 The workaround promotes data cache clean instructions to
324 data cache clean-and-invalidate.
325 Please note that this does not necessarily enable the workaround,
326 as it depends on the alternative framework, which will only patch
327 the kernel if an affected CPU is detected.
331 config ARM64_ERRATUM_827319
332 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
334 select ARM64_WORKAROUND_CLEAN_CACHE
336 This option adds an alternative code sequence to work around ARM
337 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
338 master interface and an L2 cache.
340 Under certain conditions this erratum can cause a clean line eviction
341 to occur at the same time as another transaction to the same address
342 on the AMBA 5 CHI interface, which can cause data corruption if the
343 interconnect reorders the two transactions.
345 The workaround promotes data cache clean instructions to
346 data cache clean-and-invalidate.
347 Please note that this does not necessarily enable the workaround,
348 as it depends on the alternative framework, which will only patch
349 the kernel if an affected CPU is detected.
353 config ARM64_ERRATUM_824069
354 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
356 select ARM64_WORKAROUND_CLEAN_CACHE
358 This option adds an alternative code sequence to work around ARM
359 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
360 to a coherent interconnect.
362 If a Cortex-A53 processor is executing a store or prefetch for
363 write instruction at the same time as a processor in another
364 cluster is executing a cache maintenance operation to the same
365 address, then this erratum might cause a clean cache line to be
366 incorrectly marked as dirty.
368 The workaround promotes data cache clean instructions to
369 data cache clean-and-invalidate.
370 Please note that this option does not necessarily enable the
371 workaround, as it depends on the alternative framework, which will
372 only patch the kernel if an affected CPU is detected.
376 config ARM64_ERRATUM_819472
377 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
379 select ARM64_WORKAROUND_CLEAN_CACHE
381 This option adds an alternative code sequence to work around ARM
382 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
383 present when it is connected to a coherent interconnect.
385 If the processor is executing a load and store exclusive sequence at
386 the same time as a processor in another cluster is executing a cache
387 maintenance operation to the same address, then this erratum might
388 cause data corruption.
390 The workaround promotes data cache clean instructions to
391 data cache clean-and-invalidate.
392 Please note that this does not necessarily enable the workaround,
393 as it depends on the alternative framework, which will only patch
394 the kernel if an affected CPU is detected.
398 config ARM64_ERRATUM_832075
399 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
402 This option adds an alternative code sequence to work around ARM
403 erratum 832075 on Cortex-A57 parts up to r1p2.
405 Affected Cortex-A57 parts might deadlock when exclusive load/store
406 instructions to Write-Back memory are mixed with Device loads.
408 The workaround is to promote device loads to use Load-Acquire
410 Please note that this does not necessarily enable the workaround,
411 as it depends on the alternative framework, which will only patch
412 the kernel if an affected CPU is detected.
416 config ARM64_ERRATUM_834220
417 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
421 This option adds an alternative code sequence to work around ARM
422 erratum 834220 on Cortex-A57 parts up to r1p2.
424 Affected Cortex-A57 parts might report a Stage 2 translation
425 fault as the result of a Stage 1 fault for load crossing a
426 page boundary when there is a permission or device memory
427 alignment fault at Stage 1 and a translation fault at Stage 2.
429 The workaround is to verify that the Stage 1 translation
430 doesn't generate a fault before handling the Stage 2 fault.
431 Please note that this does not necessarily enable the workaround,
432 as it depends on the alternative framework, which will only patch
433 the kernel if an affected CPU is detected.
437 config ARM64_ERRATUM_845719
438 bool "Cortex-A53: 845719: a load might read incorrect data"
442 This option adds an alternative code sequence to work around ARM
443 erratum 845719 on Cortex-A53 parts up to r0p4.
445 When running a compat (AArch32) userspace on an affected Cortex-A53
446 part, a load at EL0 from a virtual address that matches the bottom 32
447 bits of the virtual address used by a recent load at (AArch64) EL1
448 might return incorrect data.
450 The workaround is to write the contextidr_el1 register on exception
451 return to a 32-bit task.
452 Please note that this does not necessarily enable the workaround,
453 as it depends on the alternative framework, which will only patch
454 the kernel if an affected CPU is detected.
458 config ARM64_ERRATUM_843419
459 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
461 select ARM64_MODULE_PLTS if MODULES
463 This option links the kernel with '--fix-cortex-a53-843419' and
464 enables PLT support to replace certain ADRP instructions, which can
465 cause subsequent memory accesses to use an incorrect address on
466 Cortex-A53 parts up to r0p4.
470 config ARM64_ERRATUM_1024718
471 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
474 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
476 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
477 update of the hardware dirty bit when the DBM/AP bits are updated
478 without a break-before-make. The workaround is to disable the usage
479 of hardware DBM locally on the affected cores. CPUs not affected by
480 this erratum will continue to use the feature.
484 config ARM64_ERRATUM_1418040
485 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
489 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
490 errata 1188873 and 1418040.
492 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
493 cause register corruption when accessing the timer registers
494 from AArch32 userspace.
498 config ARM64_ERRATUM_1165522
499 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
502 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
504 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
505 corrupted TLBs by speculating an AT instruction during a guest
510 config ARM64_ERRATUM_1286807
511 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
513 select ARM64_WORKAROUND_REPEAT_TLBI
515 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
517 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
518 address for a cacheable mapping of a location is being
519 accessed by a core while another core is remapping the virtual
520 address to a new physical page using the recommended
521 break-before-make sequence, then under very rare circumstances
522 TLBI+DSB completes before a read using the translation being
523 invalidated has been observed by other observers. The
524 workaround repeats the TLBI+DSB operation.
528 config ARM64_ERRATUM_1463225
529 bool "Cortex-A76: Software Step might prevent interrupt recognition"
532 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
534 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
535 of a system call instruction (SVC) can prevent recognition of
536 subsequent interrupts when software stepping is disabled in the
537 exception handler of the system call and either kernel debugging
538 is enabled or VHE is in use.
540 Work around the erratum by triggering a dummy step exception
541 when handling a system call from a task that is being stepped
542 in a VHE configuration of the kernel.
546 config CAVIUM_ERRATUM_22375
547 bool "Cavium erratum 22375, 24313"
550 Enable workaround for errata 22375 and 24313.
552 This implements two gicv3-its errata workarounds for ThunderX. Both
553 with a small impact affecting only ITS table allocation.
555 erratum 22375: only alloc 8MB table size
556 erratum 24313: ignore memory access type
558 The fixes are in ITS initialization and basically ignore memory access
559 type and table size provided by the TYPER and BASER registers.
563 config CAVIUM_ERRATUM_23144
564 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
568 ITS SYNC command hang for cross node io and collections/cpu mapping.
572 config CAVIUM_ERRATUM_23154
573 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
576 The gicv3 of ThunderX requires a modified version for
577 reading the IAR status to ensure data synchronization
578 (access to icc_iar1_el1 is not sync'ed before and after).
582 config CAVIUM_ERRATUM_27456
583 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
586 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
587 instructions may cause the icache to become corrupted if it
588 contains data for a non-current ASID. The fix is to
589 invalidate the icache when changing the mm context.
593 config CAVIUM_ERRATUM_30115
594 bool "Cavium erratum 30115: Guest may disable interrupts in host"
597 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
598 1.2, and T83 Pass 1.0, KVM guest execution may disable
599 interrupts in host. Trapping both GICv3 group-0 and group-1
600 accesses sidesteps the issue.
604 config CAVIUM_TX2_ERRATUM_219
605 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
608 On Cavium ThunderX2, a load, store or prefetch instruction between a
609 TTBR update and the corresponding context synchronizing operation can
610 cause a spurious Data Abort to be delivered to any hardware thread in
613 Work around the issue by avoiding the problematic code sequence and
614 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
615 trap handler performs the corresponding register access, skips the
616 instruction and ensures context synchronization by virtue of the
621 config QCOM_FALKOR_ERRATUM_1003
622 bool "Falkor E1003: Incorrect translation due to ASID change"
625 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
626 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
627 in TTBR1_EL1, this situation only occurs in the entry trampoline and
628 then only for entries in the walk cache, since the leaf translation
629 is unchanged. Work around the erratum by invalidating the walk cache
630 entries for the trampoline before entering the kernel proper.
632 config ARM64_WORKAROUND_REPEAT_TLBI
635 config QCOM_FALKOR_ERRATUM_1009
636 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
638 select ARM64_WORKAROUND_REPEAT_TLBI
640 On Falkor v1, the CPU may prematurely complete a DSB following a
641 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
642 one more time to fix the issue.
646 config QCOM_QDF2400_ERRATUM_0065
647 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
650 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
651 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
652 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
656 config SOCIONEXT_SYNQUACER_PREITS
657 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
660 Socionext Synquacer SoCs implement a separate h/w block to generate
661 MSI doorbell writes with non-zero values for the device ID.
665 config HISILICON_ERRATUM_161600802
666 bool "Hip07 161600802: Erroneous redistributor VLPI base"
669 The HiSilicon Hip07 SoC uses the wrong redistributor base
670 when issued ITS commands such as VMOVP and VMAPP, and requires
671 a 128kB offset to be applied to the target address in this commands.
675 config QCOM_FALKOR_ERRATUM_E1041
676 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
679 Falkor CPU may speculatively fetch instructions from an improper
680 memory location when MMU translation is changed from SCTLR_ELn[M]=1
681 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
685 config FUJITSU_ERRATUM_010001
686 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
689 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
690 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
691 accesses may cause undefined fault (Data abort, DFSC=0b111111).
692 This fault occurs under a specific hardware condition when a
693 load/store instruction performs an address translation using:
694 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
695 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
696 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
697 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
699 The workaround is to ensure these bits are clear in TCR_ELx.
700 The workaround only affects the Fujitsu-A64FX.
709 default ARM64_4K_PAGES
711 Page size (translation granule) configuration.
713 config ARM64_4K_PAGES
716 This feature enables 4KB pages support.
718 config ARM64_16K_PAGES
721 The system will use 16KB pages support. AArch32 emulation
722 requires applications compiled with 16K (or a multiple of 16K)
725 config ARM64_64K_PAGES
728 This feature enables 64KB pages support (4KB by default)
729 allowing only two levels of page tables and faster TLB
730 look-up. AArch32 emulation requires applications compiled
731 with 64K aligned segments.
736 prompt "Virtual address space size"
737 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
738 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
739 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
741 Allows choosing one of multiple possible virtual address
742 space sizes. The level of translation table is determined by
743 a combination of page size and virtual address space size.
745 config ARM64_VA_BITS_36
746 bool "36-bit" if EXPERT
747 depends on ARM64_16K_PAGES
749 config ARM64_VA_BITS_39
751 depends on ARM64_4K_PAGES
753 config ARM64_VA_BITS_42
755 depends on ARM64_64K_PAGES
757 config ARM64_VA_BITS_47
759 depends on ARM64_16K_PAGES
761 config ARM64_VA_BITS_48
764 config ARM64_USER_VA_BITS_52
766 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
768 Enable 52-bit virtual addressing for userspace when explicitly
769 requested via a hint to mmap(). The kernel will continue to
770 use 48-bit virtual addresses for its own mappings.
772 NOTE: Enabling 52-bit virtual addressing in conjunction with
773 ARMv8.3 Pointer Authentication will result in the PAC being
774 reduced from 7 bits to 3 bits, which may have a significant
775 impact on its susceptibility to brute-force attacks.
777 If unsure, select 48-bit virtual addressing instead.
781 config ARM64_FORCE_52BIT
782 bool "Force 52-bit virtual addresses for userspace"
783 depends on ARM64_USER_VA_BITS_52 && EXPERT
785 For systems with 52-bit userspace VAs enabled, the kernel will attempt
786 to maintain compatibility with older software by providing 48-bit VAs
787 unless a hint is supplied to mmap.
789 This configuration option disables the 48-bit compatibility logic, and
790 forces all userspace addresses to be 52-bit on HW that supports it. One
791 should only enable this configuration option for stress testing userspace
792 memory management code. If unsure say N here.
796 default 36 if ARM64_VA_BITS_36
797 default 39 if ARM64_VA_BITS_39
798 default 42 if ARM64_VA_BITS_42
799 default 47 if ARM64_VA_BITS_47
800 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
803 prompt "Physical address space size"
804 default ARM64_PA_BITS_48
806 Choose the maximum physical address range that the kernel will
809 config ARM64_PA_BITS_48
812 config ARM64_PA_BITS_52
813 bool "52-bit (ARMv8.2)"
814 depends on ARM64_64K_PAGES
815 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
817 Enable support for a 52-bit physical address space, introduced as
818 part of the ARMv8.2-LPA extension.
820 With this enabled, the kernel will also continue to work on CPUs that
821 do not support ARMv8.2-LPA, but with some added memory overhead (and
822 minor performance overhead).
828 default 48 if ARM64_PA_BITS_48
829 default 52 if ARM64_PA_BITS_52
831 config CPU_BIG_ENDIAN
832 bool "Build big-endian kernel"
834 Say Y if you plan on running a kernel in big-endian mode.
837 bool "Multi-core scheduler support"
839 Multi-core scheduler support improves the CPU scheduler's decision
840 making when dealing with multi-core CPU chips at a cost of slightly
841 increased overhead in some places. If unsure say N here.
844 bool "SMT scheduler support"
846 Improves the CPU scheduler's decision making when dealing with
847 MultiThreading at a cost of slightly increased overhead in some
848 places. If unsure say N here.
851 int "Maximum number of CPUs (2-4096)"
856 bool "Support for hot-pluggable CPUs"
857 select GENERIC_IRQ_MIGRATION
859 Say Y here to experiment with turning CPUs off and on. CPUs
860 can be controlled through /sys/devices/system/cpu.
862 # Common NUMA Features
864 bool "Numa Memory Allocation and Scheduler Support"
865 select ACPI_NUMA if ACPI
868 Enable NUMA (Non Uniform Memory Access) support.
870 The kernel will try to allocate memory used by a CPU on the
871 local memory of the CPU and add some more
872 NUMA awareness to the kernel.
875 int "Maximum NUMA Nodes (as a power of 2)"
878 depends on NEED_MULTIPLE_NODES
880 Specify the maximum number of NUMA Nodes available on the target
881 system. Increases memory reserved to accommodate various tables.
883 config USE_PERCPU_NUMA_NODE_ID
887 config HAVE_SETUP_PER_CPU_AREA
891 config NEED_PER_CPU_EMBED_FIRST_CHUNK
898 source "kernel/Kconfig.hz"
900 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
903 config ARCH_SPARSEMEM_ENABLE
905 select SPARSEMEM_VMEMMAP_ENABLE
907 config ARCH_SPARSEMEM_DEFAULT
908 def_bool ARCH_SPARSEMEM_ENABLE
910 config ARCH_SELECT_MEMORY_MODEL
911 def_bool ARCH_SPARSEMEM_ENABLE
913 config ARCH_FLATMEM_ENABLE
916 config HAVE_ARCH_PFN_VALID
919 config HW_PERF_EVENTS
923 config SYS_SUPPORTS_HUGETLBFS
926 config ARCH_WANT_HUGE_PMD_SHARE
928 config ARCH_HAS_CACHE_LINE_SIZE
931 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
932 def_bool y if PGTABLE_LEVELS > 2
935 bool "Enable seccomp to safely compute untrusted bytecode"
937 This kernel feature is useful for number crunching applications
938 that may need to compute untrusted bytecode during their
939 execution. By using pipes or other transports made available to
940 the process as file descriptors supporting the read/write
941 syscalls, it's possible to isolate those applications in
942 their own address space using seccomp. Once seccomp is
943 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
944 and the task is only allowed to execute a few safe syscalls
945 defined by each seccomp mode.
948 bool "Enable paravirtualization code"
950 This changes the kernel so it can modify itself when it is run
951 under a hypervisor, potentially improving performance significantly
952 over full virtualization.
954 config PARAVIRT_TIME_ACCOUNTING
955 bool "Paravirtual steal time accounting"
958 Select this option to enable fine granularity task steal time
959 accounting. Time spent executing other tasks in parallel with
960 the current vCPU is discounted from the vCPU power. To account for
961 that, there can be a small performance impact.
963 If in doubt, say N here.
966 depends on PM_SLEEP_SMP
968 bool "kexec system call"
970 kexec is a system call that implements the ability to shutdown your
971 current kernel, and to start another kernel. It is like a reboot
972 but it is independent of the system firmware. And like a reboot
973 you can start any kernel with it, not just Linux.
976 bool "kexec file based system call"
979 This is new version of kexec system call. This system call is
980 file based and takes file descriptors as system call argument
981 for kernel and initramfs as opposed to list of segments as
982 accepted by previous system call.
985 bool "Verify kernel signature during kexec_file_load() syscall"
986 depends on KEXEC_FILE
989 This option makes the kexec_file_load() syscall check for a valid
990 signature of the kernel image. The image can still be loaded without
991 a valid signature unless you also enable KEXEC_SIG_FORCE, though if
992 there's a signature that we can check, then it must be valid.
994 In addition to this option, you need to enable signature
995 verification for the corresponding kernel image type being
996 loaded in order for this to work.
998 config KEXEC_SIG_FORCE
999 bool "Require a valid signature in kexec_file_load() syscall"
1000 depends on KEXEC_SIG
1002 This option makes kernel signature verification mandatory for
1003 the kexec_file_load() syscall.
1005 config KEXEC_IMAGE_VERIFY_SIG
1006 bool "Enable Image signature verification support"
1008 depends on KEXEC_SIG
1009 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1011 Enable Image signature verification support.
1013 comment "Support for PE file signature verification disabled"
1014 depends on KEXEC_SIG
1015 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1018 bool "Build kdump crash kernel"
1020 Generate crash dump after being started by kexec. This should
1021 be normally only set in special crash dump kernels which are
1022 loaded in the main kernel with kexec-tools into a specially
1023 reserved region and then later executed after a crash by
1026 For more details see Documentation/admin-guide/kdump/kdump.rst
1033 bool "Xen guest support on ARM64"
1034 depends on ARM64 && OF
1038 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1040 config FORCE_MAX_ZONEORDER
1042 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1043 default "13" if (ARCH_THUNDER && ARM64_4K_PAGES)
1044 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1047 The kernel memory allocator divides physically contiguous memory
1048 blocks into "zones", where each zone is a power of two number of
1049 pages. This option selects the largest power of two that the kernel
1050 keeps in the memory allocator. If you need to allocate very large
1051 blocks of physically contiguous memory, then you may need to
1052 increase this value.
1054 This config option is actually maximum order plus one. For example,
1055 a value of 11 means that the largest free memory block is 2^10 pages.
1057 We make sure that we can allocate upto a HugePage size for each configuration.
1059 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1061 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1062 4M allocations matching the default size used by generic code.
1064 config UNMAP_KERNEL_AT_EL0
1065 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1068 Speculation attacks against some high-performance processors can
1069 be used to bypass MMU permission checks and leak kernel data to
1070 userspace. This can be defended against by unmapping the kernel
1071 when running in userspace, mapping it back in on exception entry
1072 via a trampoline page in the vector table.
1076 config HARDEN_BRANCH_PREDICTOR
1077 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1080 Speculation attacks against some high-performance processors rely on
1081 being able to manipulate the branch predictor for a victim context by
1082 executing aliasing branches in the attacker context. Such attacks
1083 can be partially mitigated against by clearing internal branch
1084 predictor state and limiting the prediction logic in some situations.
1086 This config option will take CPU-specific actions to harden the
1087 branch predictor against aliasing attacks and may rely on specific
1088 instruction sequences or control bits being set by the system
1093 config HARDEN_EL2_VECTORS
1094 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1097 Speculation attacks against some high-performance processors can
1098 be used to leak privileged information such as the vector base
1099 register, resulting in a potential defeat of the EL2 layout
1102 This config option will map the vectors to a fixed location,
1103 independent of the EL2 code mapping, so that revealing VBAR_EL2
1104 to an attacker does not give away any extra information. This
1105 only gets enabled on affected CPUs.
1110 bool "Speculative Store Bypass Disable" if EXPERT
1113 This enables mitigation of the bypassing of previous stores
1114 by speculative loads.
1118 config RODATA_FULL_DEFAULT_ENABLED
1119 bool "Apply r/o permissions of VM areas also to their linear aliases"
1122 Apply read-only attributes of VM areas to the linear alias of
1123 the backing pages as well. This prevents code or read-only data
1124 from being modified (inadvertently or intentionally) via another
1125 mapping of the same memory page. This additional enhancement can
1126 be turned off at runtime by passing rodata=[off|on] (and turned on
1127 with rodata=full if this option is set to 'n')
1129 This requires the linear region to be mapped down to pages,
1130 which may adversely affect performance in some cases.
1132 config ARM64_SW_TTBR0_PAN
1133 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1135 Enabling this option prevents the kernel from accessing
1136 user-space memory directly by pointing TTBR0_EL1 to a reserved
1137 zeroed area and reserved ASID. The user access routines
1138 restore the valid TTBR0_EL1 temporarily.
1141 bool "Kernel support for 32-bit EL0"
1142 depends on ARM64_4K_PAGES || EXPERT
1143 select COMPAT_BINFMT_ELF if BINFMT_ELF
1145 select OLD_SIGSUSPEND3
1146 select COMPAT_OLD_SIGACTION
1148 This option enables support for a 32-bit EL0 running under a 64-bit
1149 kernel at EL1. AArch32-specific components such as system calls,
1150 the user helper functions, VFP support and the ptrace interface are
1151 handled appropriately by the kernel.
1153 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1154 that you will only be able to execute AArch32 binaries that were compiled
1155 with page size aligned segments.
1157 If you want to execute 32-bit userspace applications, say Y.
1161 config KUSER_HELPERS
1162 bool "Enable kuser helpers page for 32 bit applications"
1165 Warning: disabling this option may break 32-bit user programs.
1167 Provide kuser helpers to compat tasks. The kernel provides
1168 helper code to userspace in read only form at a fixed location
1169 to allow userspace to be independent of the CPU type fitted to
1170 the system. This permits binaries to be run on ARMv4 through
1171 to ARMv8 without modification.
1173 See Documentation/arm/kernel_user_helpers.rst for details.
1175 However, the fixed address nature of these helpers can be used
1176 by ROP (return orientated programming) authors when creating
1179 If all of the binaries and libraries which run on your platform
1180 are built specifically for your platform, and make no use of
1181 these helpers, then you can turn this option off to hinder
1182 such exploits. However, in that case, if a binary or library
1183 relying on those helpers is run, it will not function correctly.
1185 Say N here only if you are absolutely certain that you do not
1186 need these helpers; otherwise, the safe option is to say Y.
1189 menuconfig ARMV8_DEPRECATED
1190 bool "Emulate deprecated/obsolete ARMv8 instructions"
1193 Legacy software support may require certain instructions
1194 that have been deprecated or obsoleted in the architecture.
1196 Enable this config to enable selective emulation of these
1203 config SWP_EMULATION
1204 bool "Emulate SWP/SWPB instructions"
1206 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1207 they are always undefined. Say Y here to enable software
1208 emulation of these instructions for userspace using LDXR/STXR.
1210 In some older versions of glibc [<=2.8] SWP is used during futex
1211 trylock() operations with the assumption that the code will not
1212 be preempted. This invalid assumption may be more likely to fail
1213 with SWP emulation enabled, leading to deadlock of the user
1216 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1217 on an external transaction monitoring block called a global
1218 monitor to maintain update atomicity. If your system does not
1219 implement a global monitor, this option can cause programs that
1220 perform SWP operations to uncached memory to deadlock.
1224 config CP15_BARRIER_EMULATION
1225 bool "Emulate CP15 Barrier instructions"
1227 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1228 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1229 strongly recommended to use the ISB, DSB, and DMB
1230 instructions instead.
1232 Say Y here to enable software emulation of these
1233 instructions for AArch32 userspace code. When this option is
1234 enabled, CP15 barrier usage is traced which can help
1235 identify software that needs updating.
1239 config SETEND_EMULATION
1240 bool "Emulate SETEND instruction"
1242 The SETEND instruction alters the data-endianness of the
1243 AArch32 EL0, and is deprecated in ARMv8.
1245 Say Y here to enable software emulation of the instruction
1246 for AArch32 userspace code.
1248 Note: All the cpus on the system must have mixed endian support at EL0
1249 for this feature to be enabled. If a new CPU - which doesn't support mixed
1250 endian - is hotplugged in after this feature has been enabled, there could
1251 be unexpected results in the applications.
1258 menu "ARMv8.1 architectural features"
1260 config ARM64_HW_AFDBM
1261 bool "Support for hardware updates of the Access and Dirty page flags"
1264 The ARMv8.1 architecture extensions introduce support for
1265 hardware updates of the access and dirty information in page
1266 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1267 capable processors, accesses to pages with PTE_AF cleared will
1268 set this bit instead of raising an access flag fault.
1269 Similarly, writes to read-only pages with the DBM bit set will
1270 clear the read-only bit (AP[2]) instead of raising a
1273 Kernels built with this configuration option enabled continue
1274 to work on pre-ARMv8.1 hardware and the performance impact is
1275 minimal. If unsure, say Y.
1278 bool "Enable support for Privileged Access Never (PAN)"
1281 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1282 prevents the kernel or hypervisor from accessing user-space (EL0)
1285 Choosing this option will cause any unprotected (not using
1286 copy_to_user et al) memory access to fail with a permission fault.
1288 The feature is detected at runtime, and will remain as a 'nop'
1289 instruction if the cpu does not implement the feature.
1291 config ARM64_LSE_ATOMICS
1292 bool "Atomic instructions"
1295 As part of the Large System Extensions, ARMv8.1 introduces new
1296 atomic instructions that are designed specifically to scale in
1299 Say Y here to make use of these instructions for the in-kernel
1300 atomic routines. This incurs a small overhead on CPUs that do
1301 not support these instructions and requires the kernel to be
1302 built with binutils >= 2.25 in order for the new instructions
1306 bool "Enable support for Virtualization Host Extensions (VHE)"
1309 Virtualization Host Extensions (VHE) allow the kernel to run
1310 directly at EL2 (instead of EL1) on processors that support
1311 it. This leads to better performance for KVM, as they reduce
1312 the cost of the world switch.
1314 Selecting this option allows the VHE feature to be detected
1315 at runtime, and does not affect processors that do not
1316 implement this feature.
1320 menu "ARMv8.2 architectural features"
1323 bool "Enable support for User Access Override (UAO)"
1326 User Access Override (UAO; part of the ARMv8.2 Extensions)
1327 causes the 'unprivileged' variant of the load/store instructions to
1328 be overridden to be privileged.
1330 This option changes get_user() and friends to use the 'unprivileged'
1331 variant of the load/store instructions. This ensures that user-space
1332 really did have access to the supplied memory. When addr_limit is
1333 set to kernel memory the UAO bit will be set, allowing privileged
1334 access to kernel memory.
1336 Choosing this option will cause copy_to_user() et al to use user-space
1339 The feature is detected at runtime, the kernel will use the
1340 regular load/store instructions if the cpu does not implement the
1344 bool "Enable support for persistent memory"
1345 select ARCH_HAS_PMEM_API
1346 select ARCH_HAS_UACCESS_FLUSHCACHE
1348 Say Y to enable support for the persistent memory API based on the
1349 ARMv8.2 DCPoP feature.
1351 The feature is detected at runtime, and the kernel will use DC CVAC
1352 operations if DC CVAP is not supported (following the behaviour of
1353 DC CVAP itself if the system does not define a point of persistence).
1355 config ARM64_RAS_EXTN
1356 bool "Enable support for RAS CPU Extensions"
1359 CPUs that support the Reliability, Availability and Serviceability
1360 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1361 errors, classify them and report them to software.
1363 On CPUs with these extensions system software can use additional
1364 barriers to determine if faults are pending and read the
1365 classification from a new set of registers.
1367 Selecting this feature will allow the kernel to use these barriers
1368 and access the new registers if the system supports the extension.
1369 Platform RAS features may additionally depend on firmware support.
1372 bool "Enable support for Common Not Private (CNP) translations"
1374 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1376 Common Not Private (CNP) allows translation table entries to
1377 be shared between different PEs in the same inner shareable
1378 domain, so the hardware can use this fact to optimise the
1379 caching of such entries in the TLB.
1381 Selecting this option allows the CNP feature to be detected
1382 at runtime, and does not affect PEs that do not implement
1387 menu "ARMv8.3 architectural features"
1389 config ARM64_PTR_AUTH
1390 bool "Enable support for pointer authentication"
1392 depends on !KVM || ARM64_VHE
1394 Pointer authentication (part of the ARMv8.3 Extensions) provides
1395 instructions for signing and authenticating pointers against secret
1396 keys, which can be used to mitigate Return Oriented Programming (ROP)
1399 This option enables these instructions at EL0 (i.e. for userspace).
1401 Choosing this option will cause the kernel to initialise secret keys
1402 for each process at exec() time, with these keys being
1403 context-switched along with the process.
1405 The feature is detected at runtime. If the feature is not present in
1406 hardware it will not be advertised to userspace/KVM guest nor will it
1407 be enabled. However, KVM guest also require VHE mode and hence
1408 CONFIG_ARM64_VHE=y option to use this feature.
1413 bool "ARM Scalable Vector Extension support"
1415 depends on !KVM || ARM64_VHE
1417 The Scalable Vector Extension (SVE) is an extension to the AArch64
1418 execution state which complements and extends the SIMD functionality
1419 of the base architecture to support much larger vectors and to enable
1420 additional vectorisation opportunities.
1422 To enable use of this extension on CPUs that implement it, say Y.
1424 On CPUs that support the SVE2 extensions, this option will enable
1427 Note that for architectural reasons, firmware _must_ implement SVE
1428 support when running on SVE capable hardware. The required support
1431 * version 1.5 and later of the ARM Trusted Firmware
1432 * the AArch64 boot wrapper since commit 5e1261e08abf
1433 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1435 For other firmware implementations, consult the firmware documentation
1438 If you need the kernel to boot on SVE-capable hardware with broken
1439 firmware, you may need to say N here until you get your firmware
1440 fixed. Otherwise, you may experience firmware panics or lockups when
1441 booting the kernel. If unsure and you are not observing these
1442 symptoms, you should assume that it is safe to say Y.
1444 CPUs that support SVE are architecturally required to support the
1445 Virtualization Host Extensions (VHE), so the kernel makes no
1446 provision for supporting SVE alongside KVM without VHE enabled.
1447 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1448 KVM in the same kernel image.
1450 config ARM64_MODULE_PLTS
1451 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1453 select HAVE_MOD_ARCH_SPECIFIC
1455 Allocate PLTs when loading modules so that jumps and calls whose
1456 targets are too far away for their relative offsets to be encoded
1457 in the instructions themselves can be bounced via veneers in the
1458 module's PLT. This allows modules to be allocated in the generic
1459 vmalloc area after the dedicated module memory area has been
1462 When running with address space randomization (KASLR), the module
1463 region itself may be too far away for ordinary relative jumps and
1464 calls, and so in that case, module PLTs are required and cannot be
1467 Specific errata workaround(s) might also force module PLTs to be
1468 enabled (ARM64_ERRATUM_843419).
1470 config ARM64_PSEUDO_NMI
1471 bool "Support for NMI-like interrupts"
1472 select CONFIG_ARM_GIC_V3
1474 Adds support for mimicking Non-Maskable Interrupts through the use of
1475 GIC interrupt priority. This support requires version 3 or later of
1478 This high priority configuration for interrupts needs to be
1479 explicitly enabled by setting the kernel parameter
1480 "irqchip.gicv3_pseudo_nmi" to 1.
1485 config ARM64_DEBUG_PRIORITY_MASKING
1486 bool "Debug interrupt priority masking"
1488 This adds runtime checks to functions enabling/disabling
1489 interrupts when using priority masking. The additional checks verify
1490 the validity of ICC_PMR_EL1 when calling concerned functions.
1498 This builds the kernel as a Position Independent Executable (PIE),
1499 which retains all relocation metadata required to relocate the
1500 kernel binary at runtime to a different virtual address than the
1501 address it was linked at.
1502 Since AArch64 uses the RELA relocation format, this requires a
1503 relocation pass at runtime even if the kernel is loaded at the
1504 same address it was linked at.
1506 config RANDOMIZE_BASE
1507 bool "Randomize the address of the kernel image"
1508 select ARM64_MODULE_PLTS if MODULES
1511 Randomizes the virtual address at which the kernel image is
1512 loaded, as a security feature that deters exploit attempts
1513 relying on knowledge of the location of kernel internals.
1515 It is the bootloader's job to provide entropy, by passing a
1516 random u64 value in /chosen/kaslr-seed at kernel entry.
1518 When booting via the UEFI stub, it will invoke the firmware's
1519 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1520 to the kernel proper. In addition, it will randomise the physical
1521 location of the kernel Image as well.
1525 config RANDOMIZE_MODULE_REGION_FULL
1526 bool "Randomize the module region over a 4 GB range"
1527 depends on RANDOMIZE_BASE
1530 Randomizes the location of the module region inside a 4 GB window
1531 covering the core kernel. This way, it is less likely for modules
1532 to leak information about the location of core kernel data structures
1533 but it does imply that function calls between modules and the core
1534 kernel will need to be resolved via veneers in the module PLT.
1536 When this option is not set, the module region will be randomized over
1537 a limited range that contains the [_stext, _etext] interval of the
1538 core kernel, so branch relocations are always in range.
1540 config CC_HAVE_STACKPROTECTOR_SYSREG
1541 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1543 config STACKPROTECTOR_PER_TASK
1545 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1551 config ARM64_ACPI_PARKING_PROTOCOL
1552 bool "Enable support for the ARM64 ACPI parking protocol"
1555 Enable support for the ARM64 ACPI parking protocol. If disabled
1556 the kernel will not allow booting through the ARM64 ACPI parking
1557 protocol even if the corresponding data is present in the ACPI
1561 string "Default kernel command string"
1564 Provide a set of default command-line options at build time by
1565 entering them here. As a minimum, you should specify the the
1566 root device (e.g. root=/dev/nfs).
1568 config CMDLINE_FORCE
1569 bool "Always use the default kernel command string"
1571 Always use the default kernel command string, even if the boot
1572 loader passes other arguments to the kernel.
1573 This is useful if you cannot or don't want to change the
1574 command-line options your boot loader passes to the kernel.
1580 bool "UEFI runtime support"
1581 depends on OF && !CPU_BIG_ENDIAN
1582 depends on KERNEL_MODE_NEON
1583 select ARCH_SUPPORTS_ACPI
1586 select EFI_PARAMS_FROM_FDT
1587 select EFI_RUNTIME_WRAPPERS
1592 This option provides support for runtime services provided
1593 by UEFI firmware (such as non-volatile variables, realtime
1594 clock, and platform reset). A UEFI stub is also provided to
1595 allow the kernel to be booted as an EFI application. This
1596 is only useful on systems that have UEFI firmware.
1599 bool "Enable support for SMBIOS (DMI) tables"
1603 This enables SMBIOS/DMI feature for systems.
1605 This option is only useful on systems that have UEFI firmware.
1606 However, even with this option, the resultant kernel should
1607 continue to boot on existing non-UEFI platforms.
1611 config SYSVIPC_COMPAT
1613 depends on COMPAT && SYSVIPC
1615 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1617 depends on HUGETLB_PAGE && MIGRATION
1619 menu "Power management options"
1621 source "kernel/power/Kconfig"
1623 config ARCH_HIBERNATION_POSSIBLE
1627 config ARCH_HIBERNATION_HEADER
1629 depends on HIBERNATION
1631 config ARCH_SUSPEND_POSSIBLE
1636 menu "CPU Power Management"
1638 source "drivers/cpuidle/Kconfig"
1640 source "drivers/cpufreq/Kconfig"
1644 source "drivers/firmware/Kconfig"
1646 source "drivers/acpi/Kconfig"
1648 source "arch/arm64/kvm/Kconfig"
1651 source "arch/arm64/crypto/Kconfig"