arch/arm64/Kconfig

   1 config ARM64
   2         def_bool y
   3         select ACPI_CCA_REQUIRED if ACPI
   4         select ACPI_GENERIC_GSI if ACPI
   5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   6         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   7         select ARCH_HAS_ELF_RANDOMIZE
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_HAS_SG_CHAIN
  10         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  11         select ARCH_USE_CMPXCHG_LOCKREF
  12         select ARCH_SUPPORTS_ATOMIC_RMW
  13         select ARCH_SUPPORTS_NUMA_BALANCING
  14         select ARCH_WANT_OPTIONAL_GPIOLIB
  15         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
  16         select ARCH_WANT_FRAME_POINTERS
  17         select ARM_AMBA
  18         select ARM_ARCH_TIMER
  19         select ARM_GIC
  20         select AUDIT_ARCH_COMPAT_GENERIC
  21         select ARM_GIC_V2M if PCI_MSI
  22         select ARM_GIC_V3
  23         select ARM_GIC_V3_ITS if PCI_MSI
  24         select ARM_PSCI_FW
  25         select BUILDTIME_EXTABLE_SORT
  26         select CLONE_BACKWARDS
  27         select COMMON_CLK
  28         select CPU_PM if (SUSPEND || CPU_IDLE)
  29         select DCACHE_WORD_ACCESS
  30         select EDAC_SUPPORT
  31         select FRAME_POINTER
  32         select GENERIC_ALLOCATOR
  33         select GENERIC_CLOCKEVENTS
  34         select GENERIC_CLOCKEVENTS_BROADCAST
  35         select GENERIC_CPU_AUTOPROBE
  36         select GENERIC_EARLY_IOREMAP
  37         select GENERIC_IDLE_POLL_SETUP
  38         select GENERIC_IRQ_PROBE
  39         select GENERIC_IRQ_SHOW
  40         select GENERIC_IRQ_SHOW_LEVEL
  41         select GENERIC_PCI_IOMAP
  42         select GENERIC_SCHED_CLOCK
  43         select GENERIC_SMP_IDLE_THREAD
  44         select GENERIC_STRNCPY_FROM_USER
  45         select GENERIC_STRNLEN_USER
  46         select GENERIC_TIME_VSYSCALL
  47         select HANDLE_DOMAIN_IRQ
  48         select HARDIRQS_SW_RESEND
  49         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
  50         select HAVE_ARCH_AUDITSYSCALL
  51         select HAVE_ARCH_BITREVERSE
  52         select HAVE_ARCH_JUMP_LABEL
  53         select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
  54         select HAVE_ARCH_KGDB
  55         select HAVE_ARCH_SECCOMP_FILTER
  56         select HAVE_ARCH_TRACEHOOK
  57         select HAVE_BPF_JIT
  58         select HAVE_C_RECORDMCOUNT
  59         select HAVE_CC_STACKPROTECTOR
  60         select HAVE_CMPXCHG_DOUBLE
  61         select HAVE_CMPXCHG_LOCAL
  62         select HAVE_DEBUG_BUGVERBOSE
  63         select HAVE_DEBUG_KMEMLEAK
  64         select HAVE_DMA_API_DEBUG
  65         select HAVE_DMA_ATTRS
  66         select HAVE_DMA_CONTIGUOUS
  67         select HAVE_DYNAMIC_FTRACE
  68         select HAVE_EFFICIENT_UNALIGNED_ACCESS
  69         select HAVE_FTRACE_MCOUNT_RECORD
  70         select HAVE_FUNCTION_TRACER
  71         select HAVE_FUNCTION_GRAPH_TRACER
  72         select HAVE_GENERIC_DMA_COHERENT
  73         select HAVE_HW_BREAKPOINT if PERF_EVENTS
  74         select HAVE_MEMBLOCK
  75         select HAVE_MEMBLOCK_NODE_MAP if NUMA
  76         select HAVE_PATA_PLATFORM
  77         select HAVE_PERF_EVENTS
  78         select HAVE_PERF_REGS
  79         select HAVE_PERF_USER_STACK_DUMP
  80         select HAVE_RCU_TABLE_FREE
  81         select HAVE_SYSCALL_TRACEPOINTS
  82         select IOMMU_DMA if IOMMU_SUPPORT
  83         select IRQ_DOMAIN
  84         select IRQ_FORCED_THREADING
  85         select MODULES_USE_ELF_RELA
  86         select NO_BOOTMEM
  87         select OF
  88         select OF_EARLY_FLATTREE
  89         select OF_RESERVED_MEM
  90         select PERF_USE_VMALLOC
  91         select POWER_RESET
  92         select POWER_SUPPLY
  93         select RTC_LIB
  94         select SPARSE_IRQ
  95         select SYSCTL_EXCEPTION_TRACE
  96         select HAVE_CONTEXT_TRACKING
  97         select OF_NUMA if NUMA && OF
  98         help
  99           ARM 64-bit (AArch64) Linux support.
 100
 101 config 64BIT
 102         def_bool y
 103
 104 config ARCH_PHYS_ADDR_T_64BIT
 105         def_bool y
 106
 107 config MMU
 108         def_bool y
 109
 110 config NO_IOPORT_MAP
 111         def_bool y if !PCI
 112
 113 config STACKTRACE_SUPPORT
 114         def_bool y
 115
 116 config ILLEGAL_POINTER_VALUE
 117         hex
 118         default 0xdead000000000000
 119
 120 config LOCKDEP_SUPPORT
 121         def_bool y
 122
 123 config TRACE_IRQFLAGS_SUPPORT
 124         def_bool y
 125
 126 config RWSEM_XCHGADD_ALGORITHM
 127         def_bool y
 128
 129 config GENERIC_BUG
 130         def_bool y
 131         depends on BUG
 132
 133 config GENERIC_BUG_RELATIVE_POINTERS
 134         def_bool y
 135         depends on GENERIC_BUG
 136
 137 config GENERIC_HWEIGHT
 138         def_bool y
 139
 140 config GENERIC_CSUM
 141         def_bool y
 142
 143 config GENERIC_CALIBRATE_DELAY
 144         def_bool y
 145
 146 config ZONE_DMA
 147         def_bool y
 148
 149 config HAVE_GENERIC_RCU_GUP
 150         def_bool y
 151
 152 config ARCH_DMA_ADDR_T_64BIT
 153         def_bool y
 154
 155 config NEED_DMA_MAP_STATE
 156         def_bool y
 157
 158 config NEED_SG_DMA_LENGTH
 159         def_bool y
 160
 161 config SMP
 162         def_bool y
 163
 164 config SWIOTLB
 165         def_bool y
 166
 167 config IOMMU_HELPER
 168         def_bool SWIOTLB
 169
 170 config KERNEL_MODE_NEON
 171         def_bool y
 172
 173 config FIX_EARLYCON_MEM
 174         def_bool y
 175
 176 config PGTABLE_LEVELS
 177         int
 178         default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 179         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 180         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 181         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 182         default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 183         default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 184
 185 source "init/Kconfig"
 186
 187 source "kernel/Kconfig.freezer"
 188
 189 source "arch/arm64/Kconfig.platforms"
 190
 191 menu "Bus support"
 192
 193 config PCI
 194         bool "PCI support"
 195         help
 196           This feature enables support for PCI bus system. If you say Y
 197           here, the kernel will include drivers and infrastructure code
 198           to support PCI bus devices.
 199
 200 config PCI_DOMAINS
 201         def_bool PCI
 202
 203 config PCI_DOMAINS_GENERIC
 204         def_bool PCI
 205
 206 config PCI_SYSCALL
 207         def_bool PCI
 208
 209 source "drivers/pci/Kconfig"
 210 source "drivers/pci/pcie/Kconfig"
 211 source "drivers/pci/hotplug/Kconfig"
 212
 213 endmenu
 214
 215 menu "Kernel Features"
 216
 217 menu "ARM errata workarounds via the alternatives framework"
 218
 219 config ARM64_ERRATUM_826319
 220         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 221         default y
 222         help
 223           This option adds an alternative code sequence to work around ARM
 224           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 225           AXI master interface and an L2 cache.
 226
 227           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 228           and is unable to accept a certain write via this interface, it will
 229           not progress on read data presented on the read data channel and the
 230           system can deadlock.
 231
 232           The workaround promotes data cache clean instructions to
 233           data cache clean-and-invalidate.
 234           Please note that this does not necessarily enable the workaround,
 235           as it depends on the alternative framework, which will only patch
 236           the kernel if an affected CPU is detected.
 237
 238           If unsure, say Y.
 239
 240 config ARM64_ERRATUM_827319
 241         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 242         default y
 243         help
 244           This option adds an alternative code sequence to work around ARM
 245           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 246           master interface and an L2 cache.
 247
 248           Under certain conditions this erratum can cause a clean line eviction
 249           to occur at the same time as another transaction to the same address
 250           on the AMBA 5 CHI interface, which can cause data corruption if the
 251           interconnect reorders the two transactions.
 252
 253           The workaround promotes data cache clean instructions to
 254           data cache clean-and-invalidate.
 255           Please note that this does not necessarily enable the workaround,
 256           as it depends on the alternative framework, which will only patch
 257           the kernel if an affected CPU is detected.
 258
 259           If unsure, say Y.
 260
 261 config ARM64_ERRATUM_824069
 262         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 263         default y
 264         help
 265           This option adds an alternative code sequence to work around ARM
 266           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 267           to a coherent interconnect.
 268
 269           If a Cortex-A53 processor is executing a store or prefetch for
 270           write instruction at the same time as a processor in another
 271           cluster is executing a cache maintenance operation to the same
 272           address, then this erratum might cause a clean cache line to be
 273           incorrectly marked as dirty.
 274
 275           The workaround promotes data cache clean instructions to
 276           data cache clean-and-invalidate.
 277           Please note that this option does not necessarily enable the
 278           workaround, as it depends on the alternative framework, which will
 279           only patch the kernel if an affected CPU is detected.
 280
 281           If unsure, say Y.
 282
 283 config ARM64_ERRATUM_819472
 284         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 285         default y
 286         help
 287           This option adds an alternative code sequence to work around ARM
 288           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 289           present when it is connected to a coherent interconnect.
 290
 291           If the processor is executing a load and store exclusive sequence at
 292           the same time as a processor in another cluster is executing a cache
 293           maintenance operation to the same address, then this erratum might
 294           cause data corruption.
 295
 296           The workaround promotes data cache clean instructions to
 297           data cache clean-and-invalidate.
 298           Please note that this does not necessarily enable the workaround,
 299           as it depends on the alternative framework, which will only patch
 300           the kernel if an affected CPU is detected.
 301
 302           If unsure, say Y.
 303
 304 config ARM64_ERRATUM_832075
 305         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 306         default y
 307         help
 308           This option adds an alternative code sequence to work around ARM
 309           erratum 832075 on Cortex-A57 parts up to r1p2.
 310
 311           Affected Cortex-A57 parts might deadlock when exclusive load/store
 312           instructions to Write-Back memory are mixed with Device loads.
 313
 314           The workaround is to promote device loads to use Load-Acquire
 315           semantics.
 316           Please note that this does not necessarily enable the workaround,
 317           as it depends on the alternative framework, which will only patch
 318           the kernel if an affected CPU is detected.
 319
 320           If unsure, say Y.
 321
 322 config ARM64_ERRATUM_834220
 323         bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 324         depends on KVM
 325         default y
 326         help
 327           This option adds an alternative code sequence to work around ARM
 328           erratum 834220 on Cortex-A57 parts up to r1p2.
 329
 330           Affected Cortex-A57 parts might report a Stage 2 translation
 331           fault as the result of a Stage 1 fault for load crossing a
 332           page boundary when there is a permission or device memory
 333           alignment fault at Stage 1 and a translation fault at Stage 2.
 334
 335           The workaround is to verify that the Stage 1 translation
 336           doesn't generate a fault before handling the Stage 2 fault.
 337           Please note that this does not necessarily enable the workaround,
 338           as it depends on the alternative framework, which will only patch
 339           the kernel if an affected CPU is detected.
 340
 341           If unsure, say Y.
 342
 343 config ARM64_ERRATUM_845719
 344         bool "Cortex-A53: 845719: a load might read incorrect data"
 345         depends on COMPAT
 346         default y
 347         help
 348           This option adds an alternative code sequence to work around ARM
 349           erratum 845719 on Cortex-A53 parts up to r0p4.
 350
 351           When running a compat (AArch32) userspace on an affected Cortex-A53
 352           part, a load at EL0 from a virtual address that matches the bottom 32
 353           bits of the virtual address used by a recent load at (AArch64) EL1
 354           might return incorrect data.
 355
 356           The workaround is to write the contextidr_el1 register on exception
 357           return to a 32-bit task.
 358           Please note that this does not necessarily enable the workaround,
 359           as it depends on the alternative framework, which will only patch
 360           the kernel if an affected CPU is detected.
 361
 362           If unsure, say Y.
 363
 364 config ARM64_ERRATUM_843419
 365         bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 366         depends on MODULES
 367         default y
 368         help
 369           This option builds kernel modules using the large memory model in
 370           order to avoid the use of the ADRP instruction, which can cause
 371           a subsequent memory access to use an incorrect address on Cortex-A53
 372           parts up to r0p4.
 373
 374           Note that the kernel itself must be linked with a version of ld
 375           which fixes potentially affected ADRP instructions through the
 376           use of veneers.
 377
 378           If unsure, say Y.
 379
 380 config CAVIUM_ERRATUM_22375
 381         bool "Cavium erratum 22375, 24313"
 382         default y
 383         help
 384           Enable workaround for erratum 22375, 24313.
 385
 386           This implements two gicv3-its errata workarounds for ThunderX. Both
 387           with small impact affecting only ITS table allocation.
 388
 389             erratum 22375: only alloc 8MB table size
 390             erratum 24313: ignore memory access type
 391
 392           The fixes are in ITS initialization and basically ignore memory access
 393           type and table size provided by the TYPER and BASER registers.
 394
 395           If unsure, say Y.
 396
 397 config CAVIUM_ERRATUM_23144
 398         bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
 399         depends on NUMA
 400         default y
 401         help
 402           ITS SYNC command hang for cross node io and collections/cpu mapping.
 403
 404           If unsure, say Y.
 405
 406 config CAVIUM_ERRATUM_23154
 407         bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 408         default y
 409         help
 410           The gicv3 of ThunderX requires a modified version for
 411           reading the IAR status to ensure data synchronization
 412           (access to icc_iar1_el1 is not sync'ed before and after).
 413
 414           If unsure, say Y.
 415
 416 config CAVIUM_ERRATUM_27456
 417         bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 418         default y
 419         help
 420           On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
 421           instructions may cause the icache to become corrupted if it
 422           contains data for a non-current ASID.  The fix is to
 423           invalidate the icache when changing the mm context.
 424
 425           If unsure, say Y.
 426
 427 endmenu
 428
 429
 430 choice
 431         prompt "Page size"
 432         default ARM64_4K_PAGES
 433         help
 434           Page size (translation granule) configuration.
 435
 436 config ARM64_4K_PAGES
 437         bool "4KB"
 438         help
 439           This feature enables 4KB pages support.
 440
 441 config ARM64_16K_PAGES
 442         bool "16KB"
 443         help
 444           The system will use 16KB pages support. AArch32 emulation
 445           requires applications compiled with 16K (or a multiple of 16K)
 446           aligned segments.
 447
 448 config ARM64_64K_PAGES
 449         bool "64KB"
 450         help
 451           This feature enables 64KB pages support (4KB by default)
 452           allowing only two levels of page tables and faster TLB
 453           look-up. AArch32 emulation requires applications compiled
 454           with 64K aligned segments.
 455
 456 endchoice
 457
 458 choice
 459         prompt "Virtual address space size"
 460         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 461         default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 462         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 463         help
 464           Allows choosing one of multiple possible virtual address
 465           space sizes. The level of translation table is determined by
 466           a combination of page size and virtual address space size.
 467
 468 config ARM64_VA_BITS_36
 469         bool "36-bit" if EXPERT
 470         depends on ARM64_16K_PAGES
 471
 472 config ARM64_VA_BITS_39
 473         bool "39-bit"
 474         depends on ARM64_4K_PAGES
 475
 476 config ARM64_VA_BITS_42
 477         bool "42-bit"
 478         depends on ARM64_64K_PAGES
 479
 480 config ARM64_VA_BITS_47
 481         bool "47-bit"
 482         depends on ARM64_16K_PAGES
 483
 484 config ARM64_VA_BITS_48
 485         bool "48-bit"
 486
 487 endchoice
 488
 489 config ARM64_VA_BITS
 490         int
 491         default 36 if ARM64_VA_BITS_36
 492         default 39 if ARM64_VA_BITS_39
 493         default 42 if ARM64_VA_BITS_42
 494         default 47 if ARM64_VA_BITS_47
 495         default 48 if ARM64_VA_BITS_48
 496
 497 config CPU_BIG_ENDIAN
 498        bool "Build big-endian kernel"
 499        help
 500          Say Y if you plan on running a kernel in big-endian mode.
 501
 502 config SCHED_MC
 503         bool "Multi-core scheduler support"
 504         help
 505           Multi-core scheduler support improves the CPU scheduler's decision
 506           making when dealing with multi-core CPU chips at a cost of slightly
 507           increased overhead in some places. If unsure say N here.
 508
 509 config SCHED_SMT
 510         bool "SMT scheduler support"
 511         help
 512           Improves the CPU scheduler's decision making when dealing with
 513           MultiThreading at a cost of slightly increased overhead in some
 514           places. If unsure say N here.
 515
 516 config NR_CPUS
 517         int "Maximum number of CPUs (2-4096)"
 518         range 2 4096
 519         # These have to remain sorted largest to smallest
 520         default "64"
 521
 522 config HOTPLUG_CPU
 523         bool "Support for hot-pluggable CPUs"
 524         select GENERIC_IRQ_MIGRATION
 525         help
 526           Say Y here to experiment with turning CPUs off and on.  CPUs
 527           can be controlled through /sys/devices/system/cpu.
 528
 529 # Common NUMA Features
 530 config NUMA
 531         bool "Numa Memory Allocation and Scheduler Support"
 532         depends on SMP
 533         help
 534           Enable NUMA (Non Uniform Memory Access) support.
 535
 536           The kernel will try to allocate memory used by a CPU on the
 537           local memory of the CPU and add some more
 538           NUMA awareness to the kernel.
 539
 540 config NODES_SHIFT
 541         int "Maximum NUMA Nodes (as a power of 2)"
 542         range 1 10
 543         default "2"
 544         depends on NEED_MULTIPLE_NODES
 545         help
 546           Specify the maximum number of NUMA Nodes available on the target
 547           system.  Increases memory reserved to accommodate various tables.
 548
 549 config USE_PERCPU_NUMA_NODE_ID
 550         def_bool y
 551         depends on NUMA
 552
 553 source kernel/Kconfig.preempt
 554 source kernel/Kconfig.hz
 555
 556 config ARCH_HAS_HOLES_MEMORYMODEL
 557         def_bool y if SPARSEMEM
 558
 559 config ARCH_SPARSEMEM_ENABLE
 560         def_bool y
 561         select SPARSEMEM_VMEMMAP_ENABLE
 562
 563 config ARCH_SPARSEMEM_DEFAULT
 564         def_bool ARCH_SPARSEMEM_ENABLE
 565
 566 config ARCH_SELECT_MEMORY_MODEL
 567         def_bool ARCH_SPARSEMEM_ENABLE
 568
 569 config HAVE_ARCH_PFN_VALID
 570         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 571
 572 config HW_PERF_EVENTS
 573         def_bool y
 574         depends on ARM_PMU
 575
 576 config SYS_SUPPORTS_HUGETLBFS
 577         def_bool y
 578
 579 config ARCH_WANT_GENERAL_HUGETLB
 580         def_bool y
 581
 582 config ARCH_WANT_HUGE_PMD_SHARE
 583         def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
 584
 585 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 586         def_bool y
 587
 588 config ARCH_HAS_CACHE_LINE_SIZE
 589         def_bool y
 590
 591 source "mm/Kconfig"
 592
 593 config SECCOMP
 594         bool "Enable seccomp to safely compute untrusted bytecode"
 595         ---help---
 596           This kernel feature is useful for number crunching applications
 597           that may need to compute untrusted bytecode during their
 598           execution. By using pipes or other transports made available to
 599           the process as file descriptors supporting the read/write
 600           syscalls, it's possible to isolate those applications in
 601           their own address space using seccomp. Once seccomp is
 602           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 603           and the task is only allowed to execute a few safe syscalls
 604           defined by each seccomp mode.
 605
 606 config XEN_DOM0
 607         def_bool y
 608         depends on XEN
 609
 610 config XEN
 611         bool "Xen guest support on ARM64"
 612         depends on ARM64 && OF
 613         select SWIOTLB_XEN
 614         help
 615           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
 616
 617 config FORCE_MAX_ZONEORDER
 618         int
 619         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
 620         default "13" if (ARCH_THUNDER && ARM64_4K_PAGES)
 621         default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
 622         default "11"
 623         help
 624           The kernel memory allocator divides physically contiguous memory
 625           blocks into "zones", where each zone is a power of two number of
 626           pages.  This option selects the largest power of two that the kernel
 627           keeps in the memory allocator.  If you need to allocate very large
 628           blocks of physically contiguous memory, then you may need to
 629           increase this value.
 630
 631           This config option is actually maximum order plus one. For example,
 632           a value of 11 means that the largest free memory block is 2^10 pages.
 633
 634           We make sure that we can allocate upto a HugePage size for each configuration.
 635           Hence we have :
 636                 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
 637
 638           However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
 639           4M allocations matching the default size used by generic code.
 640
 641 menuconfig ARMV8_DEPRECATED
 642         bool "Emulate deprecated/obsolete ARMv8 instructions"
 643         depends on COMPAT
 644         help
 645           Legacy software support may require certain instructions
 646           that have been deprecated or obsoleted in the architecture.
 647
 648           Enable this config to enable selective emulation of these
 649           features.
 650
 651           If unsure, say Y
 652
 653 if ARMV8_DEPRECATED
 654
 655 config SWP_EMULATION
 656         bool "Emulate SWP/SWPB instructions"
 657         help
 658           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
 659           they are always undefined. Say Y here to enable software
 660           emulation of these instructions for userspace using LDXR/STXR.
 661
 662           In some older versions of glibc [<=2.8] SWP is used during futex
 663           trylock() operations with the assumption that the code will not
 664           be preempted. This invalid assumption may be more likely to fail
 665           with SWP emulation enabled, leading to deadlock of the user
 666           application.
 667
 668           NOTE: when accessing uncached shared regions, LDXR/STXR rely
 669           on an external transaction monitoring block called a global
 670           monitor to maintain update atomicity. If your system does not
 671           implement a global monitor, this option can cause programs that
 672           perform SWP operations to uncached memory to deadlock.
 673
 674           If unsure, say Y
 675
 676 config CP15_BARRIER_EMULATION
 677         bool "Emulate CP15 Barrier instructions"
 678         help
 679           The CP15 barrier instructions - CP15ISB, CP15DSB, and
 680           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
 681           strongly recommended to use the ISB, DSB, and DMB
 682           instructions instead.
 683
 684           Say Y here to enable software emulation of these
 685           instructions for AArch32 userspace code. When this option is
 686           enabled, CP15 barrier usage is traced which can help
 687           identify software that needs updating.
 688
 689           If unsure, say Y
 690
 691 config SETEND_EMULATION
 692         bool "Emulate SETEND instruction"
 693         help
 694           The SETEND instruction alters the data-endianness of the
 695           AArch32 EL0, and is deprecated in ARMv8.
 696
 697           Say Y here to enable software emulation of the instruction
 698           for AArch32 userspace code.
 699
 700           Note: All the cpus on the system must have mixed endian support at EL0
 701           for this feature to be enabled. If a new CPU - which doesn't support mixed
 702           endian - is hotplugged in after this feature has been enabled, there could
 703           be unexpected results in the applications.
 704
 705           If unsure, say Y
 706 endif
 707
 708 menu "ARMv8.1 architectural features"
 709
 710 config ARM64_HW_AFDBM
 711         bool "Support for hardware updates of the Access and Dirty page flags"
 712         default y
 713         help
 714           The ARMv8.1 architecture extensions introduce support for
 715           hardware updates of the access and dirty information in page
 716           table entries. When enabled in TCR_EL1 (HA and HD bits) on
 717           capable processors, accesses to pages with PTE_AF cleared will
 718           set this bit instead of raising an access flag fault.
 719           Similarly, writes to read-only pages with the DBM bit set will
 720           clear the read-only bit (AP[2]) instead of raising a
 721           permission fault.
 722
 723           Kernels built with this configuration option enabled continue
 724           to work on pre-ARMv8.1 hardware and the performance impact is
 725           minimal. If unsure, say Y.
 726
 727 config ARM64_PAN
 728         bool "Enable support for Privileged Access Never (PAN)"
 729         default y
 730         help
 731          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
 732          prevents the kernel or hypervisor from accessing user-space (EL0)
 733          memory directly.
 734
 735          Choosing this option will cause any unprotected (not using
 736          copy_to_user et al) memory access to fail with a permission fault.
 737
 738          The feature is detected at runtime, and will remain as a 'nop'
 739          instruction if the cpu does not implement the feature.
 740
 741 config ARM64_LSE_ATOMICS
 742         bool "Atomic instructions"
 743         help
 744           As part of the Large System Extensions, ARMv8.1 introduces new
 745           atomic instructions that are designed specifically to scale in
 746           very large systems.
 747
 748           Say Y here to make use of these instructions for the in-kernel
 749           atomic routines. This incurs a small overhead on CPUs that do
 750           not support these instructions and requires the kernel to be
 751           built with binutils >= 2.25.
 752
 753 endmenu
 754
 755 endmenu
 756
 757 menu "Boot options"
 758
 759 config ARM64_ACPI_PARKING_PROTOCOL
 760         bool "Enable support for the ARM64 ACPI parking protocol"
 761         depends on ACPI
 762         help
 763           Enable support for the ARM64 ACPI parking protocol. If disabled
 764           the kernel will not allow booting through the ARM64 ACPI parking
 765           protocol even if the corresponding data is present in the ACPI
 766           MADT table.
 767
 768 config CMDLINE
 769         string "Default kernel command string"
 770         default ""
 771         help
 772           Provide a set of default command-line options at build time by
 773           entering them here. As a minimum, you should specify the the
 774           root device (e.g. root=/dev/nfs).
 775
 776 config CMDLINE_FORCE
 777         bool "Always use the default kernel command string"
 778         help
 779           Always use the default kernel command string, even if the boot
 780           loader passes other arguments to the kernel.
 781           This is useful if you cannot or don't want to change the
 782           command-line options your boot loader passes to the kernel.
 783
 784 config EFI_STUB
 785         bool
 786
 787 config EFI
 788         bool "UEFI runtime support"
 789         depends on OF && !CPU_BIG_ENDIAN
 790         select LIBFDT
 791         select UCS2_STRING
 792         select EFI_PARAMS_FROM_FDT
 793         select EFI_RUNTIME_WRAPPERS
 794         select EFI_STUB
 795         select EFI_ARMSTUB
 796         default y
 797         help
 798           This option provides support for runtime services provided
 799           by UEFI firmware (such as non-volatile variables, realtime
 800           clock, and platform reset). A UEFI stub is also provided to
 801           allow the kernel to be booted as an EFI application. This
 802           is only useful on systems that have UEFI firmware.
 803
 804 config DMI
 805         bool "Enable support for SMBIOS (DMI) tables"
 806         depends on EFI
 807         default y
 808         help
 809           This enables SMBIOS/DMI feature for systems.
 810
 811           This option is only useful on systems that have UEFI firmware.
 812           However, even with this option, the resultant kernel should
 813           continue to boot on existing non-UEFI platforms.
 814
 815 endmenu
 816
 817 menu "Userspace binary formats"
 818
 819 source "fs/Kconfig.binfmt"
 820
 821 config COMPAT
 822         bool "Kernel support for 32-bit EL0"
 823         depends on ARM64_4K_PAGES || EXPERT
 824         select COMPAT_BINFMT_ELF
 825         select HAVE_UID16
 826         select OLD_SIGSUSPEND3
 827         select COMPAT_OLD_SIGACTION
 828         help
 829           This option enables support for a 32-bit EL0 running under a 64-bit
 830           kernel at EL1. AArch32-specific components such as system calls,
 831           the user helper functions, VFP support and the ptrace interface are
 832           handled appropriately by the kernel.
 833
 834           If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
 835           that you will only be able to execute AArch32 binaries that were compiled
 836           with page size aligned segments.
 837
 838           If you want to execute 32-bit userspace applications, say Y.
 839
 840 config SYSVIPC_COMPAT
 841         def_bool y
 842         depends on COMPAT && SYSVIPC
 843
 844 endmenu
 845
 846 menu "Power management options"
 847
 848 source "kernel/power/Kconfig"
 849
 850 config ARCH_SUSPEND_POSSIBLE
 851         def_bool y
 852
 853 endmenu
 854
 855 menu "CPU Power Management"
 856
 857 source "drivers/cpuidle/Kconfig"
 858
 859 source "drivers/cpufreq/Kconfig"
 860
 861 endmenu
 862
 863 source "net/Kconfig"
 864
 865 source "drivers/Kconfig"
 866
 867 source "ubuntu/Kconfig"
 868
 869 source "drivers/firmware/Kconfig"
 870
 871 source "drivers/acpi/Kconfig"
 872
 873 source "fs/Kconfig"
 874
 875 source "arch/arm64/kvm/Kconfig"
 876
 877 source "arch/arm64/Kconfig.debug"
 878
 879 source "security/Kconfig"
 880
 881 source "crypto/Kconfig"
 882 if CRYPTO
 883 source "arch/arm64/crypto/Kconfig"
 884 endif
 885
 886 source "lib/Kconfig"