2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
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14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
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22 * obtaining a copy of this software and associated documentation
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44 * Device Tree file for Marvell Armada CP110 Master.
51 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
55 config-space@f2000000 {
58 compatible = "simple-bus";
59 interrupt-parent = <&gic>;
60 ranges = <0x0 0x0 0xf2000000 0x2000000>;
62 cpm_ethernet: ethernet@0 {
63 compatible = "marvell,armada-7k-pp22";
64 reg = <0x0 0x100000>, <0x129000 0xb000>;
65 clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
66 clock-names = "pp_clk", "gop_clk", "mg_clk";
71 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
78 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
85 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
92 cpm_mdio: mdio@12a200 {
95 compatible = "marvell,orion-mdio";
96 reg = <0x12a200 0x10>;
99 cpm_syscon0: system-controller@440000 {
100 compatible = "marvell,cp110-system-controller0",
102 reg = <0x440000 0x1000>;
104 core-clock-output-names =
105 "cpm-apll", "cpm-ppv2-core", "cpm-eip",
106 "cpm-core", "cpm-nand-core";
107 gate-clock-output-names =
108 "cpm-audio", "cpm-communit", "cpm-nand",
109 "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
110 "cpm-mg-core", "cpm-xor1", "cpm-xor0",
111 "cpm-gop-dp", "none", "cpm-pcie_x10",
112 "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
113 "cpm-sata", "cpm-sata-usb", "cpm-main",
114 "cpm-sd-mmc-gop", "none", "none",
115 "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
116 "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
119 cpm_rtc: rtc@284000 {
120 compatible = "marvell,armada-8k-rtc";
121 reg = <0x284000 0x20>, <0x284080 0x24>;
122 reg-names = "rtc", "rtc-soc";
123 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
126 cpm_sata0: sata@540000 {
127 compatible = "marvell,armada-8k-ahci",
129 reg = <0x540000 0x30000>;
130 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&cpm_syscon0 1 15>;
135 cpm_usb3_0: usb3@500000 {
136 compatible = "marvell,armada-8k-xhci",
138 reg = <0x500000 0x4000>;
140 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cpm_syscon0 1 22>;
145 cpm_usb3_1: usb3@510000 {
146 compatible = "marvell,armada-8k-xhci",
148 reg = <0x510000 0x4000>;
150 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&cpm_syscon0 1 23>;
155 cpm_xor0: xor@6a0000 {
156 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
157 reg = <0x6a0000 0x1000>,
160 msi-parent = <&gic_v2m0>;
161 clocks = <&cpm_syscon0 1 8>;
164 cpm_xor1: xor@6c0000 {
165 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
166 reg = <0x6c0000 0x1000>,
169 msi-parent = <&gic_v2m0>;
170 clocks = <&cpm_syscon0 1 7>;
173 cpm_spi0: spi@700600 {
174 compatible = "marvell,armada-380-spi";
175 reg = <0x700600 0x50>;
176 #address-cells = <0x1>;
179 clocks = <&cpm_syscon0 1 21>;
183 cpm_spi1: spi@700680 {
184 compatible = "marvell,armada-380-spi";
185 reg = <0x700680 0x50>;
186 #address-cells = <1>;
189 clocks = <&cpm_syscon0 1 21>;
193 cpm_i2c0: i2c@701000 {
194 compatible = "marvell,mv78230-i2c";
195 reg = <0x701000 0x20>;
196 #address-cells = <1>;
198 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cpm_syscon0 1 21>;
203 cpm_i2c1: i2c@701100 {
204 compatible = "marvell,mv78230-i2c";
205 reg = <0x701100 0x20>;
206 #address-cells = <1>;
208 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&cpm_syscon0 1 21>;
213 cpm_trng: trng@760000 {
214 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
215 reg = <0x760000 0x7d>;
216 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cpm_syscon0 1 25>;
221 cpm_sdhci0: sdhci@780000 {
222 compatible = "marvell,armada-cp110-sdhci";
223 reg = <0x780000 0x300>;
224 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
225 clock-names = "core";
226 clocks = <&cpm_syscon0 1 4>;
231 cpm_crypto: crypto@800000 {
232 compatible = "inside-secure,safexcel-eip197";
233 reg = <0x800000 0x200000>;
234 interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
235 | IRQ_TYPE_LEVEL_HIGH)>,
236 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
241 interrupt-names = "mem", "ring0", "ring1",
242 "ring2", "ring3", "eip";
243 clocks = <&cpm_syscon0 1 26>;
248 cpm_pcie0: pcie@f2600000 {
249 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
250 reg = <0 0xf2600000 0 0x10000>,
251 <0 0xf6f00000 0 0x80000>;
252 reg-names = "ctrl", "config";
253 #address-cells = <3>;
255 #interrupt-cells = <1>;
258 msi-parent = <&gic_v2m0>;
260 bus-range = <0 0xff>;
263 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
264 /* non-prefetchable memory */
265 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
266 interrupt-map-mask = <0 0 0 0>;
267 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&cpm_syscon0 1 13>;
274 cpm_pcie1: pcie@f2620000 {
275 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
276 reg = <0 0xf2620000 0 0x10000>,
277 <0 0xf7f00000 0 0x80000>;
278 reg-names = "ctrl", "config";
279 #address-cells = <3>;
281 #interrupt-cells = <1>;
284 msi-parent = <&gic_v2m0>;
286 bus-range = <0 0xff>;
289 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
290 /* non-prefetchable memory */
291 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
292 interrupt-map-mask = <0 0 0 0>;
293 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
294 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&cpm_syscon0 1 11>;
301 cpm_pcie2: pcie@f2640000 {
302 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
303 reg = <0 0xf2640000 0 0x10000>,
304 <0 0xf8f00000 0 0x80000>;
305 reg-names = "ctrl", "config";
306 #address-cells = <3>;
308 #interrupt-cells = <1>;
311 msi-parent = <&gic_v2m0>;
313 bus-range = <0 0xff>;
316 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
317 /* non-prefetchable memory */
318 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
319 interrupt-map-mask = <0 0 0 0>;
320 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
321 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&cpm_syscon0 1 12>;