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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / boot / dts / rockchip / rk3328.dtsi
1 /*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3328-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51
52 / {
53 compatible = "rockchip,rk3328";
54
55 interrupt-parent = <&gic>;
56 #address-cells = <2>;
57 #size-cells = <2>;
58
59 aliases {
60 serial0 = &uart0;
61 serial1 = &uart1;
62 serial2 = &uart2;
63 i2c0 = &i2c0;
64 i2c1 = &i2c1;
65 i2c2 = &i2c2;
66 i2c3 = &i2c3;
67 ethernet0 = &gmac2io;
68 ethernet1 = &gmac2phy;
69 };
70
71 cpus {
72 #address-cells = <2>;
73 #size-cells = <0>;
74
75 cpu0: cpu@0 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a53", "arm,armv8";
78 reg = <0x0 0x0>;
79 clocks = <&cru ARMCLK>;
80 #cooling-cells = <2>;
81 dynamic-power-coefficient = <120>;
82 enable-method = "psci";
83 next-level-cache = <&l2>;
84 operating-points-v2 = <&cpu0_opp_table>;
85 };
86
87 cpu1: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53", "arm,armv8";
90 reg = <0x0 0x1>;
91 clocks = <&cru ARMCLK>;
92 dynamic-power-coefficient = <120>;
93 enable-method = "psci";
94 next-level-cache = <&l2>;
95 operating-points-v2 = <&cpu0_opp_table>;
96 };
97
98 cpu2: cpu@2 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x2>;
102 clocks = <&cru ARMCLK>;
103 dynamic-power-coefficient = <120>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 operating-points-v2 = <&cpu0_opp_table>;
107 };
108
109 cpu3: cpu@3 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a53", "arm,armv8";
112 reg = <0x0 0x3>;
113 clocks = <&cru ARMCLK>;
114 dynamic-power-coefficient = <120>;
115 enable-method = "psci";
116 next-level-cache = <&l2>;
117 operating-points-v2 = <&cpu0_opp_table>;
118 };
119
120 l2: l2-cache0 {
121 compatible = "cache";
122 };
123 };
124
125 cpu0_opp_table: opp_table0 {
126 compatible = "operating-points-v2";
127 opp-shared;
128
129 opp-408000000 {
130 opp-hz = /bits/ 64 <408000000>;
131 opp-microvolt = <950000>;
132 clock-latency-ns = <40000>;
133 opp-suspend;
134 };
135 opp-600000000 {
136 opp-hz = /bits/ 64 <600000000>;
137 opp-microvolt = <950000>;
138 clock-latency-ns = <40000>;
139 };
140 opp-816000000 {
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
143 clock-latency-ns = <40000>;
144 };
145 opp-1008000000 {
146 opp-hz = /bits/ 64 <1008000000>;
147 opp-microvolt = <1100000>;
148 clock-latency-ns = <40000>;
149 };
150 opp-1200000000 {
151 opp-hz = /bits/ 64 <1200000000>;
152 opp-microvolt = <1225000>;
153 clock-latency-ns = <40000>;
154 };
155 opp-1296000000 {
156 opp-hz = /bits/ 64 <1296000000>;
157 opp-microvolt = <1300000>;
158 clock-latency-ns = <40000>;
159 };
160 };
161
162 amba {
163 compatible = "simple-bus";
164 #address-cells = <2>;
165 #size-cells = <2>;
166 ranges;
167
168 dmac: dmac@ff1f0000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0x0 0xff1f0000 0x0 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru ACLK_DMAC>;
174 clock-names = "apb_pclk";
175 #dma-cells = <1>;
176 };
177 };
178
179 arm-pmu {
180 compatible = "arm,cortex-a53-pmu";
181 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
186 };
187
188 psci {
189 compatible = "arm,psci-1.0", "arm,psci-0.2";
190 method = "smc";
191 };
192
193 timer {
194 compatible = "arm,armv8-timer";
195 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
196 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
197 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
199 };
200
201 xin24m: xin24m {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <24000000>;
205 clock-output-names = "xin24m";
206 };
207
208 i2s0: i2s@ff000000 {
209 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
210 reg = <0x0 0xff000000 0x0 0x1000>;
211 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
213 clock-names = "i2s_clk", "i2s_hclk";
214 dmas = <&dmac 11>, <&dmac 12>;
215 dma-names = "tx", "rx";
216 status = "disabled";
217 };
218
219 i2s1: i2s@ff010000 {
220 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
221 reg = <0x0 0xff010000 0x0 0x1000>;
222 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
224 clock-names = "i2s_clk", "i2s_hclk";
225 dmas = <&dmac 14>, <&dmac 15>;
226 dma-names = "tx", "rx";
227 status = "disabled";
228 };
229
230 i2s2: i2s@ff020000 {
231 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
232 reg = <0x0 0xff020000 0x0 0x1000>;
233 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
235 clock-names = "i2s_clk", "i2s_hclk";
236 dmas = <&dmac 0>, <&dmac 1>;
237 dma-names = "tx", "rx";
238 status = "disabled";
239 };
240
241 spdif: spdif@ff030000 {
242 compatible = "rockchip,rk3328-spdif";
243 reg = <0x0 0xff030000 0x0 0x1000>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
246 clock-names = "mclk", "hclk";
247 dmas = <&dmac 10>;
248 dma-names = "tx";
249 pinctrl-names = "default";
250 pinctrl-0 = <&spdifm2_tx>;
251 status = "disabled";
252 };
253
254 pdm: pdm@ff040000 {
255 compatible = "rockchip,pdm";
256 reg = <0x0 0xff040000 0x0 0x1000>;
257 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
258 clock-names = "pdm_clk", "pdm_hclk";
259 dmas = <&dmac 16>;
260 dma-names = "rx";
261 pinctrl-names = "default", "sleep";
262 pinctrl-0 = <&pdmm0_clk
263 &pdmm0_sdi0
264 &pdmm0_sdi1
265 &pdmm0_sdi2
266 &pdmm0_sdi3>;
267 pinctrl-1 = <&pdmm0_clk_sleep
268 &pdmm0_sdi0_sleep
269 &pdmm0_sdi1_sleep
270 &pdmm0_sdi2_sleep
271 &pdmm0_sdi3_sleep>;
272 status = "disabled";
273 };
274
275 grf: syscon@ff100000 {
276 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
277 reg = <0x0 0xff100000 0x0 0x1000>;
278 #address-cells = <1>;
279 #size-cells = <1>;
280
281 io_domains: io-domains {
282 compatible = "rockchip,rk3328-io-voltage-domain";
283 status = "disabled";
284 };
285
286 power: power-controller {
287 compatible = "rockchip,rk3328-power-controller";
288 #power-domain-cells = <1>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291
292 pd_hevc@RK3328_PD_HEVC {
293 reg = <RK3328_PD_HEVC>;
294 };
295 pd_video@RK3328_PD_VIDEO {
296 reg = <RK3328_PD_VIDEO>;
297 };
298 pd_vpu@RK3328_PD_VPU {
299 reg = <RK3328_PD_VPU>;
300 };
301 };
302
303 reboot-mode {
304 compatible = "syscon-reboot-mode";
305 offset = <0x5c8>;
306 mode-normal = <BOOT_NORMAL>;
307 mode-recovery = <BOOT_RECOVERY>;
308 mode-bootloader = <BOOT_FASTBOOT>;
309 mode-loader = <BOOT_BL_DOWNLOAD>;
310 };
311
312 };
313
314 uart0: serial@ff110000 {
315 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff110000 0x0 0x100>;
317 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
319 clock-names = "baudclk", "apb_pclk";
320 dmas = <&dmac 2>, <&dmac 3>;
321 #dma-cells = <2>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
324 reg-io-width = <4>;
325 reg-shift = <2>;
326 status = "disabled";
327 };
328
329 uart1: serial@ff120000 {
330 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
331 reg = <0x0 0xff120000 0x0 0x100>;
332 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
334 clock-names = "baudclk", "apb_pclk";
335 dmas = <&dmac 4>, <&dmac 5>;
336 #dma-cells = <2>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
339 reg-io-width = <4>;
340 reg-shift = <2>;
341 status = "disabled";
342 };
343
344 uart2: serial@ff130000 {
345 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
346 reg = <0x0 0xff130000 0x0 0x100>;
347 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
349 clock-names = "baudclk", "apb_pclk";
350 dmas = <&dmac 6>, <&dmac 7>;
351 #dma-cells = <2>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart2m1_xfer>;
354 reg-io-width = <4>;
355 reg-shift = <2>;
356 status = "disabled";
357 };
358
359 i2c0: i2c@ff150000 {
360 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
361 reg = <0x0 0xff150000 0x0 0x1000>;
362 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
366 clock-names = "i2c", "pclk";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c0_xfer>;
369 status = "disabled";
370 };
371
372 i2c1: i2c@ff160000 {
373 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
374 reg = <0x0 0xff160000 0x0 0x1000>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
377 #size-cells = <0>;
378 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
379 clock-names = "i2c", "pclk";
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c1_xfer>;
382 status = "disabled";
383 };
384
385 i2c2: i2c@ff170000 {
386 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
387 reg = <0x0 0xff170000 0x0 0x1000>;
388 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
390 #size-cells = <0>;
391 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
392 clock-names = "i2c", "pclk";
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c2_xfer>;
395 status = "disabled";
396 };
397
398 i2c3: i2c@ff180000 {
399 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
400 reg = <0x0 0xff180000 0x0 0x1000>;
401 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
405 clock-names = "i2c", "pclk";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c3_xfer>;
408 status = "disabled";
409 };
410
411 spi0: spi@ff190000 {
412 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
413 reg = <0x0 0xff190000 0x0 0x1000>;
414 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
416 #size-cells = <0>;
417 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
418 clock-names = "spiclk", "apb_pclk";
419 dmas = <&dmac 8>, <&dmac 9>;
420 dma-names = "tx", "rx";
421 pinctrl-names = "default";
422 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
423 status = "disabled";
424 };
425
426 wdt: watchdog@ff1a0000 {
427 compatible = "snps,dw-wdt";
428 reg = <0x0 0xff1a0000 0x0 0x100>;
429 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
430 };
431
432 pwm0: pwm@ff1b0000 {
433 compatible = "rockchip,rk3328-pwm";
434 reg = <0x0 0xff1b0000 0x0 0x10>;
435 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
436 clock-names = "pwm", "pclk";
437 pinctrl-names = "default";
438 pinctrl-0 = <&pwm0_pin>;
439 #pwm-cells = <3>;
440 status = "disabled";
441 };
442
443 pwm1: pwm@ff1b0010 {
444 compatible = "rockchip,rk3328-pwm";
445 reg = <0x0 0xff1b0010 0x0 0x10>;
446 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
447 clock-names = "pwm", "pclk";
448 pinctrl-names = "default";
449 pinctrl-0 = <&pwm1_pin>;
450 #pwm-cells = <3>;
451 status = "disabled";
452 };
453
454 pwm2: pwm@ff1b0020 {
455 compatible = "rockchip,rk3328-pwm";
456 reg = <0x0 0xff1b0020 0x0 0x10>;
457 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
458 clock-names = "pwm", "pclk";
459 pinctrl-names = "default";
460 pinctrl-0 = <&pwm2_pin>;
461 #pwm-cells = <3>;
462 status = "disabled";
463 };
464
465 pwm3: pwm@ff1b0030 {
466 compatible = "rockchip,rk3328-pwm";
467 reg = <0x0 0xff1b0030 0x0 0x10>;
468 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
470 clock-names = "pwm", "pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pwmir_pin>;
473 #pwm-cells = <3>;
474 status = "disabled";
475 };
476
477 thermal-zones {
478 soc_thermal: soc-thermal {
479 polling-delay-passive = <20>;
480 polling-delay = <1000>;
481 sustainable-power = <1000>;
482
483 thermal-sensors = <&tsadc 0>;
484
485 trips {
486 threshold: trip-point0 {
487 temperature = <70000>;
488 hysteresis = <2000>;
489 type = "passive";
490 };
491 target: trip-point1 {
492 temperature = <85000>;
493 hysteresis = <2000>;
494 type = "passive";
495 };
496 soc_crit: soc-crit {
497 temperature = <95000>;
498 hysteresis = <2000>;
499 type = "critical";
500 };
501 };
502
503 cooling-maps {
504 map0 {
505 trip = <&target>;
506 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
507 contribution = <4096>;
508 };
509 };
510 };
511
512 };
513
514 tsadc: tsadc@ff250000 {
515 compatible = "rockchip,rk3328-tsadc";
516 reg = <0x0 0xff250000 0x0 0x100>;
517 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
518 assigned-clocks = <&cru SCLK_TSADC>;
519 assigned-clock-rates = <50000>;
520 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
521 clock-names = "tsadc", "apb_pclk";
522 pinctrl-names = "init", "default", "sleep";
523 pinctrl-0 = <&otp_gpio>;
524 pinctrl-1 = <&otp_out>;
525 pinctrl-2 = <&otp_gpio>;
526 resets = <&cru SRST_TSADC>;
527 reset-names = "tsadc-apb";
528 rockchip,grf = <&grf>;
529 rockchip,hw-tshut-temp = <100000>;
530 #thermal-sensor-cells = <1>;
531 status = "disabled";
532 };
533
534 saradc: adc@ff280000 {
535 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
536 reg = <0x0 0xff280000 0x0 0x100>;
537 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
538 #io-channel-cells = <1>;
539 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
540 clock-names = "saradc", "apb_pclk";
541 resets = <&cru SRST_SARADC_P>;
542 reset-names = "saradc-apb";
543 status = "disabled";
544 };
545
546 h265e_mmu: iommu@ff330200 {
547 compatible = "rockchip,iommu";
548 reg = <0x0 0xff330200 0 0x100>;
549 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
550 interrupt-names = "h265e_mmu";
551 #iommu-cells = <0>;
552 status = "disabled";
553 };
554
555 vepu_mmu: iommu@ff340800 {
556 compatible = "rockchip,iommu";
557 reg = <0x0 0xff340800 0x0 0x40>;
558 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-names = "vepu_mmu";
560 #iommu-cells = <0>;
561 status = "disabled";
562 };
563
564 vpu_mmu: iommu@ff350800 {
565 compatible = "rockchip,iommu";
566 reg = <0x0 0xff350800 0x0 0x40>;
567 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
568 interrupt-names = "vpu_mmu";
569 #iommu-cells = <0>;
570 status = "disabled";
571 };
572
573 rkvdec_mmu: iommu@ff360480 {
574 compatible = "rockchip,iommu";
575 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
576 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "rkvdec_mmu";
578 #iommu-cells = <0>;
579 status = "disabled";
580 };
581
582 vop_mmu: iommu@ff373f00 {
583 compatible = "rockchip,iommu";
584 reg = <0x0 0xff373f00 0x0 0x100>;
585 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
586 interrupt-names = "vop_mmu";
587 #iommu-cells = <0>;
588 status = "disabled";
589 };
590
591 cru: clock-controller@ff440000 {
592 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
593 reg = <0x0 0xff440000 0x0 0x1000>;
594 rockchip,grf = <&grf>;
595 #clock-cells = <1>;
596 #reset-cells = <1>;
597 assigned-clocks =
598 /*
599 * CPLL should run at 1200, but that is to high for
600 * the initial dividers of most of its children.
601 * We need set cpll child clk div first,
602 * and then set the cpll frequency.
603 */
604 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
605 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
606 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
607 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
608 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
609 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
610 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
611 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
612 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
613 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
614 <&cru SCLK_WIFI>, <&cru ARMCLK>,
615 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
616 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
617 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
618 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
619 <&cru SCLK_RTC32K>;
620 assigned-clock-parents =
621 <&cru HDMIPHY>, <&cru PLL_APLL>,
622 <&cru PLL_GPLL>, <&xin24m>,
623 <&xin24m>, <&xin24m>;
624 assigned-clock-rates =
625 <0>, <61440000>,
626 <0>, <24000000>,
627 <24000000>, <24000000>,
628 <15000000>, <15000000>,
629 <100000000>, <100000000>,
630 <100000000>, <100000000>,
631 <50000000>, <100000000>,
632 <100000000>, <100000000>,
633 <50000000>, <50000000>,
634 <50000000>, <50000000>,
635 <24000000>, <600000000>,
636 <491520000>, <1200000000>,
637 <150000000>, <75000000>,
638 <75000000>, <150000000>,
639 <75000000>, <75000000>,
640 <32768>;
641 };
642
643 usb2phy_grf: syscon@ff450000 {
644 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
645 "simple-mfd";
646 reg = <0x0 0xff450000 0x0 0x10000>;
647 #address-cells = <1>;
648 #size-cells = <1>;
649
650 u2phy: usb2-phy@100 {
651 compatible = "rockchip,rk3328-usb2phy";
652 reg = <0x100 0x10>;
653 clocks = <&xin24m>;
654 clock-names = "phyclk";
655 clock-output-names = "usb480m_phy";
656 #clock-cells = <0>;
657 assigned-clocks = <&cru USB480M>;
658 assigned-clock-parents = <&u2phy>;
659 status = "disabled";
660
661 u2phy_otg: otg-port {
662 #phy-cells = <0>;
663 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
666 interrupt-names = "otg-bvalid", "otg-id",
667 "linestate";
668 status = "disabled";
669 };
670
671 u2phy_host: host-port {
672 #phy-cells = <0>;
673 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-names = "linestate";
675 status = "disabled";
676 };
677 };
678 };
679
680 sdmmc: dwmmc@ff500000 {
681 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
682 reg = <0x0 0xff500000 0x0 0x4000>;
683 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
685 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
686 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
687 fifo-depth = <0x100>;
688 max-frequency = <150000000>;
689 status = "disabled";
690 };
691
692 sdio: dwmmc@ff510000 {
693 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
694 reg = <0x0 0xff510000 0x0 0x4000>;
695 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
697 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
698 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
699 fifo-depth = <0x100>;
700 max-frequency = <150000000>;
701 status = "disabled";
702 };
703
704 emmc: dwmmc@ff520000 {
705 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
706 reg = <0x0 0xff520000 0x0 0x4000>;
707 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
709 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
710 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
711 fifo-depth = <0x100>;
712 max-frequency = <150000000>;
713 status = "disabled";
714 };
715
716 gmac2io: ethernet@ff540000 {
717 compatible = "rockchip,rk3328-gmac";
718 reg = <0x0 0xff540000 0x0 0x10000>;
719 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
720 interrupt-names = "macirq";
721 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
722 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
723 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
724 <&cru PCLK_MAC2IO>;
725 clock-names = "stmmaceth", "mac_clk_rx",
726 "mac_clk_tx", "clk_mac_ref",
727 "clk_mac_refout", "aclk_mac",
728 "pclk_mac";
729 resets = <&cru SRST_GMAC2IO_A>;
730 reset-names = "stmmaceth";
731 rockchip,grf = <&grf>;
732 status = "disabled";
733 };
734
735 gmac2phy: ethernet@ff550000 {
736 compatible = "rockchip,rk3328-gmac";
737 reg = <0x0 0xff550000 0x0 0x10000>;
738 rockchip,grf = <&grf>;
739 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
740 interrupt-names = "macirq";
741 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
742 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
743 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
744 <&cru SCLK_MAC2PHY_OUT>;
745 clock-names = "stmmaceth", "mac_clk_rx",
746 "mac_clk_tx", "clk_mac_ref",
747 "aclk_mac", "pclk_mac",
748 "clk_macphy";
749 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
750 reset-names = "stmmaceth", "mac-phy";
751 phy-mode = "rmii";
752 phy-handle = <&phy>;
753 status = "disabled";
754
755 mdio {
756 compatible = "snps,dwmac-mdio";
757 #address-cells = <1>;
758 #size-cells = <0>;
759
760 phy: phy@0 {
761 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
762 reg = <0>;
763 clocks = <&cru SCLK_MAC2PHY_OUT>;
764 resets = <&cru SRST_MACPHY>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
767 phy-is-integrated;
768 };
769 };
770 };
771
772 usb20_otg: usb@ff580000 {
773 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
774 "snps,dwc2";
775 reg = <0x0 0xff580000 0x0 0x40000>;
776 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&cru HCLK_OTG>;
778 clock-names = "otg";
779 dr_mode = "otg";
780 g-np-tx-fifo-size = <16>;
781 g-rx-fifo-size = <280>;
782 g-tx-fifo-size = <256 128 128 64 32 16>;
783 g-use-dma;
784 phys = <&u2phy_otg>;
785 phy-names = "usb2-phy";
786 status = "disabled";
787 };
788
789 usb_host0_ehci: usb@ff5c0000 {
790 compatible = "generic-ehci";
791 reg = <0x0 0xff5c0000 0x0 0x10000>;
792 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&cru HCLK_HOST0>, <&u2phy>;
794 clock-names = "usbhost", "utmi";
795 phys = <&u2phy_host>;
796 phy-names = "usb";
797 status = "disabled";
798 };
799
800 usb_host0_ohci: usb@ff5d0000 {
801 compatible = "generic-ohci";
802 reg = <0x0 0xff5d0000 0x0 0x10000>;
803 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&cru HCLK_HOST0>, <&u2phy>;
805 clock-names = "usbhost", "utmi";
806 phys = <&u2phy_host>;
807 phy-names = "usb";
808 status = "disabled";
809 };
810
811 gic: interrupt-controller@ff811000 {
812 compatible = "arm,gic-400";
813 #interrupt-cells = <3>;
814 #address-cells = <0>;
815 interrupt-controller;
816 reg = <0x0 0xff811000 0 0x1000>,
817 <0x0 0xff812000 0 0x2000>,
818 <0x0 0xff814000 0 0x2000>,
819 <0x0 0xff816000 0 0x2000>;
820 interrupts = <GIC_PPI 9
821 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
822 };
823
824 pinctrl: pinctrl {
825 compatible = "rockchip,rk3328-pinctrl";
826 rockchip,grf = <&grf>;
827 #address-cells = <2>;
828 #size-cells = <2>;
829 ranges;
830
831 gpio0: gpio0@ff210000 {
832 compatible = "rockchip,gpio-bank";
833 reg = <0x0 0xff210000 0x0 0x100>;
834 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&cru PCLK_GPIO0>;
836
837 gpio-controller;
838 #gpio-cells = <2>;
839
840 interrupt-controller;
841 #interrupt-cells = <2>;
842 };
843
844 gpio1: gpio1@ff220000 {
845 compatible = "rockchip,gpio-bank";
846 reg = <0x0 0xff220000 0x0 0x100>;
847 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cru PCLK_GPIO1>;
849
850 gpio-controller;
851 #gpio-cells = <2>;
852
853 interrupt-controller;
854 #interrupt-cells = <2>;
855 };
856
857 gpio2: gpio2@ff230000 {
858 compatible = "rockchip,gpio-bank";
859 reg = <0x0 0xff230000 0x0 0x100>;
860 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru PCLK_GPIO2>;
862
863 gpio-controller;
864 #gpio-cells = <2>;
865
866 interrupt-controller;
867 #interrupt-cells = <2>;
868 };
869
870 gpio3: gpio3@ff240000 {
871 compatible = "rockchip,gpio-bank";
872 reg = <0x0 0xff240000 0x0 0x100>;
873 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&cru PCLK_GPIO3>;
875
876 gpio-controller;
877 #gpio-cells = <2>;
878
879 interrupt-controller;
880 #interrupt-cells = <2>;
881 };
882
883 pcfg_pull_up: pcfg-pull-up {
884 bias-pull-up;
885 };
886
887 pcfg_pull_down: pcfg-pull-down {
888 bias-pull-down;
889 };
890
891 pcfg_pull_none: pcfg-pull-none {
892 bias-disable;
893 };
894
895 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
896 bias-disable;
897 drive-strength = <2>;
898 };
899
900 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
901 bias-pull-up;
902 drive-strength = <2>;
903 };
904
905 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
906 bias-pull-up;
907 drive-strength = <4>;
908 };
909
910 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
911 bias-disable;
912 drive-strength = <4>;
913 };
914
915 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
916 bias-pull-down;
917 drive-strength = <4>;
918 };
919
920 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
921 bias-disable;
922 drive-strength = <8>;
923 };
924
925 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
926 bias-pull-up;
927 drive-strength = <8>;
928 };
929
930 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
931 bias-disable;
932 drive-strength = <12>;
933 };
934
935 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
936 bias-pull-up;
937 drive-strength = <12>;
938 };
939
940 pcfg_output_high: pcfg-output-high {
941 output-high;
942 };
943
944 pcfg_output_low: pcfg-output-low {
945 output-low;
946 };
947
948 pcfg_input_high: pcfg-input-high {
949 bias-pull-up;
950 input-enable;
951 };
952
953 pcfg_input: pcfg-input {
954 input-enable;
955 };
956
957 i2c0 {
958 i2c0_xfer: i2c0-xfer {
959 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
960 <2 RK_PD1 1 &pcfg_pull_none>;
961 };
962 };
963
964 i2c1 {
965 i2c1_xfer: i2c1-xfer {
966 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
967 <2 RK_PA5 2 &pcfg_pull_none>;
968 };
969 };
970
971 i2c2 {
972 i2c2_xfer: i2c2-xfer {
973 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
974 <2 RK_PB6 1 &pcfg_pull_none>;
975 };
976 };
977
978 i2c3 {
979 i2c3_xfer: i2c3-xfer {
980 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
981 <0 RK_PA6 2 &pcfg_pull_none>;
982 };
983 i2c3_gpio: i2c3-gpio {
984 rockchip,pins =
985 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
986 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
987 };
988 };
989
990 hdmi_i2c {
991 hdmii2c_xfer: hdmii2c-xfer {
992 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
993 <0 RK_PA6 1 &pcfg_pull_none>;
994 };
995 };
996
997 pdm-0 {
998 pdmm0_clk: pdmm0-clk {
999 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1000 };
1001
1002 pdmm0_fsync: pdmm0-fsync {
1003 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1004 };
1005
1006 pdmm0_sdi0: pdmm0-sdi0 {
1007 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1008 };
1009
1010 pdmm0_sdi1: pdmm0-sdi1 {
1011 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1012 };
1013
1014 pdmm0_sdi2: pdmm0-sdi2 {
1015 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1016 };
1017
1018 pdmm0_sdi3: pdmm0-sdi3 {
1019 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1020 };
1021
1022 pdmm0_clk_sleep: pdmm0-clk-sleep {
1023 rockchip,pins =
1024 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1025 };
1026
1027 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1028 rockchip,pins =
1029 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1030 };
1031
1032 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1033 rockchip,pins =
1034 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1035 };
1036
1037 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1038 rockchip,pins =
1039 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1040 };
1041
1042 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1043 rockchip,pins =
1044 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1045 };
1046
1047 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1048 rockchip,pins =
1049 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1050 };
1051 };
1052
1053 tsadc {
1054 otp_gpio: otp-gpio {
1055 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1056 };
1057
1058 otp_out: otp-out {
1059 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1060 };
1061 };
1062
1063 uart0 {
1064 uart0_xfer: uart0-xfer {
1065 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1066 <1 RK_PB0 1 &pcfg_pull_none>;
1067 };
1068
1069 uart0_cts: uart0-cts {
1070 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1071 };
1072
1073 uart0_rts: uart0-rts {
1074 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1075 };
1076
1077 uart0_rts_gpio: uart0-rts-gpio {
1078 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1079 };
1080 };
1081
1082 uart1 {
1083 uart1_xfer: uart1-xfer {
1084 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1085 <3 RK_PA6 4 &pcfg_pull_none>;
1086 };
1087
1088 uart1_cts: uart1-cts {
1089 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1090 };
1091
1092 uart1_rts: uart1-rts {
1093 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1094 };
1095
1096 uart1_rts_gpio: uart1-rts-gpio {
1097 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1098 };
1099 };
1100
1101 uart2-0 {
1102 uart2m0_xfer: uart2m0-xfer {
1103 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1104 <1 RK_PA1 2 &pcfg_pull_none>;
1105 };
1106 };
1107
1108 uart2-1 {
1109 uart2m1_xfer: uart2m1-xfer {
1110 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1111 <2 RK_PA1 1 &pcfg_pull_none>;
1112 };
1113 };
1114
1115 spi0-0 {
1116 spi0m0_clk: spi0m0-clk {
1117 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1118 };
1119
1120 spi0m0_cs0: spi0m0-cs0 {
1121 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1122 };
1123
1124 spi0m0_tx: spi0m0-tx {
1125 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1126 };
1127
1128 spi0m0_rx: spi0m0-rx {
1129 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1130 };
1131
1132 spi0m0_cs1: spi0m0-cs1 {
1133 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1134 };
1135 };
1136
1137 spi0-1 {
1138 spi0m1_clk: spi0m1-clk {
1139 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1140 };
1141
1142 spi0m1_cs0: spi0m1-cs0 {
1143 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1144 };
1145
1146 spi0m1_tx: spi0m1-tx {
1147 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1148 };
1149
1150 spi0m1_rx: spi0m1-rx {
1151 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1152 };
1153
1154 spi0m1_cs1: spi0m1-cs1 {
1155 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1156 };
1157 };
1158
1159 spi0-2 {
1160 spi0m2_clk: spi0m2-clk {
1161 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1162 };
1163
1164 spi0m2_cs0: spi0m2-cs0 {
1165 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1166 };
1167
1168 spi0m2_tx: spi0m2-tx {
1169 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1170 };
1171
1172 spi0m2_rx: spi0m2-rx {
1173 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1174 };
1175 };
1176
1177 i2s1 {
1178 i2s1_mclk: i2s1-mclk {
1179 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1180 };
1181
1182 i2s1_sclk: i2s1-sclk {
1183 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1184 };
1185
1186 i2s1_lrckrx: i2s1-lrckrx {
1187 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1188 };
1189
1190 i2s1_lrcktx: i2s1-lrcktx {
1191 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1192 };
1193
1194 i2s1_sdi: i2s1-sdi {
1195 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1196 };
1197
1198 i2s1_sdo: i2s1-sdo {
1199 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1200 };
1201
1202 i2s1_sdio1: i2s1-sdio1 {
1203 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1204 };
1205
1206 i2s1_sdio2: i2s1-sdio2 {
1207 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1208 };
1209
1210 i2s1_sdio3: i2s1-sdio3 {
1211 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1212 };
1213
1214 i2s1_sleep: i2s1-sleep {
1215 rockchip,pins =
1216 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1217 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1218 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1219 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1220 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1221 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1222 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1223 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1224 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1225 };
1226 };
1227
1228 i2s2-0 {
1229 i2s2m0_mclk: i2s2m0-mclk {
1230 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1231 };
1232
1233 i2s2m0_sclk: i2s2m0-sclk {
1234 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1235 };
1236
1237 i2s2m0_lrckrx: i2s2m0-lrckrx {
1238 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1239 };
1240
1241 i2s2m0_lrcktx: i2s2m0-lrcktx {
1242 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1243 };
1244
1245 i2s2m0_sdi: i2s2m0-sdi {
1246 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1247 };
1248
1249 i2s2m0_sdo: i2s2m0-sdo {
1250 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1251 };
1252
1253 i2s2m0_sleep: i2s2m0-sleep {
1254 rockchip,pins =
1255 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1256 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1257 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1258 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1259 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1260 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1261 };
1262 };
1263
1264 i2s2-1 {
1265 i2s2m1_mclk: i2s2m1-mclk {
1266 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1267 };
1268
1269 i2s2m1_sclk: i2s2m1-sclk {
1270 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1271 };
1272
1273 i2s2m1_lrckrx: i2sm1-lrckrx {
1274 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1275 };
1276
1277 i2s2m1_lrcktx: i2s2m1-lrcktx {
1278 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1279 };
1280
1281 i2s2m1_sdi: i2s2m1-sdi {
1282 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1283 };
1284
1285 i2s2m1_sdo: i2s2m1-sdo {
1286 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1287 };
1288
1289 i2s2m1_sleep: i2s2m1-sleep {
1290 rockchip,pins =
1291 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1292 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1293 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1294 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1295 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1296 };
1297 };
1298
1299 spdif-0 {
1300 spdifm0_tx: spdifm0-tx {
1301 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1302 };
1303 };
1304
1305 spdif-1 {
1306 spdifm1_tx: spdifm1-tx {
1307 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1308 };
1309 };
1310
1311 spdif-2 {
1312 spdifm2_tx: spdifm2-tx {
1313 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1314 };
1315 };
1316
1317 sdmmc0-0 {
1318 sdmmc0m0_pwren: sdmmc0m0-pwren {
1319 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1320 };
1321
1322 sdmmc0m0_gpio: sdmmc0m0-gpio {
1323 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1324 };
1325 };
1326
1327 sdmmc0-1 {
1328 sdmmc0m1_pwren: sdmmc0m1-pwren {
1329 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1330 };
1331
1332 sdmmc0m1_gpio: sdmmc0m1-gpio {
1333 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1334 };
1335 };
1336
1337 sdmmc0 {
1338 sdmmc0_clk: sdmmc0-clk {
1339 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1340 };
1341
1342 sdmmc0_cmd: sdmmc0-cmd {
1343 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1344 };
1345
1346 sdmmc0_dectn: sdmmc0-dectn {
1347 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1348 };
1349
1350 sdmmc0_wrprt: sdmmc0-wrprt {
1351 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1352 };
1353
1354 sdmmc0_bus1: sdmmc0-bus1 {
1355 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1356 };
1357
1358 sdmmc0_bus4: sdmmc0-bus4 {
1359 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1360 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1361 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1362 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1363 };
1364
1365 sdmmc0_gpio: sdmmc0-gpio {
1366 rockchip,pins =
1367 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1368 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1369 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1370 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1371 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1372 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1373 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1374 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1375 };
1376 };
1377
1378 sdmmc0ext {
1379 sdmmc0ext_clk: sdmmc0ext-clk {
1380 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1381 };
1382
1383 sdmmc0ext_cmd: sdmmc0ext-cmd {
1384 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1385 };
1386
1387 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1388 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1389 };
1390
1391 sdmmc0ext_dectn: sdmmc0ext-dectn {
1392 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1393 };
1394
1395 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1396 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1397 };
1398
1399 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1400 rockchip,pins =
1401 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1402 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1403 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1404 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1405 };
1406
1407 sdmmc0ext_gpio: sdmmc0ext-gpio {
1408 rockchip,pins =
1409 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1410 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1411 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1412 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1413 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1414 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1415 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1416 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1417 };
1418 };
1419
1420 sdmmc1 {
1421 sdmmc1_clk: sdmmc1-clk {
1422 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1423 };
1424
1425 sdmmc1_cmd: sdmmc1-cmd {
1426 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1427 };
1428
1429 sdmmc1_pwren: sdmmc1-pwren {
1430 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1431 };
1432
1433 sdmmc1_wrprt: sdmmc1-wrprt {
1434 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1435 };
1436
1437 sdmmc1_dectn: sdmmc1-dectn {
1438 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1439 };
1440
1441 sdmmc1_bus1: sdmmc1-bus1 {
1442 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1443 };
1444
1445 sdmmc1_bus4: sdmmc1-bus4 {
1446 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1447 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1448 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1449 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1450 };
1451
1452 sdmmc1_gpio: sdmmc1-gpio {
1453 rockchip,pins =
1454 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1455 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1456 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1457 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1458 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1459 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1460 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1461 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1462 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1463 };
1464 };
1465
1466 emmc {
1467 emmc_clk: emmc-clk {
1468 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1469 };
1470
1471 emmc_cmd: emmc-cmd {
1472 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1473 };
1474
1475 emmc_pwren: emmc-pwren {
1476 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1477 };
1478
1479 emmc_rstnout: emmc-rstnout {
1480 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1481 };
1482
1483 emmc_bus1: emmc-bus1 {
1484 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1485 };
1486
1487 emmc_bus4: emmc-bus4 {
1488 rockchip,pins =
1489 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1490 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1491 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1492 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1493 };
1494
1495 emmc_bus8: emmc-bus8 {
1496 rockchip,pins =
1497 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1498 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1499 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1500 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1501 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1502 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1503 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1504 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1505 };
1506 };
1507
1508 pwm0 {
1509 pwm0_pin: pwm0-pin {
1510 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1511 };
1512 };
1513
1514 pwm1 {
1515 pwm1_pin: pwm1-pin {
1516 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1517 };
1518 };
1519
1520 pwm2 {
1521 pwm2_pin: pwm2-pin {
1522 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1523 };
1524 };
1525
1526 pwmir {
1527 pwmir_pin: pwmir-pin {
1528 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1529 };
1530 };
1531
1532 gmac-1 {
1533 rgmiim1_pins: rgmiim1-pins {
1534 rockchip,pins =
1535 /* mac_txclk */
1536 <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1537 /* mac_rxclk */
1538 <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1539 /* mac_mdio */
1540 <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1541 /* mac_txen */
1542 <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1543 /* mac_clk */
1544 <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1545 /* mac_rxdv */
1546 <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1547 /* mac_mdc */
1548 <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1549 /* mac_rxd1 */
1550 <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1551 /* mac_rxd0 */
1552 <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1553 /* mac_txd1 */
1554 <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1555 /* mac_txd0 */
1556 <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1557 /* mac_rxd3 */
1558 <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1559 /* mac_rxd2 */
1560 <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1561 /* mac_txd3 */
1562 <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1563 /* mac_txd2 */
1564 <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1565
1566 /* mac_txclk */
1567 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1568 /* mac_txen */
1569 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1570 /* mac_clk */
1571 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1572 /* mac_txd1 */
1573 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1574 /* mac_txd0 */
1575 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1576 /* mac_txd3 */
1577 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1578 /* mac_txd2 */
1579 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1580 };
1581
1582 rmiim1_pins: rmiim1-pins {
1583 rockchip,pins =
1584 /* mac_mdio */
1585 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1586 /* mac_txen */
1587 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1588 /* mac_clk */
1589 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1590 /* mac_rxer */
1591 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1592 /* mac_rxdv */
1593 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1594 /* mac_mdc */
1595 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1596 /* mac_rxd1 */
1597 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1598 /* mac_rxd0 */
1599 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1600 /* mac_txd1 */
1601 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1602 /* mac_txd0 */
1603 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1604
1605 /* mac_mdio */
1606 <0 RK_PB3 1 &pcfg_pull_none>,
1607 /* mac_txen */
1608 <0 RK_PB4 1 &pcfg_pull_none>,
1609 /* mac_clk */
1610 <0 RK_PD0 1 &pcfg_pull_none>,
1611 /* mac_mdc */
1612 <0 RK_PC3 1 &pcfg_pull_none>,
1613 /* mac_txd1 */
1614 <0 RK_PC0 1 &pcfg_pull_none>,
1615 /* mac_txd0 */
1616 <0 RK_PC1 1 &pcfg_pull_none>;
1617 };
1618 };
1619
1620 gmac2phy {
1621 fephyled_speed100: fephyled-speed100 {
1622 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1623 };
1624
1625 fephyled_speed10: fephyled-speed10 {
1626 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1627 };
1628
1629 fephyled_duplex: fephyled-duplex {
1630 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1631 };
1632
1633 fephyled_rxm0: fephyled-rxm0 {
1634 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1635 };
1636
1637 fephyled_txm0: fephyled-txm0 {
1638 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1639 };
1640
1641 fephyled_linkm0: fephyled-linkm0 {
1642 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1643 };
1644
1645 fephyled_rxm1: fephyled-rxm1 {
1646 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1647 };
1648
1649 fephyled_txm1: fephyled-txm1 {
1650 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1651 };
1652
1653 fephyled_linkm1: fephyled-linkm1 {
1654 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1655 };
1656 };
1657
1658 tsadc_pin {
1659 tsadc_int: tsadc-int {
1660 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1661 };
1662 tsadc_gpio: tsadc-gpio {
1663 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1664 };
1665 };
1666
1667 hdmi_pin {
1668 hdmi_cec: hdmi-cec {
1669 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1670 };
1671
1672 hdmi_hpd: hdmi-hpd {
1673 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1674 };
1675 };
1676
1677 cif-0 {
1678 dvp_d2d9_m0:dvp-d2d9-m0 {
1679 rockchip,pins =
1680 /* cif_d0 */
1681 <3 RK_PA4 2 &pcfg_pull_none>,
1682 /* cif_d1 */
1683 <3 RK_PA5 2 &pcfg_pull_none>,
1684 /* cif_d2 */
1685 <3 RK_PA6 2 &pcfg_pull_none>,
1686 /* cif_d3 */
1687 <3 RK_PA7 2 &pcfg_pull_none>,
1688 /* cif_d4 */
1689 <3 RK_PB0 2 &pcfg_pull_none>,
1690 /* cif_d5m0 */
1691 <3 RK_PB1 2 &pcfg_pull_none>,
1692 /* cif_d6m0 */
1693 <3 RK_PB2 2 &pcfg_pull_none>,
1694 /* cif_d7m0 */
1695 <3 RK_PB3 2 &pcfg_pull_none>,
1696 /* cif_href */
1697 <3 RK_PA1 2 &pcfg_pull_none>,
1698 /* cif_vsync */
1699 <3 RK_PA0 2 &pcfg_pull_none>,
1700 /* cif_clkoutm0 */
1701 <3 RK_PA3 2 &pcfg_pull_none>,
1702 /* cif_clkin */
1703 <3 RK_PA2 2 &pcfg_pull_none>;
1704 };
1705 };
1706
1707 cif-1 {
1708 dvp_d2d9_m1:dvp-d2d9-m1 {
1709 rockchip,pins =
1710 /* cif_d0 */
1711 <3 RK_PA4 2 &pcfg_pull_none>,
1712 /* cif_d1 */
1713 <3 RK_PA5 2 &pcfg_pull_none>,
1714 /* cif_d2 */
1715 <3 RK_PA6 2 &pcfg_pull_none>,
1716 /* cif_d3 */
1717 <3 RK_PA7 2 &pcfg_pull_none>,
1718 /* cif_d4 */
1719 <3 RK_PB0 2 &pcfg_pull_none>,
1720 /* cif_d5m1 */
1721 <2 RK_PC0 4 &pcfg_pull_none>,
1722 /* cif_d6m1 */
1723 <2 RK_PC1 4 &pcfg_pull_none>,
1724 /* cif_d7m1 */
1725 <2 RK_PC2 4 &pcfg_pull_none>,
1726 /* cif_href */
1727 <3 RK_PA1 2 &pcfg_pull_none>,
1728 /* cif_vsync */
1729 <3 RK_PA0 2 &pcfg_pull_none>,
1730 /* cif_clkoutm1 */
1731 <2 RK_PB7 4 &pcfg_pull_none>,
1732 /* cif_clkin */
1733 <3 RK_PA2 2 &pcfg_pull_none>;
1734 };
1735 };
1736 };
1737 };
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