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[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
1 /*
2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/thermal/thermal.h>
50
51 / {
52 compatible = "rockchip,rk3399";
53
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
57
58 aliases {
59 ethernet0 = &gmac;
60 i2c0 = &i2c0;
61 i2c1 = &i2c1;
62 i2c2 = &i2c2;
63 i2c3 = &i2c3;
64 i2c4 = &i2c4;
65 i2c5 = &i2c5;
66 i2c6 = &i2c6;
67 i2c7 = &i2c7;
68 i2c8 = &i2c8;
69 serial0 = &uart0;
70 serial1 = &uart1;
71 serial2 = &uart2;
72 serial3 = &uart3;
73 serial4 = &uart4;
74 };
75
76 cpus {
77 #address-cells = <2>;
78 #size-cells = <0>;
79
80 cpu-map {
81 cluster0 {
82 core0 {
83 cpu = <&cpu_l0>;
84 };
85 core1 {
86 cpu = <&cpu_l1>;
87 };
88 core2 {
89 cpu = <&cpu_l2>;
90 };
91 core3 {
92 cpu = <&cpu_l3>;
93 };
94 };
95
96 cluster1 {
97 core0 {
98 cpu = <&cpu_b0>;
99 };
100 core1 {
101 cpu = <&cpu_b1>;
102 };
103 };
104 };
105
106 cpu_l0: cpu@0 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x0 0x0>;
110 enable-method = "psci";
111 #cooling-cells = <2>; /* min followed by max */
112 clocks = <&cru ARMCLKL>;
113 dynamic-power-coefficient = <100>;
114 };
115
116 cpu_l1: cpu@1 {
117 device_type = "cpu";
118 compatible = "arm,cortex-a53", "arm,armv8";
119 reg = <0x0 0x1>;
120 enable-method = "psci";
121 clocks = <&cru ARMCLKL>;
122 dynamic-power-coefficient = <100>;
123 };
124
125 cpu_l2: cpu@2 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a53", "arm,armv8";
128 reg = <0x0 0x2>;
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
131 dynamic-power-coefficient = <100>;
132 };
133
134 cpu_l3: cpu@3 {
135 device_type = "cpu";
136 compatible = "arm,cortex-a53", "arm,armv8";
137 reg = <0x0 0x3>;
138 enable-method = "psci";
139 clocks = <&cru ARMCLKL>;
140 dynamic-power-coefficient = <100>;
141 };
142
143 cpu_b0: cpu@100 {
144 device_type = "cpu";
145 compatible = "arm,cortex-a72", "arm,armv8";
146 reg = <0x0 0x100>;
147 enable-method = "psci";
148 #cooling-cells = <2>; /* min followed by max */
149 clocks = <&cru ARMCLKB>;
150 dynamic-power-coefficient = <436>;
151 };
152
153 cpu_b1: cpu@101 {
154 device_type = "cpu";
155 compatible = "arm,cortex-a72", "arm,armv8";
156 reg = <0x0 0x101>;
157 enable-method = "psci";
158 clocks = <&cru ARMCLKB>;
159 dynamic-power-coefficient = <436>;
160 };
161 };
162
163 display-subsystem {
164 compatible = "rockchip,display-subsystem";
165 ports = <&vopl_out>, <&vopb_out>;
166 };
167
168 pmu_a53 {
169 compatible = "arm,cortex-a53-pmu";
170 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
171 };
172
173 pmu_a72 {
174 compatible = "arm,cortex-a72-pmu";
175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
176 };
177
178 psci {
179 compatible = "arm,psci-1.0";
180 method = "smc";
181 };
182
183 timer {
184 compatible = "arm,armv8-timer";
185 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
186 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
187 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
188 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
189 arm,no-tick-in-suspend;
190 };
191
192 xin24m: xin24m {
193 compatible = "fixed-clock";
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
196 #clock-cells = <0>;
197 };
198
199 amba {
200 compatible = "simple-bus";
201 #address-cells = <2>;
202 #size-cells = <2>;
203 ranges;
204
205 dmac_bus: dma-controller@ff6d0000 {
206 compatible = "arm,pl330", "arm,primecell";
207 reg = <0x0 0xff6d0000 0x0 0x4000>;
208 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
210 #dma-cells = <1>;
211 clocks = <&cru ACLK_DMAC0_PERILP>;
212 clock-names = "apb_pclk";
213 };
214
215 dmac_peri: dma-controller@ff6e0000 {
216 compatible = "arm,pl330", "arm,primecell";
217 reg = <0x0 0xff6e0000 0x0 0x4000>;
218 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
219 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
220 #dma-cells = <1>;
221 clocks = <&cru ACLK_DMAC1_PERILP>;
222 clock-names = "apb_pclk";
223 };
224 };
225
226 pcie0: pcie@f8000000 {
227 compatible = "rockchip,rk3399-pcie";
228 reg = <0x0 0xf8000000 0x0 0x2000000>,
229 <0x0 0xfd000000 0x0 0x1000000>;
230 reg-names = "axi-base", "apb-base";
231 #address-cells = <3>;
232 #size-cells = <2>;
233 #interrupt-cells = <1>;
234 aspm-no-l0s;
235 bus-range = <0x0 0x1f>;
236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
238 clock-names = "aclk", "aclk-perf",
239 "hclk", "pm";
240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
241 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
242 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
243 interrupt-names = "sys", "legacy", "client";
244 interrupt-map-mask = <0 0 0 7>;
245 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
246 <0 0 0 2 &pcie0_intc 1>,
247 <0 0 0 3 &pcie0_intc 2>,
248 <0 0 0 4 &pcie0_intc 3>;
249 linux,pci-domain = <0>;
250 max-link-speed = <1>;
251 msi-map = <0x0 &its 0x0 0x1000>;
252 phys = <&pcie_phy 0>, <&pcie_phy 1>,
253 <&pcie_phy 2>, <&pcie_phy 3>;
254 phy-names = "pcie-phy-0", "pcie-phy-1",
255 "pcie-phy-2", "pcie-phy-3";
256 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
257 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
258 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
259 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
260 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
261 <&cru SRST_A_PCIE>;
262 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
263 "pm", "pclk", "aclk";
264 status = "disabled";
265
266 pcie0_intc: interrupt-controller {
267 interrupt-controller;
268 #address-cells = <0>;
269 #interrupt-cells = <1>;
270 };
271 };
272
273 gmac: ethernet@fe300000 {
274 compatible = "rockchip,rk3399-gmac";
275 reg = <0x0 0xfe300000 0x0 0x10000>;
276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
277 interrupt-names = "macirq";
278 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
279 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
280 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
281 <&cru PCLK_GMAC>;
282 clock-names = "stmmaceth", "mac_clk_rx",
283 "mac_clk_tx", "clk_mac_ref",
284 "clk_mac_refout", "aclk_mac",
285 "pclk_mac";
286 power-domains = <&power RK3399_PD_GMAC>;
287 resets = <&cru SRST_A_GMAC>;
288 reset-names = "stmmaceth";
289 rockchip,grf = <&grf>;
290 status = "disabled";
291 };
292
293 sdio0: dwmmc@fe310000 {
294 compatible = "rockchip,rk3399-dw-mshc",
295 "rockchip,rk3288-dw-mshc";
296 reg = <0x0 0xfe310000 0x0 0x4000>;
297 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
298 max-frequency = <150000000>;
299 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
300 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
301 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
302 fifo-depth = <0x100>;
303 power-domains = <&power RK3399_PD_SDIOAUDIO>;
304 resets = <&cru SRST_SDIO0>;
305 reset-names = "reset";
306 status = "disabled";
307 };
308
309 sdmmc: dwmmc@fe320000 {
310 compatible = "rockchip,rk3399-dw-mshc",
311 "rockchip,rk3288-dw-mshc";
312 reg = <0x0 0xfe320000 0x0 0x4000>;
313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
314 max-frequency = <150000000>;
315 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
316 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
317 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
318 fifo-depth = <0x100>;
319 power-domains = <&power RK3399_PD_SD>;
320 resets = <&cru SRST_SDMMC>;
321 reset-names = "reset";
322 status = "disabled";
323 };
324
325 sdhci: sdhci@fe330000 {
326 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
327 reg = <0x0 0xfe330000 0x0 0x10000>;
328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
329 arasan,soc-ctl-syscon = <&grf>;
330 assigned-clocks = <&cru SCLK_EMMC>;
331 assigned-clock-rates = <200000000>;
332 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
333 clock-names = "clk_xin", "clk_ahb";
334 clock-output-names = "emmc_cardclock";
335 #clock-cells = <0>;
336 phys = <&emmc_phy>;
337 phy-names = "phy_arasan";
338 power-domains = <&power RK3399_PD_EMMC>;
339 status = "disabled";
340 };
341
342 usb_host0_ehci: usb@fe380000 {
343 compatible = "generic-ehci";
344 reg = <0x0 0xfe380000 0x0 0x20000>;
345 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
346 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
347 <&u2phy0>;
348 clock-names = "usbhost", "arbiter",
349 "utmi";
350 phys = <&u2phy0_host>;
351 phy-names = "usb";
352 status = "disabled";
353 };
354
355 usb_host0_ohci: usb@fe3a0000 {
356 compatible = "generic-ohci";
357 reg = <0x0 0xfe3a0000 0x0 0x20000>;
358 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
359 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
360 <&u2phy0>;
361 clock-names = "usbhost", "arbiter",
362 "utmi";
363 phys = <&u2phy0_host>;
364 phy-names = "usb";
365 status = "disabled";
366 };
367
368 usb_host1_ehci: usb@fe3c0000 {
369 compatible = "generic-ehci";
370 reg = <0x0 0xfe3c0000 0x0 0x20000>;
371 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
372 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
373 <&u2phy1>;
374 clock-names = "usbhost", "arbiter",
375 "utmi";
376 phys = <&u2phy1_host>;
377 phy-names = "usb";
378 status = "disabled";
379 };
380
381 usb_host1_ohci: usb@fe3e0000 {
382 compatible = "generic-ohci";
383 reg = <0x0 0xfe3e0000 0x0 0x20000>;
384 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
385 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
386 <&u2phy1>;
387 clock-names = "usbhost", "arbiter",
388 "utmi";
389 phys = <&u2phy1_host>;
390 phy-names = "usb";
391 status = "disabled";
392 };
393
394 usbdrd3_0: usb@fe800000 {
395 compatible = "rockchip,rk3399-dwc3";
396 #address-cells = <2>;
397 #size-cells = <2>;
398 ranges;
399 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
400 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
401 clock-names = "ref_clk", "suspend_clk",
402 "bus_clk", "grf_clk";
403 status = "disabled";
404
405 usbdrd_dwc3_0: dwc3 {
406 compatible = "snps,dwc3";
407 reg = <0x0 0xfe800000 0x0 0x100000>;
408 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
409 dr_mode = "otg";
410 phys = <&u2phy0_otg>;
411 phy-names = "usb2-phy";
412 phy_type = "utmi_wide";
413 snps,dis_enblslpm_quirk;
414 snps,dis-u2-freeclk-exists-quirk;
415 snps,dis_u2_susphy_quirk;
416 snps,dis-del-phy-power-chg-quirk;
417 snps,dis-tx-ipgap-linecheck-quirk;
418 status = "disabled";
419 };
420 };
421
422 usbdrd3_1: usb@fe900000 {
423 compatible = "rockchip,rk3399-dwc3";
424 #address-cells = <2>;
425 #size-cells = <2>;
426 ranges;
427 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
428 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
429 clock-names = "ref_clk", "suspend_clk",
430 "bus_clk", "grf_clk";
431 status = "disabled";
432
433 usbdrd_dwc3_1: dwc3 {
434 compatible = "snps,dwc3";
435 reg = <0x0 0xfe900000 0x0 0x100000>;
436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
437 dr_mode = "otg";
438 phys = <&u2phy1_otg>;
439 phy-names = "usb2-phy";
440 phy_type = "utmi_wide";
441 snps,dis_enblslpm_quirk;
442 snps,dis-u2-freeclk-exists-quirk;
443 snps,dis_u2_susphy_quirk;
444 snps,dis-del-phy-power-chg-quirk;
445 snps,dis-tx-ipgap-linecheck-quirk;
446 status = "disabled";
447 };
448 };
449
450 gic: interrupt-controller@fee00000 {
451 compatible = "arm,gic-v3";
452 #interrupt-cells = <4>;
453 #address-cells = <2>;
454 #size-cells = <2>;
455 ranges;
456 interrupt-controller;
457
458 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
459 <0x0 0xfef00000 0 0xc0000>, /* GICR */
460 <0x0 0xfff00000 0 0x10000>, /* GICC */
461 <0x0 0xfff10000 0 0x10000>, /* GICH */
462 <0x0 0xfff20000 0 0x10000>; /* GICV */
463 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
464 its: interrupt-controller@fee20000 {
465 compatible = "arm,gic-v3-its";
466 msi-controller;
467 reg = <0x0 0xfee20000 0x0 0x20000>;
468 };
469
470 ppi-partitions {
471 ppi_cluster0: interrupt-partition-0 {
472 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
473 };
474
475 ppi_cluster1: interrupt-partition-1 {
476 affinity = <&cpu_b0 &cpu_b1>;
477 };
478 };
479 };
480
481 saradc: saradc@ff100000 {
482 compatible = "rockchip,rk3399-saradc";
483 reg = <0x0 0xff100000 0x0 0x100>;
484 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
485 #io-channel-cells = <1>;
486 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
487 clock-names = "saradc", "apb_pclk";
488 resets = <&cru SRST_P_SARADC>;
489 reset-names = "saradc-apb";
490 status = "disabled";
491 };
492
493 i2c1: i2c@ff110000 {
494 compatible = "rockchip,rk3399-i2c";
495 reg = <0x0 0xff110000 0x0 0x1000>;
496 assigned-clocks = <&cru SCLK_I2C1>;
497 assigned-clock-rates = <200000000>;
498 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
499 clock-names = "i2c", "pclk";
500 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c1_xfer>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 status = "disabled";
506 };
507
508 i2c2: i2c@ff120000 {
509 compatible = "rockchip,rk3399-i2c";
510 reg = <0x0 0xff120000 0x0 0x1000>;
511 assigned-clocks = <&cru SCLK_I2C2>;
512 assigned-clock-rates = <200000000>;
513 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
514 clock-names = "i2c", "pclk";
515 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&i2c2_xfer>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 status = "disabled";
521 };
522
523 i2c3: i2c@ff130000 {
524 compatible = "rockchip,rk3399-i2c";
525 reg = <0x0 0xff130000 0x0 0x1000>;
526 assigned-clocks = <&cru SCLK_I2C3>;
527 assigned-clock-rates = <200000000>;
528 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
529 clock-names = "i2c", "pclk";
530 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&i2c3_xfer>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 status = "disabled";
536 };
537
538 i2c5: i2c@ff140000 {
539 compatible = "rockchip,rk3399-i2c";
540 reg = <0x0 0xff140000 0x0 0x1000>;
541 assigned-clocks = <&cru SCLK_I2C5>;
542 assigned-clock-rates = <200000000>;
543 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
544 clock-names = "i2c", "pclk";
545 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c5_xfer>;
548 #address-cells = <1>;
549 #size-cells = <0>;
550 status = "disabled";
551 };
552
553 i2c6: i2c@ff150000 {
554 compatible = "rockchip,rk3399-i2c";
555 reg = <0x0 0xff150000 0x0 0x1000>;
556 assigned-clocks = <&cru SCLK_I2C6>;
557 assigned-clock-rates = <200000000>;
558 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
559 clock-names = "i2c", "pclk";
560 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&i2c6_xfer>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 status = "disabled";
566 };
567
568 i2c7: i2c@ff160000 {
569 compatible = "rockchip,rk3399-i2c";
570 reg = <0x0 0xff160000 0x0 0x1000>;
571 assigned-clocks = <&cru SCLK_I2C7>;
572 assigned-clock-rates = <200000000>;
573 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
574 clock-names = "i2c", "pclk";
575 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c7_xfer>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 status = "disabled";
581 };
582
583 uart0: serial@ff180000 {
584 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
585 reg = <0x0 0xff180000 0x0 0x100>;
586 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
587 clock-names = "baudclk", "apb_pclk";
588 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
589 reg-shift = <2>;
590 reg-io-width = <4>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&uart0_xfer>;
593 status = "disabled";
594 };
595
596 uart1: serial@ff190000 {
597 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xff190000 0x0 0x100>;
599 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
600 clock-names = "baudclk", "apb_pclk";
601 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
602 reg-shift = <2>;
603 reg-io-width = <4>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&uart1_xfer>;
606 status = "disabled";
607 };
608
609 uart2: serial@ff1a0000 {
610 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
611 reg = <0x0 0xff1a0000 0x0 0x100>;
612 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
613 clock-names = "baudclk", "apb_pclk";
614 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
615 reg-shift = <2>;
616 reg-io-width = <4>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart2c_xfer>;
619 status = "disabled";
620 };
621
622 uart3: serial@ff1b0000 {
623 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
624 reg = <0x0 0xff1b0000 0x0 0x100>;
625 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
626 clock-names = "baudclk", "apb_pclk";
627 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
628 reg-shift = <2>;
629 reg-io-width = <4>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&uart3_xfer>;
632 status = "disabled";
633 };
634
635 spi0: spi@ff1c0000 {
636 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
637 reg = <0x0 0xff1c0000 0x0 0x1000>;
638 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
639 clock-names = "spiclk", "apb_pclk";
640 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 status = "disabled";
646 };
647
648 spi1: spi@ff1d0000 {
649 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
650 reg = <0x0 0xff1d0000 0x0 0x1000>;
651 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
652 clock-names = "spiclk", "apb_pclk";
653 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
656 #address-cells = <1>;
657 #size-cells = <0>;
658 status = "disabled";
659 };
660
661 spi2: spi@ff1e0000 {
662 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
663 reg = <0x0 0xff1e0000 0x0 0x1000>;
664 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
665 clock-names = "spiclk", "apb_pclk";
666 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
669 #address-cells = <1>;
670 #size-cells = <0>;
671 status = "disabled";
672 };
673
674 spi4: spi@ff1f0000 {
675 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
676 reg = <0x0 0xff1f0000 0x0 0x1000>;
677 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
678 clock-names = "spiclk", "apb_pclk";
679 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
682 #address-cells = <1>;
683 #size-cells = <0>;
684 status = "disabled";
685 };
686
687 spi5: spi@ff200000 {
688 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
689 reg = <0x0 0xff200000 0x0 0x1000>;
690 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
691 clock-names = "spiclk", "apb_pclk";
692 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
695 power-domains = <&power RK3399_PD_SDIOAUDIO>;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 status = "disabled";
699 };
700
701 thermal_zones: thermal-zones {
702 cpu_thermal: cpu {
703 polling-delay-passive = <100>;
704 polling-delay = <1000>;
705
706 thermal-sensors = <&tsadc 0>;
707
708 trips {
709 cpu_alert0: cpu_alert0 {
710 temperature = <70000>;
711 hysteresis = <2000>;
712 type = "passive";
713 };
714 cpu_alert1: cpu_alert1 {
715 temperature = <75000>;
716 hysteresis = <2000>;
717 type = "passive";
718 };
719 cpu_crit: cpu_crit {
720 temperature = <95000>;
721 hysteresis = <2000>;
722 type = "critical";
723 };
724 };
725
726 cooling-maps {
727 map0 {
728 trip = <&cpu_alert0>;
729 cooling-device =
730 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
731 };
732 map1 {
733 trip = <&cpu_alert1>;
734 cooling-device =
735 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
736 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
737 };
738 };
739 };
740
741 gpu_thermal: gpu {
742 polling-delay-passive = <100>;
743 polling-delay = <1000>;
744
745 thermal-sensors = <&tsadc 1>;
746
747 trips {
748 gpu_alert0: gpu_alert0 {
749 temperature = <75000>;
750 hysteresis = <2000>;
751 type = "passive";
752 };
753 gpu_crit: gpu_crit {
754 temperature = <95000>;
755 hysteresis = <2000>;
756 type = "critical";
757 };
758 };
759
760 cooling-maps {
761 map0 {
762 trip = <&gpu_alert0>;
763 cooling-device =
764 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
765 };
766 };
767 };
768 };
769
770 tsadc: tsadc@ff260000 {
771 compatible = "rockchip,rk3399-tsadc";
772 reg = <0x0 0xff260000 0x0 0x100>;
773 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
774 assigned-clocks = <&cru SCLK_TSADC>;
775 assigned-clock-rates = <750000>;
776 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
777 clock-names = "tsadc", "apb_pclk";
778 resets = <&cru SRST_TSADC>;
779 reset-names = "tsadc-apb";
780 rockchip,grf = <&grf>;
781 rockchip,hw-tshut-temp = <95000>;
782 pinctrl-names = "init", "default", "sleep";
783 pinctrl-0 = <&otp_gpio>;
784 pinctrl-1 = <&otp_out>;
785 pinctrl-2 = <&otp_gpio>;
786 #thermal-sensor-cells = <1>;
787 status = "disabled";
788 };
789
790 qos_emmc: qos@ffa58000 {
791 compatible = "syscon";
792 reg = <0x0 0xffa58000 0x0 0x20>;
793 };
794
795 qos_gmac: qos@ffa5c000 {
796 compatible = "syscon";
797 reg = <0x0 0xffa5c000 0x0 0x20>;
798 };
799
800 qos_pcie: qos@ffa60080 {
801 compatible = "syscon";
802 reg = <0x0 0xffa60080 0x0 0x20>;
803 };
804
805 qos_usb_host0: qos@ffa60100 {
806 compatible = "syscon";
807 reg = <0x0 0xffa60100 0x0 0x20>;
808 };
809
810 qos_usb_host1: qos@ffa60180 {
811 compatible = "syscon";
812 reg = <0x0 0xffa60180 0x0 0x20>;
813 };
814
815 qos_usb_otg0: qos@ffa70000 {
816 compatible = "syscon";
817 reg = <0x0 0xffa70000 0x0 0x20>;
818 };
819
820 qos_usb_otg1: qos@ffa70080 {
821 compatible = "syscon";
822 reg = <0x0 0xffa70080 0x0 0x20>;
823 };
824
825 qos_sd: qos@ffa74000 {
826 compatible = "syscon";
827 reg = <0x0 0xffa74000 0x0 0x20>;
828 };
829
830 qos_sdioaudio: qos@ffa76000 {
831 compatible = "syscon";
832 reg = <0x0 0xffa76000 0x0 0x20>;
833 };
834
835 qos_hdcp: qos@ffa90000 {
836 compatible = "syscon";
837 reg = <0x0 0xffa90000 0x0 0x20>;
838 };
839
840 qos_iep: qos@ffa98000 {
841 compatible = "syscon";
842 reg = <0x0 0xffa98000 0x0 0x20>;
843 };
844
845 qos_isp0_m0: qos@ffaa0000 {
846 compatible = "syscon";
847 reg = <0x0 0xffaa0000 0x0 0x20>;
848 };
849
850 qos_isp0_m1: qos@ffaa0080 {
851 compatible = "syscon";
852 reg = <0x0 0xffaa0080 0x0 0x20>;
853 };
854
855 qos_isp1_m0: qos@ffaa8000 {
856 compatible = "syscon";
857 reg = <0x0 0xffaa8000 0x0 0x20>;
858 };
859
860 qos_isp1_m1: qos@ffaa8080 {
861 compatible = "syscon";
862 reg = <0x0 0xffaa8080 0x0 0x20>;
863 };
864
865 qos_rga_r: qos@ffab0000 {
866 compatible = "syscon";
867 reg = <0x0 0xffab0000 0x0 0x20>;
868 };
869
870 qos_rga_w: qos@ffab0080 {
871 compatible = "syscon";
872 reg = <0x0 0xffab0080 0x0 0x20>;
873 };
874
875 qos_video_m0: qos@ffab8000 {
876 compatible = "syscon";
877 reg = <0x0 0xffab8000 0x0 0x20>;
878 };
879
880 qos_video_m1_r: qos@ffac0000 {
881 compatible = "syscon";
882 reg = <0x0 0xffac0000 0x0 0x20>;
883 };
884
885 qos_video_m1_w: qos@ffac0080 {
886 compatible = "syscon";
887 reg = <0x0 0xffac0080 0x0 0x20>;
888 };
889
890 qos_vop_big_r: qos@ffac8000 {
891 compatible = "syscon";
892 reg = <0x0 0xffac8000 0x0 0x20>;
893 };
894
895 qos_vop_big_w: qos@ffac8080 {
896 compatible = "syscon";
897 reg = <0x0 0xffac8080 0x0 0x20>;
898 };
899
900 qos_vop_little: qos@ffad0000 {
901 compatible = "syscon";
902 reg = <0x0 0xffad0000 0x0 0x20>;
903 };
904
905 qos_perihp: qos@ffad8080 {
906 compatible = "syscon";
907 reg = <0x0 0xffad8080 0x0 0x20>;
908 };
909
910 qos_gpu: qos@ffae0000 {
911 compatible = "syscon";
912 reg = <0x0 0xffae0000 0x0 0x20>;
913 };
914
915 pmu: power-management@ff310000 {
916 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
917 reg = <0x0 0xff310000 0x0 0x1000>;
918
919 /*
920 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
921 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
922 * Some of the power domains are grouped together for every
923 * voltage domain.
924 * The detail contents as below.
925 */
926 power: power-controller {
927 compatible = "rockchip,rk3399-power-controller";
928 #power-domain-cells = <1>;
929 #address-cells = <1>;
930 #size-cells = <0>;
931
932 /* These power domains are grouped by VD_CENTER */
933 pd_iep@RK3399_PD_IEP {
934 reg = <RK3399_PD_IEP>;
935 clocks = <&cru ACLK_IEP>,
936 <&cru HCLK_IEP>;
937 pm_qos = <&qos_iep>;
938 };
939 pd_rga@RK3399_PD_RGA {
940 reg = <RK3399_PD_RGA>;
941 clocks = <&cru ACLK_RGA>,
942 <&cru HCLK_RGA>;
943 pm_qos = <&qos_rga_r>,
944 <&qos_rga_w>;
945 };
946 pd_vcodec@RK3399_PD_VCODEC {
947 reg = <RK3399_PD_VCODEC>;
948 clocks = <&cru ACLK_VCODEC>,
949 <&cru HCLK_VCODEC>;
950 pm_qos = <&qos_video_m0>;
951 };
952 pd_vdu@RK3399_PD_VDU {
953 reg = <RK3399_PD_VDU>;
954 clocks = <&cru ACLK_VDU>,
955 <&cru HCLK_VDU>;
956 pm_qos = <&qos_video_m1_r>,
957 <&qos_video_m1_w>;
958 };
959
960 /* These power domains are grouped by VD_GPU */
961 pd_gpu@RK3399_PD_GPU {
962 reg = <RK3399_PD_GPU>;
963 clocks = <&cru ACLK_GPU>;
964 pm_qos = <&qos_gpu>;
965 };
966
967 /* These power domains are grouped by VD_LOGIC */
968 pd_edp@RK3399_PD_EDP {
969 reg = <RK3399_PD_EDP>;
970 clocks = <&cru PCLK_EDP_CTRL>;
971 };
972 pd_emmc@RK3399_PD_EMMC {
973 reg = <RK3399_PD_EMMC>;
974 clocks = <&cru ACLK_EMMC>;
975 pm_qos = <&qos_emmc>;
976 };
977 pd_gmac@RK3399_PD_GMAC {
978 reg = <RK3399_PD_GMAC>;
979 clocks = <&cru ACLK_GMAC>,
980 <&cru PCLK_GMAC>;
981 pm_qos = <&qos_gmac>;
982 };
983 pd_sd@RK3399_PD_SD {
984 reg = <RK3399_PD_SD>;
985 clocks = <&cru HCLK_SDMMC>,
986 <&cru SCLK_SDMMC>;
987 pm_qos = <&qos_sd>;
988 };
989 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
990 reg = <RK3399_PD_SDIOAUDIO>;
991 clocks = <&cru HCLK_SDIO>;
992 pm_qos = <&qos_sdioaudio>;
993 };
994 pd_vio@RK3399_PD_VIO {
995 reg = <RK3399_PD_VIO>;
996 #address-cells = <1>;
997 #size-cells = <0>;
998
999 pd_hdcp@RK3399_PD_HDCP {
1000 reg = <RK3399_PD_HDCP>;
1001 clocks = <&cru ACLK_HDCP>,
1002 <&cru HCLK_HDCP>,
1003 <&cru PCLK_HDCP>;
1004 pm_qos = <&qos_hdcp>;
1005 };
1006 pd_isp0@RK3399_PD_ISP0 {
1007 reg = <RK3399_PD_ISP0>;
1008 clocks = <&cru ACLK_ISP0>,
1009 <&cru HCLK_ISP0>;
1010 pm_qos = <&qos_isp0_m0>,
1011 <&qos_isp0_m1>;
1012 };
1013 pd_isp1@RK3399_PD_ISP1 {
1014 reg = <RK3399_PD_ISP1>;
1015 clocks = <&cru ACLK_ISP1>,
1016 <&cru HCLK_ISP1>;
1017 pm_qos = <&qos_isp1_m0>,
1018 <&qos_isp1_m1>;
1019 };
1020 pd_tcpc0@RK3399_PD_TCPC0 {
1021 reg = <RK3399_PD_TCPD0>;
1022 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1023 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1024 };
1025 pd_tcpc1@RK3399_PD_TCPC1 {
1026 reg = <RK3399_PD_TCPD1>;
1027 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1028 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1029 };
1030 pd_vo@RK3399_PD_VO {
1031 reg = <RK3399_PD_VO>;
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034
1035 pd_vopb@RK3399_PD_VOPB {
1036 reg = <RK3399_PD_VOPB>;
1037 clocks = <&cru ACLK_VOP0>,
1038 <&cru HCLK_VOP0>;
1039 pm_qos = <&qos_vop_big_r>,
1040 <&qos_vop_big_w>;
1041 };
1042 pd_vopl@RK3399_PD_VOPL {
1043 reg = <RK3399_PD_VOPL>;
1044 clocks = <&cru ACLK_VOP1>,
1045 <&cru HCLK_VOP1>;
1046 pm_qos = <&qos_vop_little>;
1047 };
1048 };
1049 };
1050 };
1051 };
1052
1053 pmugrf: syscon@ff320000 {
1054 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1055 reg = <0x0 0xff320000 0x0 0x1000>;
1056 #address-cells = <1>;
1057 #size-cells = <1>;
1058
1059 pmu_io_domains: io-domains {
1060 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1061 status = "disabled";
1062 };
1063 };
1064
1065 spi3: spi@ff350000 {
1066 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1067 reg = <0x0 0xff350000 0x0 0x1000>;
1068 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1069 clock-names = "spiclk", "apb_pclk";
1070 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1075 status = "disabled";
1076 };
1077
1078 uart4: serial@ff370000 {
1079 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1080 reg = <0x0 0xff370000 0x0 0x100>;
1081 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1082 clock-names = "baudclk", "apb_pclk";
1083 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1084 reg-shift = <2>;
1085 reg-io-width = <4>;
1086 pinctrl-names = "default";
1087 pinctrl-0 = <&uart4_xfer>;
1088 status = "disabled";
1089 };
1090
1091 i2c0: i2c@ff3c0000 {
1092 compatible = "rockchip,rk3399-i2c";
1093 reg = <0x0 0xff3c0000 0x0 0x1000>;
1094 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1095 assigned-clock-rates = <200000000>;
1096 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1097 clock-names = "i2c", "pclk";
1098 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1099 pinctrl-names = "default";
1100 pinctrl-0 = <&i2c0_xfer>;
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1103 status = "disabled";
1104 };
1105
1106 i2c4: i2c@ff3d0000 {
1107 compatible = "rockchip,rk3399-i2c";
1108 reg = <0x0 0xff3d0000 0x0 0x1000>;
1109 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1110 assigned-clock-rates = <200000000>;
1111 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1112 clock-names = "i2c", "pclk";
1113 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1114 pinctrl-names = "default";
1115 pinctrl-0 = <&i2c4_xfer>;
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 status = "disabled";
1119 };
1120
1121 i2c8: i2c@ff3e0000 {
1122 compatible = "rockchip,rk3399-i2c";
1123 reg = <0x0 0xff3e0000 0x0 0x1000>;
1124 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1125 assigned-clock-rates = <200000000>;
1126 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1127 clock-names = "i2c", "pclk";
1128 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&i2c8_xfer>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 status = "disabled";
1134 };
1135
1136 pwm0: pwm@ff420000 {
1137 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1138 reg = <0x0 0xff420000 0x0 0x10>;
1139 #pwm-cells = <3>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&pwm0_pin>;
1142 clocks = <&pmucru PCLK_RKPWM_PMU>;
1143 clock-names = "pwm";
1144 status = "disabled";
1145 };
1146
1147 pwm1: pwm@ff420010 {
1148 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1149 reg = <0x0 0xff420010 0x0 0x10>;
1150 #pwm-cells = <3>;
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&pwm1_pin>;
1153 clocks = <&pmucru PCLK_RKPWM_PMU>;
1154 clock-names = "pwm";
1155 status = "disabled";
1156 };
1157
1158 pwm2: pwm@ff420020 {
1159 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1160 reg = <0x0 0xff420020 0x0 0x10>;
1161 #pwm-cells = <3>;
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&pwm2_pin>;
1164 clocks = <&pmucru PCLK_RKPWM_PMU>;
1165 clock-names = "pwm";
1166 status = "disabled";
1167 };
1168
1169 pwm3: pwm@ff420030 {
1170 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1171 reg = <0x0 0xff420030 0x0 0x10>;
1172 #pwm-cells = <3>;
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&pwm3a_pin>;
1175 clocks = <&pmucru PCLK_RKPWM_PMU>;
1176 clock-names = "pwm";
1177 status = "disabled";
1178 };
1179
1180 vpu_mmu: iommu@ff650800 {
1181 compatible = "rockchip,iommu";
1182 reg = <0x0 0xff650800 0x0 0x40>;
1183 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1184 interrupt-names = "vpu_mmu";
1185 #iommu-cells = <0>;
1186 status = "disabled";
1187 };
1188
1189 vdec_mmu: iommu@ff660480 {
1190 compatible = "rockchip,iommu";
1191 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1192 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1193 interrupt-names = "vdec_mmu";
1194 #iommu-cells = <0>;
1195 status = "disabled";
1196 };
1197
1198 iep_mmu: iommu@ff670800 {
1199 compatible = "rockchip,iommu";
1200 reg = <0x0 0xff670800 0x0 0x40>;
1201 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1202 interrupt-names = "iep_mmu";
1203 #iommu-cells = <0>;
1204 status = "disabled";
1205 };
1206
1207 efuse0: efuse@ff690000 {
1208 compatible = "rockchip,rk3399-efuse";
1209 reg = <0x0 0xff690000 0x0 0x80>;
1210 #address-cells = <1>;
1211 #size-cells = <1>;
1212 clocks = <&cru PCLK_EFUSE1024NS>;
1213 clock-names = "pclk_efuse";
1214
1215 /* Data cells */
1216 cpu_id: cpu-id@7 {
1217 reg = <0x07 0x10>;
1218 };
1219 cpub_leakage: cpu-leakage@17 {
1220 reg = <0x17 0x1>;
1221 };
1222 gpu_leakage: gpu-leakage@18 {
1223 reg = <0x18 0x1>;
1224 };
1225 center_leakage: center-leakage@19 {
1226 reg = <0x19 0x1>;
1227 };
1228 cpul_leakage: cpu-leakage@1a {
1229 reg = <0x1a 0x1>;
1230 };
1231 logic_leakage: logic-leakage@1b {
1232 reg = <0x1b 0x1>;
1233 };
1234 wafer_info: wafer-info@1c {
1235 reg = <0x1c 0x1>;
1236 };
1237 };
1238
1239 pmucru: pmu-clock-controller@ff750000 {
1240 compatible = "rockchip,rk3399-pmucru";
1241 reg = <0x0 0xff750000 0x0 0x1000>;
1242 rockchip,grf = <&pmugrf>;
1243 #clock-cells = <1>;
1244 #reset-cells = <1>;
1245 assigned-clocks = <&pmucru PLL_PPLL>;
1246 assigned-clock-rates = <676000000>;
1247 };
1248
1249 cru: clock-controller@ff760000 {
1250 compatible = "rockchip,rk3399-cru";
1251 reg = <0x0 0xff760000 0x0 0x1000>;
1252 rockchip,grf = <&grf>;
1253 #clock-cells = <1>;
1254 #reset-cells = <1>;
1255 assigned-clocks =
1256 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1257 <&cru PLL_NPLL>,
1258 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1259 <&cru PCLK_PERIHP>,
1260 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1261 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1262 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1263 assigned-clock-rates =
1264 <594000000>, <800000000>,
1265 <1000000000>,
1266 <150000000>, <75000000>,
1267 <37500000>,
1268 <100000000>, <100000000>,
1269 <50000000>, <600000000>,
1270 <100000000>, <50000000>;
1271 };
1272
1273 grf: syscon@ff770000 {
1274 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1275 reg = <0x0 0xff770000 0x0 0x10000>;
1276 #address-cells = <1>;
1277 #size-cells = <1>;
1278
1279 io_domains: io-domains {
1280 compatible = "rockchip,rk3399-io-voltage-domain";
1281 status = "disabled";
1282 };
1283
1284 u2phy0: usb2-phy@e450 {
1285 compatible = "rockchip,rk3399-usb2phy";
1286 reg = <0xe450 0x10>;
1287 clocks = <&cru SCLK_USB2PHY0_REF>;
1288 clock-names = "phyclk";
1289 #clock-cells = <0>;
1290 clock-output-names = "clk_usbphy0_480m";
1291 status = "disabled";
1292
1293 u2phy0_host: host-port {
1294 #phy-cells = <0>;
1295 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1296 interrupt-names = "linestate";
1297 status = "disabled";
1298 };
1299
1300 u2phy0_otg: otg-port {
1301 #phy-cells = <0>;
1302 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1303 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1304 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1305 interrupt-names = "otg-bvalid", "otg-id",
1306 "linestate";
1307 status = "disabled";
1308 };
1309 };
1310
1311 u2phy1: usb2-phy@e460 {
1312 compatible = "rockchip,rk3399-usb2phy";
1313 reg = <0xe460 0x10>;
1314 clocks = <&cru SCLK_USB2PHY1_REF>;
1315 clock-names = "phyclk";
1316 #clock-cells = <0>;
1317 clock-output-names = "clk_usbphy1_480m";
1318 status = "disabled";
1319
1320 u2phy1_host: host-port {
1321 #phy-cells = <0>;
1322 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1323 interrupt-names = "linestate";
1324 status = "disabled";
1325 };
1326
1327 u2phy1_otg: otg-port {
1328 #phy-cells = <0>;
1329 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1330 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1331 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1332 interrupt-names = "otg-bvalid", "otg-id",
1333 "linestate";
1334 status = "disabled";
1335 };
1336 };
1337
1338 emmc_phy: phy@f780 {
1339 compatible = "rockchip,rk3399-emmc-phy";
1340 reg = <0xf780 0x24>;
1341 clocks = <&sdhci>;
1342 clock-names = "emmcclk";
1343 #phy-cells = <0>;
1344 status = "disabled";
1345 };
1346
1347 pcie_phy: pcie-phy {
1348 compatible = "rockchip,rk3399-pcie-phy";
1349 clocks = <&cru SCLK_PCIEPHY_REF>;
1350 clock-names = "refclk";
1351 #phy-cells = <1>;
1352 resets = <&cru SRST_PCIEPHY>;
1353 reset-names = "phy";
1354 status = "disabled";
1355 };
1356 };
1357
1358 tcphy0: phy@ff7c0000 {
1359 compatible = "rockchip,rk3399-typec-phy";
1360 reg = <0x0 0xff7c0000 0x0 0x40000>;
1361 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1362 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1363 clock-names = "tcpdcore", "tcpdphy-ref";
1364 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1365 assigned-clock-rates = <50000000>;
1366 power-domains = <&power RK3399_PD_TCPD0>;
1367 resets = <&cru SRST_UPHY0>,
1368 <&cru SRST_UPHY0_PIPE_L00>,
1369 <&cru SRST_P_UPHY0_TCPHY>;
1370 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1371 rockchip,grf = <&grf>;
1372 rockchip,typec-conn-dir = <0xe580 0 16>;
1373 rockchip,usb3tousb2-en = <0xe580 3 19>;
1374 rockchip,external-psm = <0xe588 14 30>;
1375 rockchip,pipe-status = <0xe5c0 0 0>;
1376 status = "disabled";
1377
1378 tcphy0_dp: dp-port {
1379 #phy-cells = <0>;
1380 };
1381
1382 tcphy0_usb3: usb3-port {
1383 #phy-cells = <0>;
1384 };
1385 };
1386
1387 tcphy1: phy@ff800000 {
1388 compatible = "rockchip,rk3399-typec-phy";
1389 reg = <0x0 0xff800000 0x0 0x40000>;
1390 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1391 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1392 clock-names = "tcpdcore", "tcpdphy-ref";
1393 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1394 assigned-clock-rates = <50000000>;
1395 power-domains = <&power RK3399_PD_TCPD1>;
1396 resets = <&cru SRST_UPHY1>,
1397 <&cru SRST_UPHY1_PIPE_L00>,
1398 <&cru SRST_P_UPHY1_TCPHY>;
1399 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1400 rockchip,grf = <&grf>;
1401 rockchip,typec-conn-dir = <0xe58c 0 16>;
1402 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1403 rockchip,external-psm = <0xe594 14 30>;
1404 rockchip,pipe-status = <0xe5c0 16 16>;
1405 status = "disabled";
1406
1407 tcphy1_dp: dp-port {
1408 #phy-cells = <0>;
1409 };
1410
1411 tcphy1_usb3: usb3-port {
1412 #phy-cells = <0>;
1413 };
1414 };
1415
1416 watchdog@ff848000 {
1417 compatible = "snps,dw-wdt";
1418 reg = <0x0 0xff848000 0x0 0x100>;
1419 clocks = <&cru PCLK_WDT>;
1420 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1421 };
1422
1423 rktimer: rktimer@ff850000 {
1424 compatible = "rockchip,rk3399-timer";
1425 reg = <0x0 0xff850000 0x0 0x1000>;
1426 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1427 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1428 clock-names = "pclk", "timer";
1429 };
1430
1431 spdif: spdif@ff870000 {
1432 compatible = "rockchip,rk3399-spdif";
1433 reg = <0x0 0xff870000 0x0 0x1000>;
1434 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1435 dmas = <&dmac_bus 7>;
1436 dma-names = "tx";
1437 clock-names = "mclk", "hclk";
1438 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1439 pinctrl-names = "default";
1440 pinctrl-0 = <&spdif_bus>;
1441 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1442 status = "disabled";
1443 };
1444
1445 i2s0: i2s@ff880000 {
1446 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1447 reg = <0x0 0xff880000 0x0 0x1000>;
1448 rockchip,grf = <&grf>;
1449 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1450 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1451 dma-names = "tx", "rx";
1452 clock-names = "i2s_clk", "i2s_hclk";
1453 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1454 pinctrl-names = "default";
1455 pinctrl-0 = <&i2s0_8ch_bus>;
1456 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1457 status = "disabled";
1458 };
1459
1460 i2s1: i2s@ff890000 {
1461 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1462 reg = <0x0 0xff890000 0x0 0x1000>;
1463 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1464 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1465 dma-names = "tx", "rx";
1466 clock-names = "i2s_clk", "i2s_hclk";
1467 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1468 pinctrl-names = "default";
1469 pinctrl-0 = <&i2s1_2ch_bus>;
1470 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1471 status = "disabled";
1472 };
1473
1474 i2s2: i2s@ff8a0000 {
1475 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1476 reg = <0x0 0xff8a0000 0x0 0x1000>;
1477 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1478 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1479 dma-names = "tx", "rx";
1480 clock-names = "i2s_clk", "i2s_hclk";
1481 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1482 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1483 status = "disabled";
1484 };
1485
1486 vopl: vop@ff8f0000 {
1487 compatible = "rockchip,rk3399-vop-lit";
1488 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1489 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1490 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1491 assigned-clock-rates = <400000000>, <100000000>;
1492 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1493 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1494 iommus = <&vopl_mmu>;
1495 power-domains = <&power RK3399_PD_VOPL>;
1496 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1497 reset-names = "axi", "ahb", "dclk";
1498 status = "disabled";
1499
1500 vopl_out: port {
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1503
1504 vopl_out_mipi: endpoint@0 {
1505 reg = <0>;
1506 remote-endpoint = <&mipi_in_vopl>;
1507 };
1508
1509 vopl_out_edp: endpoint@1 {
1510 reg = <1>;
1511 remote-endpoint = <&edp_in_vopl>;
1512 };
1513
1514 vopl_out_hdmi: endpoint@2 {
1515 reg = <2>;
1516 remote-endpoint = <&hdmi_in_vopl>;
1517 };
1518 };
1519 };
1520
1521 vopl_mmu: iommu@ff8f3f00 {
1522 compatible = "rockchip,iommu";
1523 reg = <0x0 0xff8f3f00 0x0 0x100>;
1524 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1525 interrupt-names = "vopl_mmu";
1526 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1527 clock-names = "aclk", "hclk";
1528 power-domains = <&power RK3399_PD_VOPL>;
1529 #iommu-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 vopb: vop@ff900000 {
1534 compatible = "rockchip,rk3399-vop-big";
1535 reg = <0x0 0xff900000 0x0 0x3efc>;
1536 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1537 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1538 assigned-clock-rates = <400000000>, <100000000>;
1539 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1540 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1541 iommus = <&vopb_mmu>;
1542 power-domains = <&power RK3399_PD_VOPB>;
1543 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1544 reset-names = "axi", "ahb", "dclk";
1545 status = "disabled";
1546
1547 vopb_out: port {
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550
1551 vopb_out_edp: endpoint@0 {
1552 reg = <0>;
1553 remote-endpoint = <&edp_in_vopb>;
1554 };
1555
1556 vopb_out_mipi: endpoint@1 {
1557 reg = <1>;
1558 remote-endpoint = <&mipi_in_vopb>;
1559 };
1560
1561 vopb_out_hdmi: endpoint@2 {
1562 reg = <2>;
1563 remote-endpoint = <&hdmi_in_vopb>;
1564 };
1565 };
1566 };
1567
1568 vopb_mmu: iommu@ff903f00 {
1569 compatible = "rockchip,iommu";
1570 reg = <0x0 0xff903f00 0x0 0x100>;
1571 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1572 interrupt-names = "vopb_mmu";
1573 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1574 clock-names = "aclk", "hclk";
1575 power-domains = <&power RK3399_PD_VOPB>;
1576 #iommu-cells = <0>;
1577 status = "disabled";
1578 };
1579
1580 isp0_mmu: iommu@ff914000 {
1581 compatible = "rockchip,iommu";
1582 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1583 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1584 interrupt-names = "isp0_mmu";
1585 #iommu-cells = <0>;
1586 rockchip,disable-mmu-reset;
1587 status = "disabled";
1588 };
1589
1590 isp1_mmu: iommu@ff924000 {
1591 compatible = "rockchip,iommu";
1592 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1593 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1594 interrupt-names = "isp1_mmu";
1595 #iommu-cells = <0>;
1596 rockchip,disable-mmu-reset;
1597 status = "disabled";
1598 };
1599
1600 hdmi: hdmi@ff940000 {
1601 compatible = "rockchip,rk3399-dw-hdmi";
1602 reg = <0x0 0xff940000 0x0 0x20000>;
1603 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1604 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1605 clock-names = "iahb", "isfr", "vpll", "grf";
1606 power-domains = <&power RK3399_PD_HDCP>;
1607 reg-io-width = <4>;
1608 rockchip,grf = <&grf>;
1609 status = "disabled";
1610
1611 ports {
1612 hdmi_in: port {
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615
1616 hdmi_in_vopb: endpoint@0 {
1617 reg = <0>;
1618 remote-endpoint = <&vopb_out_hdmi>;
1619 };
1620 hdmi_in_vopl: endpoint@1 {
1621 reg = <1>;
1622 remote-endpoint = <&vopl_out_hdmi>;
1623 };
1624 };
1625 };
1626 };
1627
1628 mipi_dsi: mipi@ff960000 {
1629 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1630 reg = <0x0 0xff960000 0x0 0x8000>;
1631 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1632 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1633 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1634 clock-names = "ref", "pclk", "phy_cfg", "grf";
1635 power-domains = <&power RK3399_PD_VIO>;
1636 rockchip,grf = <&grf>;
1637 status = "disabled";
1638
1639 ports {
1640 mipi_in: port {
1641 #address-cells = <1>;
1642 #size-cells = <0>;
1643
1644 mipi_in_vopb: endpoint@0 {
1645 reg = <0>;
1646 remote-endpoint = <&vopb_out_mipi>;
1647 };
1648 mipi_in_vopl: endpoint@1 {
1649 reg = <1>;
1650 remote-endpoint = <&vopl_out_mipi>;
1651 };
1652 };
1653 };
1654 };
1655
1656 edp: edp@ff970000 {
1657 compatible = "rockchip,rk3399-edp";
1658 reg = <0x0 0xff970000 0x0 0x8000>;
1659 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1660 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1661 clock-names = "dp", "pclk";
1662 pinctrl-names = "default";
1663 pinctrl-0 = <&edp_hpd>;
1664 power-domains = <&power RK3399_PD_EDP>;
1665 resets = <&cru SRST_P_EDP_CTRL>;
1666 reset-names = "dp";
1667 rockchip,grf = <&grf>;
1668 status = "disabled";
1669
1670 ports {
1671 #address-cells = <1>;
1672 #size-cells = <0>;
1673 edp_in: port@0 {
1674 reg = <0>;
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1677
1678 edp_in_vopb: endpoint@0 {
1679 reg = <0>;
1680 remote-endpoint = <&vopb_out_edp>;
1681 };
1682
1683 edp_in_vopl: endpoint@1 {
1684 reg = <1>;
1685 remote-endpoint = <&vopl_out_edp>;
1686 };
1687 };
1688 };
1689 };
1690
1691 gpu: gpu@ff9a0000 {
1692 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1693 reg = <0x0 0xff9a0000 0x0 0x10000>;
1694 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1695 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1696 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1697 interrupt-names = "gpu", "job", "mmu";
1698 clocks = <&cru ACLK_GPU>;
1699 power-domains = <&power RK3399_PD_GPU>;
1700 status = "disabled";
1701 };
1702
1703 pinctrl: pinctrl {
1704 compatible = "rockchip,rk3399-pinctrl";
1705 rockchip,grf = <&grf>;
1706 rockchip,pmu = <&pmugrf>;
1707 #address-cells = <2>;
1708 #size-cells = <2>;
1709 ranges;
1710
1711 gpio0: gpio0@ff720000 {
1712 compatible = "rockchip,gpio-bank";
1713 reg = <0x0 0xff720000 0x0 0x100>;
1714 clocks = <&pmucru PCLK_GPIO0_PMU>;
1715 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1716
1717 gpio-controller;
1718 #gpio-cells = <0x2>;
1719
1720 interrupt-controller;
1721 #interrupt-cells = <0x2>;
1722 };
1723
1724 gpio1: gpio1@ff730000 {
1725 compatible = "rockchip,gpio-bank";
1726 reg = <0x0 0xff730000 0x0 0x100>;
1727 clocks = <&pmucru PCLK_GPIO1_PMU>;
1728 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1729
1730 gpio-controller;
1731 #gpio-cells = <0x2>;
1732
1733 interrupt-controller;
1734 #interrupt-cells = <0x2>;
1735 };
1736
1737 gpio2: gpio2@ff780000 {
1738 compatible = "rockchip,gpio-bank";
1739 reg = <0x0 0xff780000 0x0 0x100>;
1740 clocks = <&cru PCLK_GPIO2>;
1741 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1742
1743 gpio-controller;
1744 #gpio-cells = <0x2>;
1745
1746 interrupt-controller;
1747 #interrupt-cells = <0x2>;
1748 };
1749
1750 gpio3: gpio3@ff788000 {
1751 compatible = "rockchip,gpio-bank";
1752 reg = <0x0 0xff788000 0x0 0x100>;
1753 clocks = <&cru PCLK_GPIO3>;
1754 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1755
1756 gpio-controller;
1757 #gpio-cells = <0x2>;
1758
1759 interrupt-controller;
1760 #interrupt-cells = <0x2>;
1761 };
1762
1763 gpio4: gpio4@ff790000 {
1764 compatible = "rockchip,gpio-bank";
1765 reg = <0x0 0xff790000 0x0 0x100>;
1766 clocks = <&cru PCLK_GPIO4>;
1767 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1768
1769 gpio-controller;
1770 #gpio-cells = <0x2>;
1771
1772 interrupt-controller;
1773 #interrupt-cells = <0x2>;
1774 };
1775
1776 pcfg_pull_up: pcfg-pull-up {
1777 bias-pull-up;
1778 };
1779
1780 pcfg_pull_down: pcfg-pull-down {
1781 bias-pull-down;
1782 };
1783
1784 pcfg_pull_none: pcfg-pull-none {
1785 bias-disable;
1786 };
1787
1788 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1789 bias-disable;
1790 drive-strength = <12>;
1791 };
1792
1793 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1794 bias-pull-up;
1795 drive-strength = <8>;
1796 };
1797
1798 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1799 bias-pull-down;
1800 drive-strength = <4>;
1801 };
1802
1803 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1804 bias-pull-up;
1805 drive-strength = <2>;
1806 };
1807
1808 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1809 bias-pull-down;
1810 drive-strength = <12>;
1811 };
1812
1813 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1814 bias-disable;
1815 drive-strength = <13>;
1816 };
1817
1818 clock {
1819 clk_32k: clk-32k {
1820 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1821 };
1822 };
1823
1824 edp {
1825 edp_hpd: edp-hpd {
1826 rockchip,pins =
1827 <4 23 RK_FUNC_2 &pcfg_pull_none>;
1828 };
1829 };
1830
1831 gmac {
1832 rgmii_pins: rgmii-pins {
1833 rockchip,pins =
1834 /* mac_txclk */
1835 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1836 /* mac_rxclk */
1837 <3 14 RK_FUNC_1 &pcfg_pull_none>,
1838 /* mac_mdio */
1839 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1840 /* mac_txen */
1841 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1842 /* mac_clk */
1843 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1844 /* mac_rxdv */
1845 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1846 /* mac_mdc */
1847 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1848 /* mac_rxd1 */
1849 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1850 /* mac_rxd0 */
1851 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1852 /* mac_txd1 */
1853 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1854 /* mac_txd0 */
1855 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1856 /* mac_rxd3 */
1857 <3 3 RK_FUNC_1 &pcfg_pull_none>,
1858 /* mac_rxd2 */
1859 <3 2 RK_FUNC_1 &pcfg_pull_none>,
1860 /* mac_txd3 */
1861 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1862 /* mac_txd2 */
1863 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1864 };
1865
1866 rmii_pins: rmii-pins {
1867 rockchip,pins =
1868 /* mac_mdio */
1869 <3 13 RK_FUNC_1 &pcfg_pull_none>,
1870 /* mac_txen */
1871 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1872 /* mac_clk */
1873 <3 11 RK_FUNC_1 &pcfg_pull_none>,
1874 /* mac_rxer */
1875 <3 10 RK_FUNC_1 &pcfg_pull_none>,
1876 /* mac_rxdv */
1877 <3 9 RK_FUNC_1 &pcfg_pull_none>,
1878 /* mac_mdc */
1879 <3 8 RK_FUNC_1 &pcfg_pull_none>,
1880 /* mac_rxd1 */
1881 <3 7 RK_FUNC_1 &pcfg_pull_none>,
1882 /* mac_rxd0 */
1883 <3 6 RK_FUNC_1 &pcfg_pull_none>,
1884 /* mac_txd1 */
1885 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1886 /* mac_txd0 */
1887 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1888 };
1889 };
1890
1891 i2c0 {
1892 i2c0_xfer: i2c0-xfer {
1893 rockchip,pins =
1894 <1 15 RK_FUNC_2 &pcfg_pull_none>,
1895 <1 16 RK_FUNC_2 &pcfg_pull_none>;
1896 };
1897 };
1898
1899 i2c1 {
1900 i2c1_xfer: i2c1-xfer {
1901 rockchip,pins =
1902 <4 2 RK_FUNC_1 &pcfg_pull_none>,
1903 <4 1 RK_FUNC_1 &pcfg_pull_none>;
1904 };
1905 };
1906
1907 i2c2 {
1908 i2c2_xfer: i2c2-xfer {
1909 rockchip,pins =
1910 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1911 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1912 };
1913 };
1914
1915 i2c3 {
1916 i2c3_xfer: i2c3-xfer {
1917 rockchip,pins =
1918 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1919 <4 16 RK_FUNC_1 &pcfg_pull_none>;
1920 };
1921 };
1922
1923 i2c4 {
1924 i2c4_xfer: i2c4-xfer {
1925 rockchip,pins =
1926 <1 12 RK_FUNC_1 &pcfg_pull_none>,
1927 <1 11 RK_FUNC_1 &pcfg_pull_none>;
1928 };
1929 };
1930
1931 i2c5 {
1932 i2c5_xfer: i2c5-xfer {
1933 rockchip,pins =
1934 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1935 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1936 };
1937 };
1938
1939 i2c6 {
1940 i2c6_xfer: i2c6-xfer {
1941 rockchip,pins =
1942 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1943 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1944 };
1945 };
1946
1947 i2c7 {
1948 i2c7_xfer: i2c7-xfer {
1949 rockchip,pins =
1950 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1951 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1952 };
1953 };
1954
1955 i2c8 {
1956 i2c8_xfer: i2c8-xfer {
1957 rockchip,pins =
1958 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1959 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1960 };
1961 };
1962
1963 i2s0 {
1964 i2s0_8ch_bus: i2s0-8ch-bus {
1965 rockchip,pins =
1966 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1967 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1968 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1969 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1970 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1971 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1972 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1973 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1974 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1975 };
1976 };
1977
1978 i2s1 {
1979 i2s1_2ch_bus: i2s1-2ch-bus {
1980 rockchip,pins =
1981 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1982 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1983 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1984 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1985 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1986 };
1987 };
1988
1989 sdio0 {
1990 sdio0_bus1: sdio0-bus1 {
1991 rockchip,pins =
1992 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
1993 };
1994
1995 sdio0_bus4: sdio0-bus4 {
1996 rockchip,pins =
1997 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
1998 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
1999 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2000 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2001 };
2002
2003 sdio0_cmd: sdio0-cmd {
2004 rockchip,pins =
2005 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2006 };
2007
2008 sdio0_clk: sdio0-clk {
2009 rockchip,pins =
2010 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2011 };
2012
2013 sdio0_cd: sdio0-cd {
2014 rockchip,pins =
2015 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2016 };
2017
2018 sdio0_pwr: sdio0-pwr {
2019 rockchip,pins =
2020 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2021 };
2022
2023 sdio0_bkpwr: sdio0-bkpwr {
2024 rockchip,pins =
2025 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2026 };
2027
2028 sdio0_wp: sdio0-wp {
2029 rockchip,pins =
2030 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2031 };
2032
2033 sdio0_int: sdio0-int {
2034 rockchip,pins =
2035 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2036 };
2037 };
2038
2039 sdmmc {
2040 sdmmc_bus1: sdmmc-bus1 {
2041 rockchip,pins =
2042 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2043 };
2044
2045 sdmmc_bus4: sdmmc-bus4 {
2046 rockchip,pins =
2047 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2048 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2049 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2050 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2051 };
2052
2053 sdmmc_clk: sdmmc-clk {
2054 rockchip,pins =
2055 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2056 };
2057
2058 sdmmc_cmd: sdmmc-cmd {
2059 rockchip,pins =
2060 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2061 };
2062
2063 sdmmc_cd: sdmmc-cd {
2064 rockchip,pins =
2065 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2066 };
2067
2068 sdmmc_wp: sdmmc-wp {
2069 rockchip,pins =
2070 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2071 };
2072 };
2073
2074 sleep {
2075 ap_pwroff: ap-pwroff {
2076 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2077 };
2078
2079 ddrio_pwroff: ddrio-pwroff {
2080 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2081 };
2082 };
2083
2084 spdif {
2085 spdif_bus: spdif-bus {
2086 rockchip,pins =
2087 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2088 };
2089
2090 spdif_bus_1: spdif-bus-1 {
2091 rockchip,pins =
2092 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2093 };
2094 };
2095
2096 spi0 {
2097 spi0_clk: spi0-clk {
2098 rockchip,pins =
2099 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2100 };
2101 spi0_cs0: spi0-cs0 {
2102 rockchip,pins =
2103 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2104 };
2105 spi0_cs1: spi0-cs1 {
2106 rockchip,pins =
2107 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2108 };
2109 spi0_tx: spi0-tx {
2110 rockchip,pins =
2111 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2112 };
2113 spi0_rx: spi0-rx {
2114 rockchip,pins =
2115 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2116 };
2117 };
2118
2119 spi1 {
2120 spi1_clk: spi1-clk {
2121 rockchip,pins =
2122 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2123 };
2124 spi1_cs0: spi1-cs0 {
2125 rockchip,pins =
2126 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2127 };
2128 spi1_rx: spi1-rx {
2129 rockchip,pins =
2130 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2131 };
2132 spi1_tx: spi1-tx {
2133 rockchip,pins =
2134 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2135 };
2136 };
2137
2138 spi2 {
2139 spi2_clk: spi2-clk {
2140 rockchip,pins =
2141 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2142 };
2143 spi2_cs0: spi2-cs0 {
2144 rockchip,pins =
2145 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2146 };
2147 spi2_rx: spi2-rx {
2148 rockchip,pins =
2149 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2150 };
2151 spi2_tx: spi2-tx {
2152 rockchip,pins =
2153 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2154 };
2155 };
2156
2157 spi3 {
2158 spi3_clk: spi3-clk {
2159 rockchip,pins =
2160 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2161 };
2162 spi3_cs0: spi3-cs0 {
2163 rockchip,pins =
2164 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2165 };
2166 spi3_rx: spi3-rx {
2167 rockchip,pins =
2168 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2169 };
2170 spi3_tx: spi3-tx {
2171 rockchip,pins =
2172 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2173 };
2174 };
2175
2176 spi4 {
2177 spi4_clk: spi4-clk {
2178 rockchip,pins =
2179 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2180 };
2181 spi4_cs0: spi4-cs0 {
2182 rockchip,pins =
2183 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2184 };
2185 spi4_rx: spi4-rx {
2186 rockchip,pins =
2187 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2188 };
2189 spi4_tx: spi4-tx {
2190 rockchip,pins =
2191 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2192 };
2193 };
2194
2195 spi5 {
2196 spi5_clk: spi5-clk {
2197 rockchip,pins =
2198 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2199 };
2200 spi5_cs0: spi5-cs0 {
2201 rockchip,pins =
2202 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2203 };
2204 spi5_rx: spi5-rx {
2205 rockchip,pins =
2206 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2207 };
2208 spi5_tx: spi5-tx {
2209 rockchip,pins =
2210 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2211 };
2212 };
2213
2214 tsadc {
2215 otp_gpio: otp-gpio {
2216 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2217 };
2218
2219 otp_out: otp-out {
2220 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2221 };
2222 };
2223
2224 uart0 {
2225 uart0_xfer: uart0-xfer {
2226 rockchip,pins =
2227 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2228 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2229 };
2230
2231 uart0_cts: uart0-cts {
2232 rockchip,pins =
2233 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2234 };
2235
2236 uart0_rts: uart0-rts {
2237 rockchip,pins =
2238 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2239 };
2240 };
2241
2242 uart1 {
2243 uart1_xfer: uart1-xfer {
2244 rockchip,pins =
2245 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2246 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2247 };
2248 };
2249
2250 uart2a {
2251 uart2a_xfer: uart2a-xfer {
2252 rockchip,pins =
2253 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2254 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2255 };
2256 };
2257
2258 uart2b {
2259 uart2b_xfer: uart2b-xfer {
2260 rockchip,pins =
2261 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2262 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2263 };
2264 };
2265
2266 uart2c {
2267 uart2c_xfer: uart2c-xfer {
2268 rockchip,pins =
2269 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2270 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2271 };
2272 };
2273
2274 uart3 {
2275 uart3_xfer: uart3-xfer {
2276 rockchip,pins =
2277 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2278 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2279 };
2280
2281 uart3_cts: uart3-cts {
2282 rockchip,pins =
2283 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2284 };
2285
2286 uart3_rts: uart3-rts {
2287 rockchip,pins =
2288 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2289 };
2290 };
2291
2292 uart4 {
2293 uart4_xfer: uart4-xfer {
2294 rockchip,pins =
2295 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2296 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2297 };
2298 };
2299
2300 uarthdcp {
2301 uarthdcp_xfer: uarthdcp-xfer {
2302 rockchip,pins =
2303 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2304 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2305 };
2306 };
2307
2308 pwm0 {
2309 pwm0_pin: pwm0-pin {
2310 rockchip,pins =
2311 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2312 };
2313
2314 vop0_pwm_pin: vop0-pwm-pin {
2315 rockchip,pins =
2316 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2317 };
2318 };
2319
2320 pwm1 {
2321 pwm1_pin: pwm1-pin {
2322 rockchip,pins =
2323 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2324 };
2325
2326 vop1_pwm_pin: vop1-pwm-pin {
2327 rockchip,pins =
2328 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2329 };
2330 };
2331
2332 pwm2 {
2333 pwm2_pin: pwm2-pin {
2334 rockchip,pins =
2335 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2336 };
2337 };
2338
2339 pwm3a {
2340 pwm3a_pin: pwm3a-pin {
2341 rockchip,pins =
2342 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2343 };
2344 };
2345
2346 pwm3b {
2347 pwm3b_pin: pwm3b-pin {
2348 rockchip,pins =
2349 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2350 };
2351 };
2352
2353 hdmi {
2354 hdmi_i2c_xfer: hdmi-i2c-xfer {
2355 rockchip,pins =
2356 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2357 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2358 };
2359
2360 hdmi_cec: hdmi-cec {
2361 rockchip,pins =
2362 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2363 };
2364 };
2365
2366 pcie {
2367 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2368 rockchip,pins =
2369 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2370 };
2371
2372 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2373 rockchip,pins =
2374 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2375 };
2376 };
2377
2378 };
2379 };
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