2 * Device Tree Source for UniPhier PXs3 SoC
4 * Copyright (C) 2017 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #include <dt-bindings/gpio/gpio.h>
12 /memreserve/ 0x80000000 0x02000000;
15 compatible = "socionext,uniphier-pxs3";
18 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a53", "arm,armv8";
45 clocks = <&sys_clk 33>;
46 enable-method = "psci";
47 operating-points-v2 = <&cluster0_opp>;
52 compatible = "arm,cortex-a53", "arm,armv8";
54 clocks = <&sys_clk 33>;
55 enable-method = "psci";
56 operating-points-v2 = <&cluster0_opp>;
61 compatible = "arm,cortex-a53", "arm,armv8";
63 clocks = <&sys_clk 33>;
64 enable-method = "psci";
65 operating-points-v2 = <&cluster0_opp>;
70 compatible = "arm,cortex-a53", "arm,armv8";
72 clocks = <&sys_clk 33>;
73 enable-method = "psci";
74 operating-points-v2 = <&cluster0_opp>;
78 cluster0_opp: opp-table {
79 compatible = "operating-points-v2";
83 opp-hz = /bits/ 64 <250000000>;
84 clock-latency-ns = <300>;
87 opp-hz = /bits/ 64 <325000000>;
88 clock-latency-ns = <300>;
91 opp-hz = /bits/ 64 <500000000>;
92 clock-latency-ns = <300>;
95 opp-hz = /bits/ 64 <650000000>;
96 clock-latency-ns = <300>;
99 opp-hz = /bits/ 64 <666667000>;
100 clock-latency-ns = <300>;
103 opp-hz = /bits/ 64 <866667000>;
104 clock-latency-ns = <300>;
107 opp-hz = /bits/ 64 <1000000000>;
108 clock-latency-ns = <300>;
111 opp-hz = /bits/ 64 <1300000000>;
112 clock-latency-ns = <300>;
117 compatible = "arm,psci-1.0";
123 compatible = "fixed-clock";
125 clock-frequency = <25000000>;
129 emmc_pwrseq: emmc-pwrseq {
130 compatible = "mmc-pwrseq-emmc";
131 reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
135 compatible = "arm,armv8-timer";
136 interrupts = <1 13 4>,
143 compatible = "simple-bus";
144 #address-cells = <1>;
146 ranges = <0 0 0 0xffffffff>;
148 serial0: serial@54006800 {
149 compatible = "socionext,uniphier-uart";
151 reg = <0x54006800 0x40>;
152 interrupts = <0 33 4>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uart0>;
155 clocks = <&peri_clk 0>;
156 resets = <&peri_rst 0>;
159 serial1: serial@54006900 {
160 compatible = "socionext,uniphier-uart";
162 reg = <0x54006900 0x40>;
163 interrupts = <0 35 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_uart1>;
166 clocks = <&peri_clk 1>;
167 resets = <&peri_rst 1>;
170 serial2: serial@54006a00 {
171 compatible = "socionext,uniphier-uart";
173 reg = <0x54006a00 0x40>;
174 interrupts = <0 37 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_uart2>;
177 clocks = <&peri_clk 2>;
178 resets = <&peri_rst 2>;
181 serial3: serial@54006b00 {
182 compatible = "socionext,uniphier-uart";
184 reg = <0x54006b00 0x40>;
185 interrupts = <0 177 4>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart3>;
188 clocks = <&peri_clk 3>;
189 resets = <&peri_rst 3>;
192 gpio: gpio@55000000 {
193 compatible = "socionext,uniphier-gpio";
194 reg = <0x55000000 0x200>;
195 interrupt-parent = <&aidet>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
200 gpio-ranges = <&pinctrl 0 0 0>,
203 gpio-ranges-group-names = "gpio_range0",
207 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
212 compatible = "socionext,uniphier-fi2c";
214 reg = <0x58780000 0x80>;
215 #address-cells = <1>;
217 interrupts = <0 41 4>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_i2c0>;
220 clocks = <&peri_clk 4>;
221 resets = <&peri_rst 4>;
222 clock-frequency = <100000>;
226 compatible = "socionext,uniphier-fi2c";
228 reg = <0x58781000 0x80>;
229 #address-cells = <1>;
231 interrupts = <0 42 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_i2c1>;
234 clocks = <&peri_clk 5>;
235 resets = <&peri_rst 5>;
236 clock-frequency = <100000>;
240 compatible = "socionext,uniphier-fi2c";
242 reg = <0x58782000 0x80>;
243 #address-cells = <1>;
245 interrupts = <0 43 4>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_i2c2>;
248 clocks = <&peri_clk 6>;
249 resets = <&peri_rst 6>;
250 clock-frequency = <100000>;
254 compatible = "socionext,uniphier-fi2c";
256 reg = <0x58783000 0x80>;
257 #address-cells = <1>;
259 interrupts = <0 44 4>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_i2c3>;
262 clocks = <&peri_clk 7>;
263 resets = <&peri_rst 7>;
264 clock-frequency = <100000>;
267 /* chip-internal connection for HDMI */
269 compatible = "socionext,uniphier-fi2c";
270 reg = <0x58786000 0x80>;
271 #address-cells = <1>;
273 interrupts = <0 26 4>;
274 clocks = <&peri_clk 10>;
275 resets = <&peri_rst 10>;
276 clock-frequency = <400000>;
279 system_bus: system-bus@58c00000 {
280 compatible = "socionext,uniphier-system-bus";
282 reg = <0x58c00000 0x400>;
283 #address-cells = <2>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_system_bus>;
290 compatible = "socionext,uniphier-smpctrl";
291 reg = <0x59801000 0x400>;
295 compatible = "socionext,uniphier-pxs3-sdctrl",
296 "simple-mfd", "syscon";
297 reg = <0x59810000 0x400>;
300 compatible = "socionext,uniphier-pxs3-sd-clock";
305 compatible = "socionext,uniphier-pxs3-sd-reset";
311 compatible = "socionext,uniphier-pxs3-perictrl",
312 "simple-mfd", "syscon";
313 reg = <0x59820000 0x200>;
316 compatible = "socionext,uniphier-pxs3-peri-clock";
321 compatible = "socionext,uniphier-pxs3-peri-reset";
326 emmc: sdhc@5a000000 {
327 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
328 reg = <0x5a000000 0x400>;
329 interrupts = <0 78 4>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_emmc>;
332 clocks = <&sys_clk 4>;
333 resets = <&sys_rst 4>;
337 mmc-pwrseq = <&emmc_pwrseq>;
338 cdns,phy-input-delay-legacy = <4>;
339 cdns,phy-input-delay-mmc-highspeed = <2>;
340 cdns,phy-input-delay-mmc-ddr = <3>;
341 cdns,phy-dll-delay-sdclk = <21>;
342 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
346 compatible = "socionext,uniphier-pxs3-soc-glue",
347 "simple-mfd", "syscon";
348 reg = <0x5f800000 0x2000>;
351 compatible = "socionext,uniphier-pxs3-pinctrl";
356 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
358 #address-cells = <1>;
360 ranges = <0 0x5f900000 0x2000>;
363 compatible = "socionext,uniphier-efuse";
368 compatible = "socionext,uniphier-efuse";
373 aidet: aidet@5fc20000 {
374 compatible = "socionext,uniphier-pxs3-aidet";
375 reg = <0x5fc20000 0x200>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
380 gic: interrupt-controller@5fe00000 {
381 compatible = "arm,gic-v3";
382 reg = <0x5fe00000 0x10000>, /* GICD */
383 <0x5fe80000 0x80000>; /* GICR */
384 interrupt-controller;
385 #interrupt-cells = <3>;
386 interrupts = <1 9 4>;
390 compatible = "socionext,uniphier-pxs3-sysctrl",
391 "simple-mfd", "syscon";
392 reg = <0x61840000 0x10000>;
395 compatible = "socionext,uniphier-pxs3-clock";
400 compatible = "socionext,uniphier-pxs3-reset";
405 compatible = "socionext,uniphier-wdt";
409 nand: nand@68000000 {
410 compatible = "socionext,uniphier-denali-nand-v5b";
412 reg-names = "nand_data", "denali_reg";
413 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
414 interrupts = <0 65 4>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_nand>;
417 clocks = <&sys_clk 2>;
418 resets = <&sys_rst 2>;
423 #include "uniphier-pinctrl.dtsi"