arch/arm64/boot/dts/xilinx/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  */
  13
  14 / {
  15         compatible = "xlnx,zynqmp";
  16         #address-cells = <2>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a53", "arm,armv8";
  25                         device_type = "cpu";
  26                         enable-method = "psci";
  27                         reg = <0x0>;
  28                 };
  29
  30                 cpu@1 {
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         device_type = "cpu";
  33                         enable-method = "psci";
  34                         reg = <0x1>;
  35                 };
  36
  37                 cpu@2 {
  38                         compatible = "arm,cortex-a53", "arm,armv8";
  39                         device_type = "cpu";
  40                         enable-method = "psci";
  41                         reg = <0x2>;
  42                 };
  43
  44                 cpu@3 {
  45                         compatible = "arm,cortex-a53", "arm,armv8";
  46                         device_type = "cpu";
  47                         enable-method = "psci";
  48                         reg = <0x3>;
  49                 };
  50         };
  51
  52         pmu {
  53                 compatible = "arm,armv8-pmuv3";
  54                 interrupts = <0 143 4>,
  55                              <0 144 4>,
  56                              <0 145 4>,
  57                              <0 146 4>;
  58         };
  59
  60         psci {
  61                 compatible = "arm,psci-0.2";
  62                 method = "smc";
  63         };
  64
  65         timer {
  66                 compatible = "arm,armv8-timer";
  67                 interrupt-parent = <&gic>;
  68                 interrupts = <1 13 0xf01>,
  69                              <1 14 0xf01>,
  70                              <1 11 0xf01>,
  71                              <1 10 0xf01>;
  72         };
  73
  74         amba_apu {
  75                 compatible = "simple-bus";
  76                 #address-cells = <2>;
  77                 #size-cells = <1>;
  78                 ranges;
  79
  80                 gic: interrupt-controller@f9010000 {
  81                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
  82                         #interrupt-cells = <3>;
  83                         reg = <0x0 0xf9010000 0x10000>,
  84                               <0x0 0xf902f000 0x2000>,
  85                               <0x0 0xf9040000 0x20000>,
  86                               <0x0 0xf906f000 0x2000>;
  87                         interrupt-controller;
  88                         interrupt-parent = <&gic>;
  89                         interrupts = <1 9 0xf04>;
  90                 };
  91         };
  92
  93         amba {
  94                 compatible = "simple-bus";
  95                 #address-cells = <2>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 can0: can@ff060000 {
 100                         compatible = "xlnx,zynq-can-1.0";
 101                         status = "disabled";
 102                         clocks = <&misc_clk &misc_clk>;
 103                         clock-names = "can_clk", "pclk";
 104                         reg = <0x0 0xff060000 0x1000>;
 105                         interrupts = <0 23 4>;
 106                         interrupt-parent = <&gic>;
 107                         tx-fifo-depth = <0x40>;
 108                         rx-fifo-depth = <0x40>;
 109                 };
 110
 111                 can1: can@ff070000 {
 112                         compatible = "xlnx,zynq-can-1.0";
 113                         status = "disabled";
 114                         clocks = <&misc_clk &misc_clk>;
 115                         clock-names = "can_clk", "pclk";
 116                         reg = <0x0 0xff070000 0x1000>;
 117                         interrupts = <0 24 4>;
 118                         interrupt-parent = <&gic>;
 119                         tx-fifo-depth = <0x40>;
 120                         rx-fifo-depth = <0x40>;
 121                 };
 122
 123                 misc_clk: misc_clk {
 124                         compatible = "fixed-clock";
 125                         #clock-cells = <0>;
 126                         clock-frequency = <25000000>;
 127                 };
 128
 129                 gpio: gpio@ff0a0000 {
 130                         compatible = "xlnx,zynqmp-gpio-1.0";
 131                         status = "disabled";
 132                         #gpio-cells = <0x2>;
 133                         clocks = <&misc_clk>;
 134                         interrupt-parent = <&gic>;
 135                         interrupts = <0 16 4>;
 136                         reg = <0x0 0xff0a0000 0x1000>;
 137                 };
 138
 139                 gem0: ethernet@ff0b0000 {
 140                         compatible = "cdns,gem";
 141                         status = "disabled";
 142                         interrupt-parent = <&gic>;
 143                         interrupts = <0 57 4>, <0 57 4>;
 144                         reg = <0x0 0xff0b0000 0x1000>;
 145                         clock-names = "pclk", "hclk", "tx_clk";
 146                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                 };
 150
 151                 gem1: ethernet@ff0c0000 {
 152                         compatible = "cdns,gem";
 153                         status = "disabled";
 154                         interrupt-parent = <&gic>;
 155                         interrupts = <0 59 4>, <0 59 4>;
 156                         reg = <0x0 0xff0c0000 0x1000>;
 157                         clock-names = "pclk", "hclk", "tx_clk";
 158                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                 };
 162
 163                 gem2: ethernet@ff0d0000 {
 164                         compatible = "cdns,gem";
 165                         status = "disabled";
 166                         interrupt-parent = <&gic>;
 167                         interrupts = <0 61 4>, <0 61 4>;
 168                         reg = <0x0 0xff0d0000 0x1000>;
 169                         clock-names = "pclk", "hclk", "tx_clk";
 170                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                 };
 174
 175                 gem3: ethernet@ff0e0000 {
 176                         compatible = "cdns,gem";
 177                         status = "disabled";
 178                         interrupt-parent = <&gic>;
 179                         interrupts = <0 63 4>, <0 63 4>;
 180                         reg = <0x0 0xff0e0000 0x1000>;
 181                         clock-names = "pclk", "hclk", "tx_clk";
 182                         clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 183                         #address-cells = <1>;
 184                         #size-cells = <0>;
 185                 };
 186
 187                 i2c_clk: i2c_clk {
 188                         compatible = "fixed-clock";
 189                         #clock-cells = <0x0>;
 190                         clock-frequency = <111111111>;
 191                 };
 192
 193                 i2c0: i2c@ff020000 {
 194                         compatible = "cdns,i2c-r1p10";
 195                         status = "disabled";
 196                         interrupt-parent = <&gic>;
 197                         interrupts = <0 17 4>;
 198                         reg = <0x0 0xff020000 0x1000>;
 199                         clocks = <&i2c_clk>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                 };
 203
 204                 i2c1: i2c@ff030000 {
 205                         compatible = "cdns,i2c-r1p10";
 206                         status = "disabled";
 207                         interrupt-parent = <&gic>;
 208                         interrupts = <0 18 4>;
 209                         reg = <0x0 0xff030000 0x1000>;
 210                         clocks = <&i2c_clk>;
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                 };
 214
 215                 sata_clk: sata_clk {
 216                         compatible = "fixed-clock";
 217                         #clock-cells = <0>;
 218                         clock-frequency = <75000000>;
 219                 };
 220
 221                 sata: ahci@fd0c0000 {
 222                         compatible = "ceva,ahci-1v84";
 223                         status = "disabled";
 224                         reg = <0x0 0xfd0c0000 0x2000>;
 225                         interrupt-parent = <&gic>;
 226                         interrupts = <0 133 4>;
 227                         clocks = <&sata_clk>;
 228                 };
 229
 230                 sdhci0: sdhci@ff160000 {
 231                         compatible = "arasan,sdhci-8.9a";
 232                         status = "disabled";
 233                         interrupt-parent = <&gic>;
 234                         interrupts = <0 48 4>;
 235                         reg = <0x0 0xff160000 0x1000>;
 236                         clock-names = "clk_xin", "clk_ahb";
 237                         clocks = <&misc_clk>, <&misc_clk>;
 238                 };
 239
 240                 sdhci1: sdhci@ff170000 {
 241                         compatible = "arasan,sdhci-8.9a";
 242                         status = "disabled";
 243                         interrupt-parent = <&gic>;
 244                         interrupts = <0 49 4>;
 245                         reg = <0x0 0xff170000 0x1000>;
 246                         clock-names = "clk_xin", "clk_ahb";
 247                         clocks = <&misc_clk>, <&misc_clk>;
 248                 };
 249
 250                 smmu: smmu@fd800000 {
 251                         compatible = "arm,mmu-500";
 252                         reg = <0x0 0xfd800000 0x20000>;
 253                         #global-interrupts = <1>;
 254                         interrupt-parent = <&gic>;
 255                         interrupts = <0 157 4>,
 256                                 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
 257                                 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
 258                                 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
 259                                 <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
 260                 };
 261
 262                 spi0: spi@ff040000 {
 263                         compatible = "cdns,spi-r1p6";
 264                         status = "disabled";
 265                         interrupt-parent = <&gic>;
 266                         interrupts = <0 19 4>;
 267                         reg = <0x0 0xff040000 0x1000>;
 268                         clock-names = "ref_clk", "pclk";
 269                         clocks = <&misc_clk &misc_clk>;
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                 };
 273
 274                 spi1: spi@ff050000 {
 275                         compatible = "cdns,spi-r1p6";
 276                         status = "disabled";
 277                         interrupt-parent = <&gic>;
 278                         interrupts = <0 20 4>;
 279                         reg = <0x0 0xff050000 0x1000>;
 280                         clock-names = "ref_clk", "pclk";
 281                         clocks = <&misc_clk &misc_clk>;
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                 };
 285
 286                 ttc0: timer@ff110000 {
 287                         compatible = "cdns,ttc";
 288                         status = "disabled";
 289                         interrupt-parent = <&gic>;
 290                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 291                         reg = <0x0 0xff110000 0x1000>;
 292                         clocks = <&misc_clk>;
 293                         timer-width = <32>;
 294                 };
 295
 296                 ttc1: timer@ff120000 {
 297                         compatible = "cdns,ttc";
 298                         status = "disabled";
 299                         interrupt-parent = <&gic>;
 300                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 301                         reg = <0x0 0xff120000 0x1000>;
 302                         clocks = <&misc_clk>;
 303                         timer-width = <32>;
 304                 };
 305
 306                 ttc2: timer@ff130000 {
 307                         compatible = "cdns,ttc";
 308                         status = "disabled";
 309                         interrupt-parent = <&gic>;
 310                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 311                         reg = <0x0 0xff130000 0x1000>;
 312                         clocks = <&misc_clk>;
 313                         timer-width = <32>;
 314                 };
 315
 316                 ttc3: timer@ff140000 {
 317                         compatible = "cdns,ttc";
 318                         status = "disabled";
 319                         interrupt-parent = <&gic>;
 320                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 321                         reg = <0x0 0xff140000 0x1000>;
 322                         clocks = <&misc_clk>;
 323                         timer-width = <32>;
 324                 };
 325
 326                 uart0: serial@ff000000 {
 327                         compatible = "cdns,uart-r1p8";
 328                         status = "disabled";
 329                         interrupt-parent = <&gic>;
 330                         interrupts = <0 21 4>;
 331                         reg = <0x0 0xff000000 0x1000>;
 332                         clock-names = "uart_clk", "pclk";
 333                         clocks = <&misc_clk &misc_clk>;
 334                 };
 335
 336                 uart1: serial@ff010000 {
 337                         compatible = "cdns,uart-r1p8";
 338                         status = "disabled";
 339                         interrupt-parent = <&gic>;
 340                         interrupts = <0 22 4>;
 341                         reg = <0x0 0xff010000 0x1000>;
 342                         clock-names = "uart_clk", "pclk";
 343                         clocks = <&misc_clk &misc_clk>;
 344                 };
 345
 346                 usb0: usb@fe200000 {
 347                         compatible = "snps,dwc3";
 348                         status = "disabled";
 349                         interrupt-parent = <&gic>;
 350                         interrupts = <0 65 4>;
 351                         reg = <0x0 0xfe200000 0x40000>;
 352                         clock-names = "clk_xin", "clk_ahb";
 353                         clocks = <&misc_clk>, <&misc_clk>;
 354                 };
 355
 356                 usb1: usb@fe300000 {
 357                         compatible = "snps,dwc3";
 358                         status = "disabled";
 359                         interrupt-parent = <&gic>;
 360                         interrupts = <0 70 4>;
 361                         reg = <0x0 0xfe300000 0x40000>;
 362                         clock-names = "clk_xin", "clk_ahb";
 363                         clocks = <&misc_clk>, <&misc_clk>;
 364                 };
 365
 366                 watchdog0: watchdog@fd4d0000 {
 367                         compatible = "cdns,wdt-r1p2";
 368                         status = "disabled";
 369                         clocks= <&misc_clk>;
 370                         interrupt-parent = <&gic>;
 371                         interrupts = <0 52 1>;
 372                         reg = <0x0 0xfd4d0000 0x1000>;
 373                         timeout-sec = <10>;
 374                 };
 375         };
 376 };