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arm64: Change cpu_resume() to enable mmu early then access sleep_sp by va
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1 /*
2 * Copyright (C) 2014 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16 #ifndef __ASM_CPU_H
17 #define __ASM_CPU_H
18
19 #include <linux/cpu.h>
20 #include <linux/init.h>
21 #include <linux/percpu.h>
22
23 /*
24 * Records attributes of an individual CPU.
25 */
26 struct cpuinfo_arm64 {
27 struct cpu cpu;
28 u32 reg_ctr;
29 u32 reg_cntfrq;
30 u32 reg_dczid;
31 u32 reg_midr;
32
33 u64 reg_id_aa64dfr0;
34 u64 reg_id_aa64dfr1;
35 u64 reg_id_aa64isar0;
36 u64 reg_id_aa64isar1;
37 u64 reg_id_aa64mmfr0;
38 u64 reg_id_aa64mmfr1;
39 u64 reg_id_aa64mmfr2;
40 u64 reg_id_aa64pfr0;
41 u64 reg_id_aa64pfr1;
42
43 u32 reg_id_dfr0;
44 u32 reg_id_isar0;
45 u32 reg_id_isar1;
46 u32 reg_id_isar2;
47 u32 reg_id_isar3;
48 u32 reg_id_isar4;
49 u32 reg_id_isar5;
50 u32 reg_id_mmfr0;
51 u32 reg_id_mmfr1;
52 u32 reg_id_mmfr2;
53 u32 reg_id_mmfr3;
54 u32 reg_id_pfr0;
55 u32 reg_id_pfr1;
56
57 u32 reg_mvfr0;
58 u32 reg_mvfr1;
59 u32 reg_mvfr2;
60 };
61
62 DECLARE_PER_CPU(struct cpuinfo_arm64, cpu_data);
63
64 void cpuinfo_store_cpu(void);
65 void __init cpuinfo_store_boot_cpu(void);
66
67 void __init init_cpu_features(struct cpuinfo_arm64 *info);
68 void update_cpu_features(int cpu, struct cpuinfo_arm64 *info,
69 struct cpuinfo_arm64 *boot);
70
71 #endif /* __ASM_CPU_H */