arch/blackfin/Kconfig

   1 config MMU
   2         def_bool n
   3
   4 config FPU
   5         def_bool n
   6
   7 config RWSEM_GENERIC_SPINLOCK
   8         def_bool y
   9
  10 config RWSEM_XCHGADD_ALGORITHM
  11         def_bool n
  12
  13 config BLACKFIN
  14         def_bool y
  15         select HAVE_ARCH_KGDB
  16         select HAVE_ARCH_TRACEHOOK
  17         select HAVE_DYNAMIC_FTRACE
  18         select HAVE_FTRACE_MCOUNT_RECORD
  19         select HAVE_FUNCTION_GRAPH_TRACER
  20         select HAVE_FUNCTION_TRACER
  21         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  22         select HAVE_IDE
  23         select HAVE_KERNEL_GZIP if RAMKERNEL
  24         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  25         select HAVE_KERNEL_LZMA if RAMKERNEL
  26         select HAVE_KERNEL_LZO if RAMKERNEL
  27         select HAVE_OPROFILE
  28         select HAVE_PERF_EVENTS
  29         select ARCH_HAVE_CUSTOM_GPIO_H
  30         select ARCH_WANT_OPTIONAL_GPIOLIB
  31         select HAVE_UID16
  32         select HAVE_UNDERSCORE_SYMBOL_PREFIX
  33         select VIRT_TO_BUS
  34         select ARCH_WANT_IPC_PARSE_VERSION
  35         select HAVE_GENERIC_HARDIRQS
  36         select GENERIC_ATOMIC64
  37         select GENERIC_IRQ_PROBE
  38         select USE_GENERIC_SMP_HELPERS if SMP
  39         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  40         select GENERIC_SMP_IDLE_THREAD
  41         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  42         select HAVE_MOD_ARCH_SPECIFIC
  43         select MODULES_USE_ELF_RELA
  44
  45 config GENERIC_CSUM
  46         def_bool y
  47
  48 config GENERIC_BUG
  49         def_bool y
  50         depends on BUG
  51
  52 config ZONE_DMA
  53         def_bool y
  54
  55 config GENERIC_GPIO
  56         def_bool y
  57
  58 config FORCE_MAX_ZONEORDER
  59         int
  60         default "14"
  61
  62 config GENERIC_CALIBRATE_DELAY
  63         def_bool y
  64
  65 config LOCKDEP_SUPPORT
  66         def_bool y
  67
  68 config STACKTRACE_SUPPORT
  69         def_bool y
  70
  71 config TRACE_IRQFLAGS_SUPPORT
  72         def_bool y
  73
  74 source "init/Kconfig"
  75
  76 source "kernel/Kconfig.preempt"
  77
  78 source "kernel/Kconfig.freezer"
  79
  80 menu "Blackfin Processor Options"
  81
  82 comment "Processor and Board Settings"
  83
  84 choice
  85         prompt "CPU"
  86         default BF533
  87
  88 config BF512
  89         bool "BF512"
  90         help
  91           BF512 Processor Support.
  92
  93 config BF514
  94         bool "BF514"
  95         help
  96           BF514 Processor Support.
  97
  98 config BF516
  99         bool "BF516"
 100         help
 101           BF516 Processor Support.
 102
 103 config BF518
 104         bool "BF518"
 105         help
 106           BF518 Processor Support.
 107
 108 config BF522
 109         bool "BF522"
 110         help
 111           BF522 Processor Support.
 112
 113 config BF523
 114         bool "BF523"
 115         help
 116           BF523 Processor Support.
 117
 118 config BF524
 119         bool "BF524"
 120         help
 121           BF524 Processor Support.
 122
 123 config BF525
 124         bool "BF525"
 125         help
 126           BF525 Processor Support.
 127
 128 config BF526
 129         bool "BF526"
 130         help
 131           BF526 Processor Support.
 132
 133 config BF527
 134         bool "BF527"
 135         help
 136           BF527 Processor Support.
 137
 138 config BF531
 139         bool "BF531"
 140         help
 141           BF531 Processor Support.
 142
 143 config BF532
 144         bool "BF532"
 145         help
 146           BF532 Processor Support.
 147
 148 config BF533
 149         bool "BF533"
 150         help
 151           BF533 Processor Support.
 152
 153 config BF534
 154         bool "BF534"
 155         help
 156           BF534 Processor Support.
 157
 158 config BF536
 159         bool "BF536"
 160         help
 161           BF536 Processor Support.
 162
 163 config BF537
 164         bool "BF537"
 165         help
 166           BF537 Processor Support.
 167
 168 config BF538
 169         bool "BF538"
 170         help
 171           BF538 Processor Support.
 172
 173 config BF539
 174         bool "BF539"
 175         help
 176           BF539 Processor Support.
 177
 178 config BF542_std
 179         bool "BF542"
 180         help
 181           BF542 Processor Support.
 182
 183 config BF542M
 184         bool "BF542m"
 185         help
 186           BF542 Processor Support.
 187
 188 config BF544_std
 189         bool "BF544"
 190         help
 191           BF544 Processor Support.
 192
 193 config BF544M
 194         bool "BF544m"
 195         help
 196           BF544 Processor Support.
 197
 198 config BF547_std
 199         bool "BF547"
 200         help
 201           BF547 Processor Support.
 202
 203 config BF547M
 204         bool "BF547m"
 205         help
 206           BF547 Processor Support.
 207
 208 config BF548_std
 209         bool "BF548"
 210         help
 211           BF548 Processor Support.
 212
 213 config BF548M
 214         bool "BF548m"
 215         help
 216           BF548 Processor Support.
 217
 218 config BF549_std
 219         bool "BF549"
 220         help
 221           BF549 Processor Support.
 222
 223 config BF549M
 224         bool "BF549m"
 225         help
 226           BF549 Processor Support.
 227
 228 config BF561
 229         bool "BF561"
 230         help
 231           BF561 Processor Support.
 232
 233 config BF609
 234         bool "BF609"
 235         select CLKDEV_LOOKUP
 236         help
 237           BF609 Processor Support.
 238
 239 endchoice
 240
 241 config SMP
 242         depends on BF561
 243         select TICKSOURCE_CORETMR
 244         bool "Symmetric multi-processing support"
 245         ---help---
 246           This enables support for systems with more than one CPU,
 247           like the dual core BF561. If you have a system with only one
 248           CPU, say N. If you have a system with more than one CPU, say Y.
 249
 250           If you don't know what to do here, say N.
 251
 252 config NR_CPUS
 253         int
 254         depends on SMP
 255         default 2 if BF561
 256
 257 config HOTPLUG_CPU
 258         bool "Support for hot-pluggable CPUs"
 259         depends on SMP && HOTPLUG
 260         default y
 261
 262 config BF_REV_MIN
 263         int
 264         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 265         default 2 if (BF537 || BF536 || BF534)
 266         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 267         default 4 if (BF538 || BF539)
 268
 269 config BF_REV_MAX
 270         int
 271         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 272         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 273         default 5 if (BF561 || BF538 || BF539)
 274         default 6 if (BF533 || BF532 || BF531)
 275
 276 choice
 277         prompt "Silicon Rev"
 278         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 279         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 280         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 281
 282 config BF_REV_0_0
 283         bool "0.0"
 284         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 285
 286 config BF_REV_0_1
 287         bool "0.1"
 288         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 289
 290 config BF_REV_0_2
 291         bool "0.2"
 292         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 293
 294 config BF_REV_0_3
 295         bool "0.3"
 296         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 297
 298 config BF_REV_0_4
 299         bool "0.4"
 300         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
 301
 302 config BF_REV_0_5
 303         bool "0.5"
 304         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 305
 306 config BF_REV_0_6
 307         bool "0.6"
 308         depends on (BF533 || BF532 || BF531)
 309
 310 config BF_REV_ANY
 311         bool "any"
 312
 313 config BF_REV_NONE
 314         bool "none"
 315
 316 endchoice
 317
 318 config BF53x
 319         bool
 320         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 321         default y
 322
 323 config MEM_MT48LC64M4A2FB_7E
 324         bool
 325         depends on (BFIN533_STAMP)
 326         default y
 327
 328 config MEM_MT48LC16M16A2TG_75
 329         bool
 330         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 331                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 332                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 333                 || BFIN527_BLUETECHNIX_CM)
 334         default y
 335
 336 config MEM_MT48LC32M8A2_75
 337         bool
 338         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 339         default y
 340
 341 config MEM_MT48LC8M32B2B5_7
 342         bool
 343         depends on (BFIN561_BLUETECHNIX_CM)
 344         default y
 345
 346 config MEM_MT48LC32M16A2TG_75
 347         bool
 348         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 349         default y
 350
 351 config MEM_MT48H32M16LFCJ_75
 352         bool
 353         depends on (BFIN526_EZBRD)
 354         default y
 355
 356 config MEM_MT47H64M16
 357         bool
 358         depends on (BFIN609_EZKIT)
 359         default y
 360
 361 source "arch/blackfin/mach-bf518/Kconfig"
 362 source "arch/blackfin/mach-bf527/Kconfig"
 363 source "arch/blackfin/mach-bf533/Kconfig"
 364 source "arch/blackfin/mach-bf561/Kconfig"
 365 source "arch/blackfin/mach-bf537/Kconfig"
 366 source "arch/blackfin/mach-bf538/Kconfig"
 367 source "arch/blackfin/mach-bf548/Kconfig"
 368 source "arch/blackfin/mach-bf609/Kconfig"
 369
 370 menu "Board customizations"
 371
 372 config CMDLINE_BOOL
 373         bool "Default bootloader kernel arguments"
 374
 375 config CMDLINE
 376         string "Initial kernel command string"
 377         depends on CMDLINE_BOOL
 378         default "console=ttyBF0,57600"
 379         help
 380           If you don't have a boot loader capable of passing a command line string
 381           to the kernel, you may specify one here. As a minimum, you should specify
 382           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 383
 384 config BOOT_LOAD
 385         hex "Kernel load address for booting"
 386         default "0x1000"
 387         range 0x1000 0x20000000
 388         help
 389           This option allows you to set the load address of the kernel.
 390           This can be useful if you are on a board which has a small amount
 391           of memory or you wish to reserve some memory at the beginning of
 392           the address space.
 393
 394           Note that you need to keep this value above 4k (0x1000) as this
 395           memory region is used to capture NULL pointer references as well
 396           as some core kernel functions.
 397
 398 config PHY_RAM_BASE_ADDRESS
 399         hex "Physical RAM Base"
 400         default 0x0
 401         help
 402           set BF609 FPGA physical SRAM base address
 403
 404 config ROM_BASE
 405         hex "Kernel ROM Base"
 406         depends on ROMKERNEL
 407         default "0x20040040"
 408         range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 409         range 0x20000000 0x30000000 if (BF54x || BF561)
 410         range 0xB0000000 0xC0000000 if (BF60x)
 411         help
 412           Make sure your ROM base does not include any file-header
 413           information that is prepended to the kernel.
 414
 415           For example, the bootable U-Boot format (created with
 416           mkimage) has a 64 byte header (0x40).  So while the image
 417           you write to flash might start at say 0x20080000, you have
 418           to add 0x40 to get the kernel's ROM base as it will come
 419           after the header.
 420
 421 comment "Clock/PLL Setup"
 422
 423 config CLKIN_HZ
 424         int "Frequency of the crystal on the board in Hz"
 425         default "10000000" if BFIN532_IP0X
 426         default "11059200" if BFIN533_STAMP
 427         default "24576000" if PNAV10
 428         default "25000000" # most people use this
 429         default "27000000" if BFIN533_EZKIT
 430         default "30000000" if BFIN561_EZKIT
 431         default "24000000" if BFIN527_AD7160EVAL
 432         help
 433           The frequency of CLKIN crystal oscillator on the board in Hz.
 434           Warning: This value should match the crystal on the board. Otherwise,
 435           peripherals won't work properly.
 436
 437 config BFIN_KERNEL_CLOCK
 438         bool "Re-program Clocks while Kernel boots?"
 439         default n
 440         help
 441           This option decides if kernel clocks are re-programed from the
 442           bootloader settings. If the clocks are not set, the SDRAM settings
 443           are also not changed, and the Bootloader does 100% of the hardware
 444           configuration.
 445
 446 config PLL_BYPASS
 447         bool "Bypass PLL"
 448         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 449         default n
 450
 451 config CLKIN_HALF
 452         bool "Half Clock In"
 453         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 454         default n
 455         help
 456           If this is set the clock will be divided by 2, before it goes to the PLL.
 457
 458 config VCO_MULT
 459         int "VCO Multiplier"
 460         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 461         range 1 64
 462         default "22" if BFIN533_EZKIT
 463         default "45" if BFIN533_STAMP
 464         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 465         default "22" if BFIN533_BLUETECHNIX_CM
 466         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 467         default "20" if (BFIN561_EZKIT || BF609)
 468         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 469         default "25" if BFIN527_AD7160EVAL
 470         help
 471           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 472           PLL Frequency = (Crystal Frequency) * (this setting)
 473
 474 choice
 475         prompt "Core Clock Divider"
 476         depends on BFIN_KERNEL_CLOCK
 477         default CCLK_DIV_1
 478         help
 479           This sets the frequency of the core. It can be 1, 2, 4 or 8
 480           Core Frequency = (PLL frequency) / (this setting)
 481
 482 config CCLK_DIV_1
 483         bool "1"
 484
 485 config CCLK_DIV_2
 486         bool "2"
 487
 488 config CCLK_DIV_4
 489         bool "4"
 490
 491 config CCLK_DIV_8
 492         bool "8"
 493 endchoice
 494
 495 config SCLK_DIV
 496         int "System Clock Divider"
 497         depends on BFIN_KERNEL_CLOCK
 498         range 1 15
 499         default 4
 500         help
 501           This sets the frequency of the system clock (including SDRAM or DDR) on
 502           !BF60x else it set the clock for system buses and provides the
 503           source from which SCLK0 and SCLK1 are derived.
 504           This can be between 1 and 15
 505           System Clock = (PLL frequency) / (this setting)
 506
 507 config SCLK0_DIV
 508         int "System Clock0 Divider"
 509         depends on BFIN_KERNEL_CLOCK && BF60x
 510         range 1 15
 511         default 1
 512         help
 513           This sets the frequency of the system clock0 for PVP and all other
 514           peripherals not clocked by SCLK1.
 515           This can be between 1 and 15
 516           System Clock0 = (System Clock) / (this setting)
 517
 518 config SCLK1_DIV
 519         int "System Clock1 Divider"
 520         depends on BFIN_KERNEL_CLOCK && BF60x
 521         range 1 15
 522         default 1
 523         help
 524           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 525           This can be between 1 and 15
 526           System Clock1 = (System Clock) / (this setting)
 527
 528 config DCLK_DIV
 529         int "DDR Clock Divider"
 530         depends on BFIN_KERNEL_CLOCK && BF60x
 531         range 1 15
 532         default 2
 533         help
 534           This sets the frequency of the DDR memory.
 535           This can be between 1 and 15
 536           DDR Clock = (PLL frequency) / (this setting)
 537
 538 choice
 539         prompt "DDR SDRAM Chip Type"
 540         depends on BFIN_KERNEL_CLOCK
 541         depends on BF54x
 542         default MEM_MT46V32M16_5B
 543
 544 config MEM_MT46V32M16_6T
 545         bool "MT46V32M16_6T"
 546
 547 config MEM_MT46V32M16_5B
 548         bool "MT46V32M16_5B"
 549 endchoice
 550
 551 choice
 552         prompt "DDR/SDRAM Timing"
 553         depends on BFIN_KERNEL_CLOCK && !BF60x
 554         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 555         help
 556           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 557           The calculated SDRAM timing parameters may not be 100%
 558           accurate - This option is therefore marked experimental.
 559
 560 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 561         bool "Calculate Timings"
 562
 563 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 564         bool "Provide accurate Timings based on target SCLK"
 565         help
 566           Please consult the Blackfin Hardware Reference Manuals as well
 567           as the memory device datasheet.
 568           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 569 endchoice
 570
 571 menu "Memory Init Control"
 572         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 573
 574 config MEM_DDRCTL0
 575         depends on BF54x
 576         hex "DDRCTL0"
 577         default 0x0
 578
 579 config MEM_DDRCTL1
 580         depends on BF54x
 581         hex "DDRCTL1"
 582         default 0x0
 583
 584 config MEM_DDRCTL2
 585         depends on BF54x
 586         hex "DDRCTL2"
 587         default 0x0
 588
 589 config MEM_EBIU_DDRQUE
 590         depends on BF54x
 591         hex "DDRQUE"
 592         default 0x0
 593
 594 config MEM_SDRRC
 595         depends on !BF54x
 596         hex "SDRRC"
 597         default 0x0
 598
 599 config MEM_SDGCTL
 600         depends on !BF54x
 601         hex "SDGCTL"
 602         default 0x0
 603 endmenu
 604
 605 #
 606 # Max & Min Speeds for various Chips
 607 #
 608 config MAX_VCO_HZ
 609         int
 610         default 400000000 if BF512
 611         default 400000000 if BF514
 612         default 400000000 if BF516
 613         default 400000000 if BF518
 614         default 400000000 if BF522
 615         default 600000000 if BF523
 616         default 400000000 if BF524
 617         default 600000000 if BF525
 618         default 400000000 if BF526
 619         default 600000000 if BF527
 620         default 400000000 if BF531
 621         default 400000000 if BF532
 622         default 750000000 if BF533
 623         default 500000000 if BF534
 624         default 400000000 if BF536
 625         default 600000000 if BF537
 626         default 533333333 if BF538
 627         default 533333333 if BF539
 628         default 600000000 if BF542
 629         default 533333333 if BF544
 630         default 600000000 if BF547
 631         default 600000000 if BF548
 632         default 533333333 if BF549
 633         default 600000000 if BF561
 634         default 800000000 if BF609
 635
 636 config MIN_VCO_HZ
 637         int
 638         default 50000000
 639
 640 config MAX_SCLK_HZ
 641         int
 642         default 200000000 if BF609
 643         default 133333333
 644
 645 config MIN_SCLK_HZ
 646         int
 647         default 27000000
 648
 649 comment "Kernel Timer/Scheduler"
 650
 651 source kernel/Kconfig.hz
 652
 653 config SET_GENERIC_CLOCKEVENTS
 654         bool "Generic clock events"
 655         default y
 656         select GENERIC_CLOCKEVENTS
 657
 658 menu "Clock event device"
 659         depends on GENERIC_CLOCKEVENTS
 660 config TICKSOURCE_GPTMR0
 661         bool "GPTimer0"
 662         depends on !SMP
 663         select BFIN_GPTIMERS
 664
 665 config TICKSOURCE_CORETMR
 666         bool "Core timer"
 667         default y
 668 endmenu
 669
 670 menu "Clock souce"
 671         depends on GENERIC_CLOCKEVENTS
 672 config CYCLES_CLOCKSOURCE
 673         bool "CYCLES"
 674         default y
 675         depends on !BFIN_SCRATCH_REG_CYCLES
 676         depends on !SMP
 677         help
 678           If you say Y here, you will enable support for using the 'cycles'
 679           registers as a clock source.  Doing so means you will be unable to
 680           safely write to the 'cycles' register during runtime.  You will
 681           still be able to read it (such as for performance monitoring), but
 682           writing the registers will most likely crash the kernel.
 683
 684 config GPTMR0_CLOCKSOURCE
 685         bool "GPTimer0"
 686         select BFIN_GPTIMERS
 687         depends on !TICKSOURCE_GPTMR0
 688 endmenu
 689
 690 comment "Misc"
 691
 692 choice
 693         prompt "Blackfin Exception Scratch Register"
 694         default BFIN_SCRATCH_REG_RETN
 695         help
 696           Select the resource to reserve for the Exception handler:
 697             - RETN: Non-Maskable Interrupt (NMI)
 698             - RETE: Exception Return (JTAG/ICE)
 699             - CYCLES: Performance counter
 700
 701           If you are unsure, please select "RETN".
 702
 703 config BFIN_SCRATCH_REG_RETN
 704         bool "RETN"
 705         help
 706           Use the RETN register in the Blackfin exception handler
 707           as a stack scratch register.  This means you cannot
 708           safely use NMI on the Blackfin while running Linux, but
 709           you can debug the system with a JTAG ICE and use the
 710           CYCLES performance registers.
 711
 712           If you are unsure, please select "RETN".
 713
 714 config BFIN_SCRATCH_REG_RETE
 715         bool "RETE"
 716         help
 717           Use the RETE register in the Blackfin exception handler
 718           as a stack scratch register.  This means you cannot
 719           safely use a JTAG ICE while debugging a Blackfin board,
 720           but you can safely use the CYCLES performance registers
 721           and the NMI.
 722
 723           If you are unsure, please select "RETN".
 724
 725 config BFIN_SCRATCH_REG_CYCLES
 726         bool "CYCLES"
 727         help
 728           Use the CYCLES register in the Blackfin exception handler
 729           as a stack scratch register.  This means you cannot
 730           safely use the CYCLES performance registers on a Blackfin
 731           board at anytime, but you can debug the system with a JTAG
 732           ICE and use the NMI.
 733
 734           If you are unsure, please select "RETN".
 735
 736 endchoice
 737
 738 endmenu
 739
 740
 741 menu "Blackfin Kernel Optimizations"
 742
 743 comment "Memory Optimizations"
 744
 745 config I_ENTRY_L1
 746         bool "Locate interrupt entry code in L1 Memory"
 747         default y
 748         depends on !SMP
 749         help
 750           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 751           into L1 instruction memory. (less latency)
 752
 753 config EXCPT_IRQ_SYSC_L1
 754         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 755         default y
 756         depends on !SMP
 757         help
 758           If enabled, the entire ASM lowlevel exception and interrupt entry code
 759           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 760           (less latency)
 761
 762 config DO_IRQ_L1
 763         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 764         default y
 765         depends on !SMP
 766         help
 767           If enabled, the frequently called do_irq dispatcher function is linked
 768           into L1 instruction memory. (less latency)
 769
 770 config CORE_TIMER_IRQ_L1
 771         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 772         default y
 773         depends on !SMP
 774         help
 775           If enabled, the frequently called timer_interrupt() function is linked
 776           into L1 instruction memory. (less latency)
 777
 778 config IDLE_L1
 779         bool "Locate frequently idle function in L1 Memory"
 780         default y
 781         depends on !SMP
 782         help
 783           If enabled, the frequently called idle function is linked
 784           into L1 instruction memory. (less latency)
 785
 786 config SCHEDULE_L1
 787         bool "Locate kernel schedule function in L1 Memory"
 788         default y
 789         depends on !SMP
 790         help
 791           If enabled, the frequently called kernel schedule is linked
 792           into L1 instruction memory. (less latency)
 793
 794 config ARITHMETIC_OPS_L1
 795         bool "Locate kernel owned arithmetic functions in L1 Memory"
 796         default y
 797         depends on !SMP
 798         help
 799           If enabled, arithmetic functions are linked
 800           into L1 instruction memory. (less latency)
 801
 802 config ACCESS_OK_L1
 803         bool "Locate access_ok function in L1 Memory"
 804         default y
 805         depends on !SMP
 806         help
 807           If enabled, the access_ok function is linked
 808           into L1 instruction memory. (less latency)
 809
 810 config MEMSET_L1
 811         bool "Locate memset function in L1 Memory"
 812         default y
 813         depends on !SMP
 814         help
 815           If enabled, the memset function is linked
 816           into L1 instruction memory. (less latency)
 817
 818 config MEMCPY_L1
 819         bool "Locate memcpy function in L1 Memory"
 820         default y
 821         depends on !SMP
 822         help
 823           If enabled, the memcpy function is linked
 824           into L1 instruction memory. (less latency)
 825
 826 config STRCMP_L1
 827         bool "locate strcmp function in L1 Memory"
 828         default y
 829         depends on !SMP
 830         help
 831           If enabled, the strcmp function is linked
 832           into L1 instruction memory (less latency).
 833
 834 config STRNCMP_L1
 835         bool "locate strncmp function in L1 Memory"
 836         default y
 837         depends on !SMP
 838         help
 839           If enabled, the strncmp function is linked
 840           into L1 instruction memory (less latency).
 841
 842 config STRCPY_L1
 843         bool "locate strcpy function in L1 Memory"
 844         default y
 845         depends on !SMP
 846         help
 847           If enabled, the strcpy function is linked
 848           into L1 instruction memory (less latency).
 849
 850 config STRNCPY_L1
 851         bool "locate strncpy function in L1 Memory"
 852         default y
 853         depends on !SMP
 854         help
 855           If enabled, the strncpy function is linked
 856           into L1 instruction memory (less latency).
 857
 858 config SYS_BFIN_SPINLOCK_L1
 859         bool "Locate sys_bfin_spinlock function in L1 Memory"
 860         default y
 861         depends on !SMP
 862         help
 863           If enabled, sys_bfin_spinlock function is linked
 864           into L1 instruction memory. (less latency)
 865
 866 config IP_CHECKSUM_L1
 867         bool "Locate IP Checksum function in L1 Memory"
 868         default n
 869         depends on !SMP
 870         help
 871           If enabled, the IP Checksum function is linked
 872           into L1 instruction memory. (less latency)
 873
 874 config CACHELINE_ALIGNED_L1
 875         bool "Locate cacheline_aligned data to L1 Data Memory"
 876         default y if !BF54x
 877         default n if BF54x
 878         depends on !SMP && !BF531 && !CRC32
 879         help
 880           If enabled, cacheline_aligned data is linked
 881           into L1 data memory. (less latency)
 882
 883 config SYSCALL_TAB_L1
 884         bool "Locate Syscall Table L1 Data Memory"
 885         default n
 886         depends on !SMP && !BF531
 887         help
 888           If enabled, the Syscall LUT is linked
 889           into L1 data memory. (less latency)
 890
 891 config CPLB_SWITCH_TAB_L1
 892         bool "Locate CPLB Switch Tables L1 Data Memory"
 893         default n
 894         depends on !SMP && !BF531
 895         help
 896           If enabled, the CPLB Switch Tables are linked
 897           into L1 data memory. (less latency)
 898
 899 config ICACHE_FLUSH_L1
 900         bool "Locate icache flush funcs in L1 Inst Memory"
 901         default y
 902         help
 903           If enabled, the Blackfin icache flushing functions are linked
 904           into L1 instruction memory.
 905
 906           Note that this might be required to address anomalies, but
 907           these functions are pretty small, so it shouldn't be too bad.
 908           If you are using a processor affected by an anomaly, the build
 909           system will double check for you and prevent it.
 910
 911 config DCACHE_FLUSH_L1
 912         bool "Locate dcache flush funcs in L1 Inst Memory"
 913         default y
 914         depends on !SMP
 915         help
 916           If enabled, the Blackfin dcache flushing functions are linked
 917           into L1 instruction memory.
 918
 919 config APP_STACK_L1
 920         bool "Support locating application stack in L1 Scratch Memory"
 921         default y
 922         depends on !SMP
 923         help
 924           If enabled the application stack can be located in L1
 925           scratch memory (less latency).
 926
 927           Currently only works with FLAT binaries.
 928
 929 config EXCEPTION_L1_SCRATCH
 930         bool "Locate exception stack in L1 Scratch Memory"
 931         default n
 932         depends on !SMP && !APP_STACK_L1
 933         help
 934           Whenever an exception occurs, use the L1 Scratch memory for
 935           stack storage.  You cannot place the stacks of FLAT binaries
 936           in L1 when using this option.
 937
 938           If you don't use L1 Scratch, then you should say Y here.
 939
 940 comment "Speed Optimizations"
 941 config BFIN_INS_LOWOVERHEAD
 942         bool "ins[bwl] low overhead, higher interrupt latency"
 943         default y
 944         depends on !SMP
 945         help
 946           Reads on the Blackfin are speculative. In Blackfin terms, this means
 947           they can be interrupted at any time (even after they have been issued
 948           on to the external bus), and re-issued after the interrupt occurs.
 949           For memory - this is not a big deal, since memory does not change if
 950           it sees a read.
 951
 952           If a FIFO is sitting on the end of the read, it will see two reads,
 953           when the core only sees one since the FIFO receives both the read
 954           which is cancelled (and not delivered to the core) and the one which
 955           is re-issued (which is delivered to the core).
 956
 957           To solve this, interrupts are turned off before reads occur to
 958           I/O space. This option controls which the overhead/latency of
 959           controlling interrupts during this time
 960            "n" turns interrupts off every read
 961                 (higher overhead, but lower interrupt latency)
 962            "y" turns interrupts off every loop
 963                 (low overhead, but longer interrupt latency)
 964
 965           default behavior is to leave this set to on (type "Y"). If you are experiencing
 966           interrupt latency issues, it is safe and OK to turn this off.
 967
 968 endmenu
 969
 970 choice
 971         prompt "Kernel executes from"
 972         help
 973           Choose the memory type that the kernel will be running in.
 974
 975 config RAMKERNEL
 976         bool "RAM"
 977         help
 978           The kernel will be resident in RAM when running.
 979
 980 config ROMKERNEL
 981         bool "ROM"
 982         help
 983           The kernel will be resident in FLASH/ROM when running.
 984
 985 endchoice
 986
 987 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 988 config XIP_KERNEL
 989         bool
 990         default y
 991         depends on ROMKERNEL
 992
 993 source "mm/Kconfig"
 994
 995 config BFIN_GPTIMERS
 996         tristate "Enable Blackfin General Purpose Timers API"
 997         default n
 998         help
 999           Enable support for the General Purpose Timers API.  If you
1000           are unsure, say N.
1001
1002           To compile this driver as a module, choose M here: the module
1003           will be called gptimers.
1004
1005 choice
1006         prompt "Uncached DMA region"
1007         default DMA_UNCACHED_1M
1008 config DMA_UNCACHED_32M
1009         bool "Enable 32M DMA region"
1010 config DMA_UNCACHED_16M
1011         bool "Enable 16M DMA region"
1012 config DMA_UNCACHED_8M
1013         bool "Enable 8M DMA region"
1014 config DMA_UNCACHED_4M
1015         bool "Enable 4M DMA region"
1016 config DMA_UNCACHED_2M
1017         bool "Enable 2M DMA region"
1018 config DMA_UNCACHED_1M
1019         bool "Enable 1M DMA region"
1020 config DMA_UNCACHED_512K
1021         bool "Enable 512K DMA region"
1022 config DMA_UNCACHED_256K
1023         bool "Enable 256K DMA region"
1024 config DMA_UNCACHED_128K
1025         bool "Enable 128K DMA region"
1026 config DMA_UNCACHED_NONE
1027         bool "Disable DMA region"
1028 endchoice
1029
1030
1031 comment "Cache Support"
1032
1033 config BFIN_ICACHE
1034         bool "Enable ICACHE"
1035         default y
1036 config BFIN_EXTMEM_ICACHEABLE
1037         bool "Enable ICACHE for external memory"
1038         depends on BFIN_ICACHE
1039         default y
1040 config BFIN_L2_ICACHEABLE
1041         bool "Enable ICACHE for L2 SRAM"
1042         depends on BFIN_ICACHE
1043         depends on (BF54x || BF561 || BF60x) && !SMP
1044         default n
1045
1046 config BFIN_DCACHE
1047         bool "Enable DCACHE"
1048         default y
1049 config BFIN_DCACHE_BANKA
1050         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1051         depends on BFIN_DCACHE && !BF531
1052         default n
1053 config BFIN_EXTMEM_DCACHEABLE
1054         bool "Enable DCACHE for external memory"
1055         depends on BFIN_DCACHE
1056         default y
1057 choice
1058         prompt "External memory DCACHE policy"
1059         depends on BFIN_EXTMEM_DCACHEABLE
1060         default BFIN_EXTMEM_WRITEBACK if !SMP
1061         default BFIN_EXTMEM_WRITETHROUGH if SMP
1062 config BFIN_EXTMEM_WRITEBACK
1063         bool "Write back"
1064         depends on !SMP
1065         help
1066           Write Back Policy:
1067             Cached data will be written back to SDRAM only when needed.
1068             This can give a nice increase in performance, but beware of
1069             broken drivers that do not properly invalidate/flush their
1070             cache.
1071
1072           Write Through Policy:
1073             Cached data will always be written back to SDRAM when the
1074             cache is updated.  This is a completely safe setting, but
1075             performance is worse than Write Back.
1076
1077           If you are unsure of the options and you want to be safe,
1078           then go with Write Through.
1079
1080 config BFIN_EXTMEM_WRITETHROUGH
1081         bool "Write through"
1082         help
1083           Write Back Policy:
1084             Cached data will be written back to SDRAM only when needed.
1085             This can give a nice increase in performance, but beware of
1086             broken drivers that do not properly invalidate/flush their
1087             cache.
1088
1089           Write Through Policy:
1090             Cached data will always be written back to SDRAM when the
1091             cache is updated.  This is a completely safe setting, but
1092             performance is worse than Write Back.
1093
1094           If you are unsure of the options and you want to be safe,
1095           then go with Write Through.
1096
1097 endchoice
1098
1099 config BFIN_L2_DCACHEABLE
1100         bool "Enable DCACHE for L2 SRAM"
1101         depends on BFIN_DCACHE
1102         depends on (BF54x || BF561 || BF60x) && !SMP
1103         default n
1104 choice
1105         prompt "L2 SRAM DCACHE policy"
1106         depends on BFIN_L2_DCACHEABLE
1107         default BFIN_L2_WRITEBACK
1108 config BFIN_L2_WRITEBACK
1109         bool "Write back"
1110
1111 config BFIN_L2_WRITETHROUGH
1112         bool "Write through"
1113 endchoice
1114
1115
1116 comment "Memory Protection Unit"
1117 config MPU
1118         bool "Enable the memory protection unit"
1119         default n
1120         help
1121           Use the processor's MPU to protect applications from accessing
1122           memory they do not own.  This comes at a performance penalty
1123           and is recommended only for debugging.
1124
1125 comment "Asynchronous Memory Configuration"
1126
1127 menu "EBIU_AMGCTL Global Control"
1128         depends on !BF60x
1129 config C_AMCKEN
1130         bool "Enable CLKOUT"
1131         default y
1132
1133 config C_CDPRIO
1134         bool "DMA has priority over core for ext. accesses"
1135         default n
1136
1137 config C_B0PEN
1138         depends on BF561
1139         bool "Bank 0 16 bit packing enable"
1140         default y
1141
1142 config C_B1PEN
1143         depends on BF561
1144         bool "Bank 1 16 bit packing enable"
1145         default y
1146
1147 config C_B2PEN
1148         depends on BF561
1149         bool "Bank 2 16 bit packing enable"
1150         default y
1151
1152 config C_B3PEN
1153         depends on BF561
1154         bool "Bank 3 16 bit packing enable"
1155         default n
1156
1157 choice
1158         prompt "Enable Asynchronous Memory Banks"
1159         default C_AMBEN_ALL
1160
1161 config C_AMBEN
1162         bool "Disable All Banks"
1163
1164 config C_AMBEN_B0
1165         bool "Enable Bank 0"
1166
1167 config C_AMBEN_B0_B1
1168         bool "Enable Bank 0 & 1"
1169
1170 config C_AMBEN_B0_B1_B2
1171         bool "Enable Bank 0 & 1 & 2"
1172
1173 config C_AMBEN_ALL
1174         bool "Enable All Banks"
1175 endchoice
1176 endmenu
1177
1178 menu "EBIU_AMBCTL Control"
1179         depends on !BF60x
1180 config BANK_0
1181         hex "Bank 0 (AMBCTL0.L)"
1182         default 0x7BB0
1183         help
1184           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1185           used to control the Asynchronous Memory Bank 0 settings.
1186
1187 config BANK_1
1188         hex "Bank 1 (AMBCTL0.H)"
1189         default 0x7BB0
1190         default 0x5558 if BF54x
1191         help
1192           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1193           used to control the Asynchronous Memory Bank 1 settings.
1194
1195 config BANK_2
1196         hex "Bank 2 (AMBCTL1.L)"
1197         default 0x7BB0
1198         help
1199           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1200           used to control the Asynchronous Memory Bank 2 settings.
1201
1202 config BANK_3
1203         hex "Bank 3 (AMBCTL1.H)"
1204         default 0x99B3
1205         help
1206           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1207           used to control the Asynchronous Memory Bank 3 settings.
1208
1209 endmenu
1210
1211 config EBIU_MBSCTLVAL
1212         hex "EBIU Bank Select Control Register"
1213         depends on BF54x
1214         default 0
1215
1216 config EBIU_MODEVAL
1217         hex "Flash Memory Mode Control Register"
1218         depends on BF54x
1219         default 1
1220
1221 config EBIU_FCTLVAL
1222         hex "Flash Memory Bank Control Register"
1223         depends on BF54x
1224         default 6
1225 endmenu
1226
1227 #############################################################################
1228 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1229
1230 config PCI
1231         bool "PCI support"
1232         depends on BROKEN
1233         help
1234           Support for PCI bus.
1235
1236 source "drivers/pci/Kconfig"
1237
1238 source "drivers/pcmcia/Kconfig"
1239
1240 source "drivers/pci/hotplug/Kconfig"
1241
1242 endmenu
1243
1244 menu "Executable file formats"
1245
1246 source "fs/Kconfig.binfmt"
1247
1248 endmenu
1249
1250 menu "Power management options"
1251
1252 source "kernel/power/Kconfig"
1253
1254 config ARCH_SUSPEND_POSSIBLE
1255         def_bool y
1256
1257 choice
1258         prompt "Standby Power Saving Mode"
1259         depends on PM && !BF60x
1260         default PM_BFIN_SLEEP_DEEPER
1261 config  PM_BFIN_SLEEP_DEEPER
1262         bool "Sleep Deeper"
1263         help
1264           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1265           power dissipation by disabling the clock to the processor core (CCLK).
1266           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1267           to 0.85 V to provide the greatest power savings, while preserving the
1268           processor state.
1269           The PLL and system clock (SCLK) continue to operate at a very low
1270           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1271           the SDRAM is put into Self Refresh Mode. Typically an external event
1272           such as GPIO interrupt or RTC activity wakes up the processor.
1273           Various Peripherals such as UART, SPORT, PPI may not function as
1274           normal during Sleep Deeper, due to the reduced SCLK frequency.
1275           When in the sleep mode, system DMA access to L1 memory is not supported.
1276
1277           If unsure, select "Sleep Deeper".
1278
1279 config  PM_BFIN_SLEEP
1280         bool "Sleep"
1281         help
1282           Sleep Mode (High Power Savings) - The sleep mode reduces power
1283           dissipation by disabling the clock to the processor core (CCLK).
1284           The PLL and system clock (SCLK), however, continue to operate in
1285           this mode. Typically an external event or RTC activity will wake
1286           up the processor. When in the sleep mode, system DMA access to L1
1287           memory is not supported.
1288
1289           If unsure, select "Sleep Deeper".
1290 endchoice
1291
1292 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1293         depends on PM
1294
1295 config PM_BFIN_WAKE_PH6
1296         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1297         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1298         default n
1299         help
1300           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1301
1302 config PM_BFIN_WAKE_GP
1303         bool "Allow Wake-Up from GPIOs"
1304         depends on PM && BF54x
1305         default n
1306         help
1307           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1308           (all processors, except ADSP-BF549). This option sets
1309           the general-purpose wake-up enable (GPWE) control bit to enable
1310           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1311           On ADSP-BF549 this option enables the same functionality on the
1312           /MRXON pin also PH7.
1313
1314 config PM_BFIN_WAKE_PA15
1315         bool "Allow Wake-Up from PA15"
1316         depends on PM && BF60x
1317         default n
1318         help
1319           Enable PA15 Wake-Up
1320
1321 config PM_BFIN_WAKE_PA15_POL
1322         int "Wake-up priority"
1323         depends on PM_BFIN_WAKE_PA15
1324         default 0
1325         help
1326           Wake-Up priority 0(low) 1(high)
1327
1328 config PM_BFIN_WAKE_PB15
1329         bool "Allow Wake-Up from PB15"
1330         depends on PM && BF60x
1331         default n
1332         help
1333           Enable PB15 Wake-Up
1334
1335 config PM_BFIN_WAKE_PB15_POL
1336         int "Wake-up priority"
1337         depends on PM_BFIN_WAKE_PB15
1338         default 0
1339         help
1340           Wake-Up priority 0(low) 1(high)
1341
1342 config PM_BFIN_WAKE_PC15
1343         bool "Allow Wake-Up from PC15"
1344         depends on PM && BF60x
1345         default n
1346         help
1347           Enable PC15 Wake-Up
1348
1349 config PM_BFIN_WAKE_PC15_POL
1350         int "Wake-up priority"
1351         depends on PM_BFIN_WAKE_PC15
1352         default 0
1353         help
1354           Wake-Up priority 0(low) 1(high)
1355
1356 config PM_BFIN_WAKE_PD06
1357         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1358         depends on PM && BF60x
1359         default n
1360         help
1361           Enable PD06(ETH0_PHYINT) Wake-up
1362
1363 config PM_BFIN_WAKE_PD06_POL
1364         int "Wake-up priority"
1365         depends on PM_BFIN_WAKE_PD06
1366         default 0
1367         help
1368           Wake-Up priority 0(low) 1(high)
1369
1370 config PM_BFIN_WAKE_PE12
1371         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1372         depends on PM && BF60x
1373         default n
1374         help
1375           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1376
1377 config PM_BFIN_WAKE_PE12_POL
1378         int "Wake-up priority"
1379         depends on PM_BFIN_WAKE_PE12
1380         default 0
1381         help
1382           Wake-Up priority 0(low) 1(high)
1383
1384 config PM_BFIN_WAKE_PG04
1385         bool "Allow Wake-Up from PG04(CAN0_RX)"
1386         depends on PM && BF60x
1387         default n
1388         help
1389           Enable PG04(CAN0_RX) Wake-up
1390
1391 config PM_BFIN_WAKE_PG04_POL
1392         int "Wake-up priority"
1393         depends on PM_BFIN_WAKE_PG04
1394         default 0
1395         help
1396           Wake-Up priority 0(low) 1(high)
1397
1398 config PM_BFIN_WAKE_PG13
1399         bool "Allow Wake-Up from PG13"
1400         depends on PM && BF60x
1401         default n
1402         help
1403           Enable PG13 Wake-Up
1404
1405 config PM_BFIN_WAKE_PG13_POL
1406         int "Wake-up priority"
1407         depends on PM_BFIN_WAKE_PG13
1408         default 0
1409         help
1410           Wake-Up priority 0(low) 1(high)
1411
1412 config PM_BFIN_WAKE_USB
1413         bool "Allow Wake-Up from (USB)"
1414         depends on PM && BF60x
1415         default n
1416         help
1417           Enable (USB) Wake-up
1418
1419 config PM_BFIN_WAKE_USB_POL
1420         int "Wake-up priority"
1421         depends on PM_BFIN_WAKE_USB
1422         default 0
1423         help
1424           Wake-Up priority 0(low) 1(high)
1425
1426 endmenu
1427
1428 menu "CPU Frequency scaling"
1429
1430 source "drivers/cpufreq/Kconfig"
1431
1432 config BFIN_CPU_FREQ
1433         bool
1434         depends on CPU_FREQ
1435         select CPU_FREQ_TABLE
1436         default y
1437
1438 config CPU_VOLTAGE
1439         bool "CPU Voltage scaling"
1440         depends on CPU_FREQ
1441         default n
1442         help
1443           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1444           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1445           manuals. There is a theoretical risk that during VDDINT transitions
1446           the PLL may unlock.
1447
1448 endmenu
1449
1450 source "net/Kconfig"
1451
1452 source "drivers/Kconfig"
1453
1454 source "drivers/firmware/Kconfig"
1455
1456 source "fs/Kconfig"
1457
1458 source "arch/blackfin/Kconfig.debug"
1459
1460 source "security/Kconfig"
1461
1462 source "crypto/Kconfig"
1463
1464 source "lib/Kconfig"