arch/blackfin/Kconfig

   1 config MMU
   2         def_bool n
   3
   4 config FPU
   5         def_bool n
   6
   7 config RWSEM_GENERIC_SPINLOCK
   8         def_bool y
   9
  10 config RWSEM_XCHGADD_ALGORITHM
  11         def_bool n
  12
  13 config BLACKFIN
  14         def_bool y
  15         select HAVE_ARCH_KGDB
  16         select HAVE_ARCH_TRACEHOOK
  17         select HAVE_DYNAMIC_FTRACE
  18         select HAVE_FTRACE_MCOUNT_RECORD
  19         select HAVE_FUNCTION_GRAPH_TRACER
  20         select HAVE_FUNCTION_TRACER
  21         select HAVE_IDE
  22         select HAVE_KERNEL_GZIP if RAMKERNEL
  23         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  24         select HAVE_KERNEL_LZMA if RAMKERNEL
  25         select HAVE_KERNEL_LZO if RAMKERNEL
  26         select HAVE_OPROFILE
  27         select HAVE_PERF_EVENTS
  28         select ARCH_HAVE_CUSTOM_GPIO_H
  29         select GPIOLIB
  30         select HAVE_UID16
  31         select HAVE_UNDERSCORE_SYMBOL_PREFIX
  32         select VIRT_TO_BUS
  33         select ARCH_WANT_IPC_PARSE_VERSION
  34         select GENERIC_ATOMIC64
  35         select GENERIC_IRQ_PROBE
  36         select GENERIC_IRQ_SHOW
  37         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
  38         select GENERIC_SMP_IDLE_THREAD
  39         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
  40         select HAVE_MOD_ARCH_SPECIFIC
  41         select MODULES_USE_ELF_RELA
  42         select HAVE_DEBUG_STACKOVERFLOW
  43         select HAVE_NMI
  44         select ARCH_NO_COHERENT_DMA_MMAP
  45
  46 config GENERIC_CSUM
  47         def_bool y
  48
  49 config GENERIC_BUG
  50         def_bool y
  51         depends on BUG
  52
  53 config ZONE_DMA
  54         def_bool y
  55
  56 config FORCE_MAX_ZONEORDER
  57         int
  58         default "14"
  59
  60 config GENERIC_CALIBRATE_DELAY
  61         def_bool y
  62
  63 config LOCKDEP_SUPPORT
  64         def_bool y
  65
  66 config STACKTRACE_SUPPORT
  67         def_bool y
  68
  69 config TRACE_IRQFLAGS_SUPPORT
  70         def_bool y
  71
  72 source "init/Kconfig"
  73
  74 source "kernel/Kconfig.preempt"
  75
  76 source "kernel/Kconfig.freezer"
  77
  78 menu "Blackfin Processor Options"
  79
  80 comment "Processor and Board Settings"
  81
  82 choice
  83         prompt "CPU"
  84         default BF533
  85
  86 config BF512
  87         bool "BF512"
  88         help
  89           BF512 Processor Support.
  90
  91 config BF514
  92         bool "BF514"
  93         help
  94           BF514 Processor Support.
  95
  96 config BF516
  97         bool "BF516"
  98         help
  99           BF516 Processor Support.
 100
 101 config BF518
 102         bool "BF518"
 103         help
 104           BF518 Processor Support.
 105
 106 config BF522
 107         bool "BF522"
 108         help
 109           BF522 Processor Support.
 110
 111 config BF523
 112         bool "BF523"
 113         help
 114           BF523 Processor Support.
 115
 116 config BF524
 117         bool "BF524"
 118         help
 119           BF524 Processor Support.
 120
 121 config BF525
 122         bool "BF525"
 123         help
 124           BF525 Processor Support.
 125
 126 config BF526
 127         bool "BF526"
 128         help
 129           BF526 Processor Support.
 130
 131 config BF527
 132         bool "BF527"
 133         help
 134           BF527 Processor Support.
 135
 136 config BF531
 137         bool "BF531"
 138         help
 139           BF531 Processor Support.
 140
 141 config BF532
 142         bool "BF532"
 143         help
 144           BF532 Processor Support.
 145
 146 config BF533
 147         bool "BF533"
 148         help
 149           BF533 Processor Support.
 150
 151 config BF534
 152         bool "BF534"
 153         help
 154           BF534 Processor Support.
 155
 156 config BF536
 157         bool "BF536"
 158         help
 159           BF536 Processor Support.
 160
 161 config BF537
 162         bool "BF537"
 163         help
 164           BF537 Processor Support.
 165
 166 config BF538
 167         bool "BF538"
 168         help
 169           BF538 Processor Support.
 170
 171 config BF539
 172         bool "BF539"
 173         help
 174           BF539 Processor Support.
 175
 176 config BF542_std
 177         bool "BF542"
 178         help
 179           BF542 Processor Support.
 180
 181 config BF542M
 182         bool "BF542m"
 183         help
 184           BF542 Processor Support.
 185
 186 config BF544_std
 187         bool "BF544"
 188         help
 189           BF544 Processor Support.
 190
 191 config BF544M
 192         bool "BF544m"
 193         help
 194           BF544 Processor Support.
 195
 196 config BF547_std
 197         bool "BF547"
 198         help
 199           BF547 Processor Support.
 200
 201 config BF547M
 202         bool "BF547m"
 203         help
 204           BF547 Processor Support.
 205
 206 config BF548_std
 207         bool "BF548"
 208         help
 209           BF548 Processor Support.
 210
 211 config BF548M
 212         bool "BF548m"
 213         help
 214           BF548 Processor Support.
 215
 216 config BF549_std
 217         bool "BF549"
 218         help
 219           BF549 Processor Support.
 220
 221 config BF549M
 222         bool "BF549m"
 223         help
 224           BF549 Processor Support.
 225
 226 config BF561
 227         bool "BF561"
 228         help
 229           BF561 Processor Support.
 230
 231 config BF609
 232         bool "BF609"
 233         select CLKDEV_LOOKUP
 234         help
 235           BF609 Processor Support.
 236
 237 endchoice
 238
 239 config SMP
 240         depends on BF561
 241         select TICKSOURCE_CORETMR
 242         bool "Symmetric multi-processing support"
 243         ---help---
 244           This enables support for systems with more than one CPU,
 245           like the dual core BF561. If you have a system with only one
 246           CPU, say N. If you have a system with more than one CPU, say Y.
 247
 248           If you don't know what to do here, say N.
 249
 250 config NR_CPUS
 251         int
 252         depends on SMP
 253         default 2 if BF561
 254
 255 config HOTPLUG_CPU
 256         bool "Support for hot-pluggable CPUs"
 257         depends on SMP
 258         default y
 259
 260 config BF_REV_MIN
 261         int
 262         default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 263         default 2 if (BF537 || BF536 || BF534)
 264         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 265         default 4 if (BF538 || BF539)
 266
 267 config BF_REV_MAX
 268         int
 269         default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
 270         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 271         default 5 if (BF561 || BF538 || BF539)
 272         default 6 if (BF533 || BF532 || BF531)
 273
 274 choice
 275         prompt "Silicon Rev"
 276         default BF_REV_0_0 if (BF51x || BF52x || BF60x)
 277         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 278         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 279
 280 config BF_REV_0_0
 281         bool "0.0"
 282         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 283
 284 config BF_REV_0_1
 285         bool "0.1"
 286         depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 287
 288 config BF_REV_0_2
 289         bool "0.2"
 290         depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 291
 292 config BF_REV_0_3
 293         bool "0.3"
 294         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 295
 296 config BF_REV_0_4
 297         bool "0.4"
 298         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
 299
 300 config BF_REV_0_5
 301         bool "0.5"
 302         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 303
 304 config BF_REV_0_6
 305         bool "0.6"
 306         depends on (BF533 || BF532 || BF531)
 307
 308 config BF_REV_ANY
 309         bool "any"
 310
 311 config BF_REV_NONE
 312         bool "none"
 313
 314 endchoice
 315
 316 config BF53x
 317         bool
 318         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 319         default y
 320
 321 config GPIO_ADI
 322         def_bool y
 323         depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
 324
 325 config PINCTRL
 326         def_bool y
 327         depends on BF54x || BF60x
 328
 329 config MEM_MT48LC64M4A2FB_7E
 330         bool
 331         depends on (BFIN533_STAMP)
 332         default y
 333
 334 config MEM_MT48LC16M16A2TG_75
 335         bool
 336         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 337                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 338                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 339                 || BFIN527_BLUETECHNIX_CM)
 340         default y
 341
 342 config MEM_MT48LC32M8A2_75
 343         bool
 344         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 345         default y
 346
 347 config MEM_MT48LC8M32B2B5_7
 348         bool
 349         depends on (BFIN561_BLUETECHNIX_CM)
 350         default y
 351
 352 config MEM_MT48LC32M16A2TG_75
 353         bool
 354         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
 355         default y
 356
 357 config MEM_MT48H32M16LFCJ_75
 358         bool
 359         depends on (BFIN526_EZBRD)
 360         default y
 361
 362 config MEM_MT47H64M16
 363         bool
 364         depends on (BFIN609_EZKIT)
 365         default y
 366
 367 source "arch/blackfin/mach-bf518/Kconfig"
 368 source "arch/blackfin/mach-bf527/Kconfig"
 369 source "arch/blackfin/mach-bf533/Kconfig"
 370 source "arch/blackfin/mach-bf561/Kconfig"
 371 source "arch/blackfin/mach-bf537/Kconfig"
 372 source "arch/blackfin/mach-bf538/Kconfig"
 373 source "arch/blackfin/mach-bf548/Kconfig"
 374 source "arch/blackfin/mach-bf609/Kconfig"
 375
 376 menu "Board customizations"
 377
 378 config CMDLINE_BOOL
 379         bool "Default bootloader kernel arguments"
 380
 381 config CMDLINE
 382         string "Initial kernel command string"
 383         depends on CMDLINE_BOOL
 384         default "console=ttyBF0,57600"
 385         help
 386           If you don't have a boot loader capable of passing a command line string
 387           to the kernel, you may specify one here. As a minimum, you should specify
 388           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 389
 390 config BOOT_LOAD
 391         hex "Kernel load address for booting"
 392         default "0x1000"
 393         range 0x1000 0x20000000
 394         help
 395           This option allows you to set the load address of the kernel.
 396           This can be useful if you are on a board which has a small amount
 397           of memory or you wish to reserve some memory at the beginning of
 398           the address space.
 399
 400           Note that you need to keep this value above 4k (0x1000) as this
 401           memory region is used to capture NULL pointer references as well
 402           as some core kernel functions.
 403
 404 config PHY_RAM_BASE_ADDRESS
 405         hex "Physical RAM Base"
 406         default 0x0
 407         help
 408           set BF609 FPGA physical SRAM base address
 409
 410 config ROM_BASE
 411         hex "Kernel ROM Base"
 412         depends on ROMKERNEL
 413         default "0x20040040"
 414         range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
 415         range 0x20000000 0x30000000 if (BF54x || BF561)
 416         range 0xB0000000 0xC0000000 if (BF60x)
 417         help
 418           Make sure your ROM base does not include any file-header
 419           information that is prepended to the kernel.
 420
 421           For example, the bootable U-Boot format (created with
 422           mkimage) has a 64 byte header (0x40).  So while the image
 423           you write to flash might start at say 0x20080000, you have
 424           to add 0x40 to get the kernel's ROM base as it will come
 425           after the header.
 426
 427 comment "Clock/PLL Setup"
 428
 429 config CLKIN_HZ
 430         int "Frequency of the crystal on the board in Hz"
 431         default "10000000" if BFIN532_IP0X
 432         default "11059200" if BFIN533_STAMP
 433         default "24576000" if PNAV10
 434         default "25000000" # most people use this
 435         default "27000000" if BFIN533_EZKIT
 436         default "30000000" if BFIN561_EZKIT
 437         default "24000000" if BFIN527_AD7160EVAL
 438         help
 439           The frequency of CLKIN crystal oscillator on the board in Hz.
 440           Warning: This value should match the crystal on the board. Otherwise,
 441           peripherals won't work properly.
 442
 443 config BFIN_KERNEL_CLOCK
 444         bool "Re-program Clocks while Kernel boots?"
 445         default n
 446         help
 447           This option decides if kernel clocks are re-programed from the
 448           bootloader settings. If the clocks are not set, the SDRAM settings
 449           are also not changed, and the Bootloader does 100% of the hardware
 450           configuration.
 451
 452 config PLL_BYPASS
 453         bool "Bypass PLL"
 454         depends on BFIN_KERNEL_CLOCK && (!BF60x)
 455         default n
 456
 457 config CLKIN_HALF
 458         bool "Half Clock In"
 459         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 460         default n
 461         help
 462           If this is set the clock will be divided by 2, before it goes to the PLL.
 463
 464 config VCO_MULT
 465         int "VCO Multiplier"
 466         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 467         range 1 64
 468         default "22" if BFIN533_EZKIT
 469         default "45" if BFIN533_STAMP
 470         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 471         default "22" if BFIN533_BLUETECHNIX_CM
 472         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 473         default "20" if (BFIN561_EZKIT || BF609)
 474         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 475         default "25" if BFIN527_AD7160EVAL
 476         help
 477           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 478           PLL Frequency = (Crystal Frequency) * (this setting)
 479
 480 choice
 481         prompt "Core Clock Divider"
 482         depends on BFIN_KERNEL_CLOCK
 483         default CCLK_DIV_1
 484         help
 485           This sets the frequency of the core. It can be 1, 2, 4 or 8
 486           Core Frequency = (PLL frequency) / (this setting)
 487
 488 config CCLK_DIV_1
 489         bool "1"
 490
 491 config CCLK_DIV_2
 492         bool "2"
 493
 494 config CCLK_DIV_4
 495         bool "4"
 496
 497 config CCLK_DIV_8
 498         bool "8"
 499 endchoice
 500
 501 config SCLK_DIV
 502         int "System Clock Divider"
 503         depends on BFIN_KERNEL_CLOCK
 504         range 1 15
 505         default 4
 506         help
 507           This sets the frequency of the system clock (including SDRAM or DDR) on
 508           !BF60x else it set the clock for system buses and provides the
 509           source from which SCLK0 and SCLK1 are derived.
 510           This can be between 1 and 15
 511           System Clock = (PLL frequency) / (this setting)
 512
 513 config SCLK0_DIV
 514         int "System Clock0 Divider"
 515         depends on BFIN_KERNEL_CLOCK && BF60x
 516         range 1 15
 517         default 1
 518         help
 519           This sets the frequency of the system clock0 for PVP and all other
 520           peripherals not clocked by SCLK1.
 521           This can be between 1 and 15
 522           System Clock0 = (System Clock) / (this setting)
 523
 524 config SCLK1_DIV
 525         int "System Clock1 Divider"
 526         depends on BFIN_KERNEL_CLOCK && BF60x
 527         range 1 15
 528         default 1
 529         help
 530           This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
 531           This can be between 1 and 15
 532           System Clock1 = (System Clock) / (this setting)
 533
 534 config DCLK_DIV
 535         int "DDR Clock Divider"
 536         depends on BFIN_KERNEL_CLOCK && BF60x
 537         range 1 15
 538         default 2
 539         help
 540           This sets the frequency of the DDR memory.
 541           This can be between 1 and 15
 542           DDR Clock = (PLL frequency) / (this setting)
 543
 544 choice
 545         prompt "DDR SDRAM Chip Type"
 546         depends on BFIN_KERNEL_CLOCK
 547         depends on BF54x
 548         default MEM_MT46V32M16_5B
 549
 550 config MEM_MT46V32M16_6T
 551         bool "MT46V32M16_6T"
 552
 553 config MEM_MT46V32M16_5B
 554         bool "MT46V32M16_5B"
 555 endchoice
 556
 557 choice
 558         prompt "DDR/SDRAM Timing"
 559         depends on BFIN_KERNEL_CLOCK && !BF60x
 560         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 561         help
 562           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 563           The calculated SDRAM timing parameters may not be 100%
 564           accurate - This option is therefore marked experimental.
 565
 566 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 567         bool "Calculate Timings"
 568
 569 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 570         bool "Provide accurate Timings based on target SCLK"
 571         help
 572           Please consult the Blackfin Hardware Reference Manuals as well
 573           as the memory device datasheet.
 574           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 575 endchoice
 576
 577 menu "Memory Init Control"
 578         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 579
 580 config MEM_DDRCTL0
 581         depends on BF54x
 582         hex "DDRCTL0"
 583         default 0x0
 584
 585 config MEM_DDRCTL1
 586         depends on BF54x
 587         hex "DDRCTL1"
 588         default 0x0
 589
 590 config MEM_DDRCTL2
 591         depends on BF54x
 592         hex "DDRCTL2"
 593         default 0x0
 594
 595 config MEM_EBIU_DDRQUE
 596         depends on BF54x
 597         hex "DDRQUE"
 598         default 0x0
 599
 600 config MEM_SDRRC
 601         depends on !BF54x
 602         hex "SDRRC"
 603         default 0x0
 604
 605 config MEM_SDGCTL
 606         depends on !BF54x
 607         hex "SDGCTL"
 608         default 0x0
 609 endmenu
 610
 611 #
 612 # Max & Min Speeds for various Chips
 613 #
 614 config MAX_VCO_HZ
 615         int
 616         default 400000000 if BF512
 617         default 400000000 if BF514
 618         default 400000000 if BF516
 619         default 400000000 if BF518
 620         default 400000000 if BF522
 621         default 600000000 if BF523
 622         default 400000000 if BF524
 623         default 600000000 if BF525
 624         default 400000000 if BF526
 625         default 600000000 if BF527
 626         default 400000000 if BF531
 627         default 400000000 if BF532
 628         default 750000000 if BF533
 629         default 500000000 if BF534
 630         default 400000000 if BF536
 631         default 600000000 if BF537
 632         default 533333333 if BF538
 633         default 533333333 if BF539
 634         default 600000000 if BF542
 635         default 533333333 if BF544
 636         default 600000000 if BF547
 637         default 600000000 if BF548
 638         default 533333333 if BF549
 639         default 600000000 if BF561
 640         default 800000000 if BF609
 641
 642 config MIN_VCO_HZ
 643         int
 644         default 50000000
 645
 646 config MAX_SCLK_HZ
 647         int
 648         default 200000000 if BF609
 649         default 133333333
 650
 651 config MIN_SCLK_HZ
 652         int
 653         default 27000000
 654
 655 comment "Kernel Timer/Scheduler"
 656
 657 source kernel/Kconfig.hz
 658
 659 config SET_GENERIC_CLOCKEVENTS
 660         bool "Generic clock events"
 661         default y
 662         select GENERIC_CLOCKEVENTS
 663
 664 menu "Clock event device"
 665         depends on GENERIC_CLOCKEVENTS
 666 config TICKSOURCE_GPTMR0
 667         bool "GPTimer0"
 668         depends on !SMP
 669         select BFIN_GPTIMERS
 670
 671 config TICKSOURCE_CORETMR
 672         bool "Core timer"
 673         default y
 674 endmenu
 675
 676 menu "Clock source"
 677         depends on GENERIC_CLOCKEVENTS
 678 config CYCLES_CLOCKSOURCE
 679         bool "CYCLES"
 680         default y
 681         depends on !BFIN_SCRATCH_REG_CYCLES
 682         depends on !SMP
 683         help
 684           If you say Y here, you will enable support for using the 'cycles'
 685           registers as a clock source.  Doing so means you will be unable to
 686           safely write to the 'cycles' register during runtime.  You will
 687           still be able to read it (such as for performance monitoring), but
 688           writing the registers will most likely crash the kernel.
 689
 690 config GPTMR0_CLOCKSOURCE
 691         bool "GPTimer0"
 692         select BFIN_GPTIMERS
 693         depends on !TICKSOURCE_GPTMR0
 694 endmenu
 695
 696 comment "Misc"
 697
 698 choice
 699         prompt "Blackfin Exception Scratch Register"
 700         default BFIN_SCRATCH_REG_RETN
 701         help
 702           Select the resource to reserve for the Exception handler:
 703             - RETN: Non-Maskable Interrupt (NMI)
 704             - RETE: Exception Return (JTAG/ICE)
 705             - CYCLES: Performance counter
 706
 707           If you are unsure, please select "RETN".
 708
 709 config BFIN_SCRATCH_REG_RETN
 710         bool "RETN"
 711         help
 712           Use the RETN register in the Blackfin exception handler
 713           as a stack scratch register.  This means you cannot
 714           safely use NMI on the Blackfin while running Linux, but
 715           you can debug the system with a JTAG ICE and use the
 716           CYCLES performance registers.
 717
 718           If you are unsure, please select "RETN".
 719
 720 config BFIN_SCRATCH_REG_RETE
 721         bool "RETE"
 722         help
 723           Use the RETE register in the Blackfin exception handler
 724           as a stack scratch register.  This means you cannot
 725           safely use a JTAG ICE while debugging a Blackfin board,
 726           but you can safely use the CYCLES performance registers
 727           and the NMI.
 728
 729           If you are unsure, please select "RETN".
 730
 731 config BFIN_SCRATCH_REG_CYCLES
 732         bool "CYCLES"
 733         help
 734           Use the CYCLES register in the Blackfin exception handler
 735           as a stack scratch register.  This means you cannot
 736           safely use the CYCLES performance registers on a Blackfin
 737           board at anytime, but you can debug the system with a JTAG
 738           ICE and use the NMI.
 739
 740           If you are unsure, please select "RETN".
 741
 742 endchoice
 743
 744 endmenu
 745
 746
 747 menu "Blackfin Kernel Optimizations"
 748
 749 comment "Memory Optimizations"
 750
 751 config I_ENTRY_L1
 752         bool "Locate interrupt entry code in L1 Memory"
 753         default y
 754         depends on !SMP
 755         help
 756           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 757           into L1 instruction memory. (less latency)
 758
 759 config EXCPT_IRQ_SYSC_L1
 760         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 761         default y
 762         depends on !SMP
 763         help
 764           If enabled, the entire ASM lowlevel exception and interrupt entry code
 765           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 766           (less latency)
 767
 768 config DO_IRQ_L1
 769         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 770         default y
 771         depends on !SMP
 772         help
 773           If enabled, the frequently called do_irq dispatcher function is linked
 774           into L1 instruction memory. (less latency)
 775
 776 config CORE_TIMER_IRQ_L1
 777         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 778         default y
 779         depends on !SMP
 780         help
 781           If enabled, the frequently called timer_interrupt() function is linked
 782           into L1 instruction memory. (less latency)
 783
 784 config IDLE_L1
 785         bool "Locate frequently idle function in L1 Memory"
 786         default y
 787         depends on !SMP
 788         help
 789           If enabled, the frequently called idle function is linked
 790           into L1 instruction memory. (less latency)
 791
 792 config SCHEDULE_L1
 793         bool "Locate kernel schedule function in L1 Memory"
 794         default y
 795         depends on !SMP
 796         help
 797           If enabled, the frequently called kernel schedule is linked
 798           into L1 instruction memory. (less latency)
 799
 800 config ARITHMETIC_OPS_L1
 801         bool "Locate kernel owned arithmetic functions in L1 Memory"
 802         default y
 803         depends on !SMP
 804         help
 805           If enabled, arithmetic functions are linked
 806           into L1 instruction memory. (less latency)
 807
 808 config ACCESS_OK_L1
 809         bool "Locate access_ok function in L1 Memory"
 810         default y
 811         depends on !SMP
 812         help
 813           If enabled, the access_ok function is linked
 814           into L1 instruction memory. (less latency)
 815
 816 config MEMSET_L1
 817         bool "Locate memset function in L1 Memory"
 818         default y
 819         depends on !SMP
 820         help
 821           If enabled, the memset function is linked
 822           into L1 instruction memory. (less latency)
 823
 824 config MEMCPY_L1
 825         bool "Locate memcpy function in L1 Memory"
 826         default y
 827         depends on !SMP
 828         help
 829           If enabled, the memcpy function is linked
 830           into L1 instruction memory. (less latency)
 831
 832 config STRCMP_L1
 833         bool "locate strcmp function in L1 Memory"
 834         default y
 835         depends on !SMP
 836         help
 837           If enabled, the strcmp function is linked
 838           into L1 instruction memory (less latency).
 839
 840 config STRNCMP_L1
 841         bool "locate strncmp function in L1 Memory"
 842         default y
 843         depends on !SMP
 844         help
 845           If enabled, the strncmp function is linked
 846           into L1 instruction memory (less latency).
 847
 848 config STRCPY_L1
 849         bool "locate strcpy function in L1 Memory"
 850         default y
 851         depends on !SMP
 852         help
 853           If enabled, the strcpy function is linked
 854           into L1 instruction memory (less latency).
 855
 856 config STRNCPY_L1
 857         bool "locate strncpy function in L1 Memory"
 858         default y
 859         depends on !SMP
 860         help
 861           If enabled, the strncpy function is linked
 862           into L1 instruction memory (less latency).
 863
 864 config SYS_BFIN_SPINLOCK_L1
 865         bool "Locate sys_bfin_spinlock function in L1 Memory"
 866         default y
 867         depends on !SMP
 868         help
 869           If enabled, sys_bfin_spinlock function is linked
 870           into L1 instruction memory. (less latency)
 871
 872 config CACHELINE_ALIGNED_L1
 873         bool "Locate cacheline_aligned data to L1 Data Memory"
 874         default y if !BF54x
 875         default n if BF54x
 876         depends on !SMP && !BF531 && !CRC32
 877         help
 878           If enabled, cacheline_aligned data is linked
 879           into L1 data memory. (less latency)
 880
 881 config SYSCALL_TAB_L1
 882         bool "Locate Syscall Table L1 Data Memory"
 883         default n
 884         depends on !SMP && !BF531
 885         help
 886           If enabled, the Syscall LUT is linked
 887           into L1 data memory. (less latency)
 888
 889 config CPLB_SWITCH_TAB_L1
 890         bool "Locate CPLB Switch Tables L1 Data Memory"
 891         default n
 892         depends on !SMP && !BF531
 893         help
 894           If enabled, the CPLB Switch Tables are linked
 895           into L1 data memory. (less latency)
 896
 897 config ICACHE_FLUSH_L1
 898         bool "Locate icache flush funcs in L1 Inst Memory"
 899         default y
 900         help
 901           If enabled, the Blackfin icache flushing functions are linked
 902           into L1 instruction memory.
 903
 904           Note that this might be required to address anomalies, but
 905           these functions are pretty small, so it shouldn't be too bad.
 906           If you are using a processor affected by an anomaly, the build
 907           system will double check for you and prevent it.
 908
 909 config DCACHE_FLUSH_L1
 910         bool "Locate dcache flush funcs in L1 Inst Memory"
 911         default y
 912         depends on !SMP
 913         help
 914           If enabled, the Blackfin dcache flushing functions are linked
 915           into L1 instruction memory.
 916
 917 config APP_STACK_L1
 918         bool "Support locating application stack in L1 Scratch Memory"
 919         default y
 920         depends on !SMP
 921         help
 922           If enabled the application stack can be located in L1
 923           scratch memory (less latency).
 924
 925           Currently only works with FLAT binaries.
 926
 927 config EXCEPTION_L1_SCRATCH
 928         bool "Locate exception stack in L1 Scratch Memory"
 929         default n
 930         depends on !SMP && !APP_STACK_L1
 931         help
 932           Whenever an exception occurs, use the L1 Scratch memory for
 933           stack storage.  You cannot place the stacks of FLAT binaries
 934           in L1 when using this option.
 935
 936           If you don't use L1 Scratch, then you should say Y here.
 937
 938 comment "Speed Optimizations"
 939 config BFIN_INS_LOWOVERHEAD
 940         bool "ins[bwl] low overhead, higher interrupt latency"
 941         default y
 942         depends on !SMP
 943         help
 944           Reads on the Blackfin are speculative. In Blackfin terms, this means
 945           they can be interrupted at any time (even after they have been issued
 946           on to the external bus), and re-issued after the interrupt occurs.
 947           For memory - this is not a big deal, since memory does not change if
 948           it sees a read.
 949
 950           If a FIFO is sitting on the end of the read, it will see two reads,
 951           when the core only sees one since the FIFO receives both the read
 952           which is cancelled (and not delivered to the core) and the one which
 953           is re-issued (which is delivered to the core).
 954
 955           To solve this, interrupts are turned off before reads occur to
 956           I/O space. This option controls which the overhead/latency of
 957           controlling interrupts during this time
 958            "n" turns interrupts off every read
 959                 (higher overhead, but lower interrupt latency)
 960            "y" turns interrupts off every loop
 961                 (low overhead, but longer interrupt latency)
 962
 963           default behavior is to leave this set to on (type "Y"). If you are experiencing
 964           interrupt latency issues, it is safe and OK to turn this off.
 965
 966 endmenu
 967
 968 choice
 969         prompt "Kernel executes from"
 970         help
 971           Choose the memory type that the kernel will be running in.
 972
 973 config RAMKERNEL
 974         bool "RAM"
 975         help
 976           The kernel will be resident in RAM when running.
 977
 978 config ROMKERNEL
 979         bool "ROM"
 980         help
 981           The kernel will be resident in FLASH/ROM when running.
 982
 983 endchoice
 984
 985 # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
 986 config XIP_KERNEL
 987         bool
 988         default y
 989         depends on ROMKERNEL
 990
 991 source "mm/Kconfig"
 992
 993 config BFIN_GPTIMERS
 994         tristate "Enable Blackfin General Purpose Timers API"
 995         default n
 996         help
 997           Enable support for the General Purpose Timers API.  If you
 998           are unsure, say N.
 999
1000           To compile this driver as a module, choose M here: the module
1001           will be called gptimers.
1002
1003 choice
1004         prompt "Uncached DMA region"
1005         default DMA_UNCACHED_1M
1006 config DMA_UNCACHED_32M
1007         bool "Enable 32M DMA region"
1008 config DMA_UNCACHED_16M
1009         bool "Enable 16M DMA region"
1010 config DMA_UNCACHED_8M
1011         bool "Enable 8M DMA region"
1012 config DMA_UNCACHED_4M
1013         bool "Enable 4M DMA region"
1014 config DMA_UNCACHED_2M
1015         bool "Enable 2M DMA region"
1016 config DMA_UNCACHED_1M
1017         bool "Enable 1M DMA region"
1018 config DMA_UNCACHED_512K
1019         bool "Enable 512K DMA region"
1020 config DMA_UNCACHED_256K
1021         bool "Enable 256K DMA region"
1022 config DMA_UNCACHED_128K
1023         bool "Enable 128K DMA region"
1024 config DMA_UNCACHED_NONE
1025         bool "Disable DMA region"
1026 endchoice
1027
1028
1029 comment "Cache Support"
1030
1031 config BFIN_ICACHE
1032         bool "Enable ICACHE"
1033         default y
1034 config BFIN_EXTMEM_ICACHEABLE
1035         bool "Enable ICACHE for external memory"
1036         depends on BFIN_ICACHE
1037         default y
1038 config BFIN_L2_ICACHEABLE
1039         bool "Enable ICACHE for L2 SRAM"
1040         depends on BFIN_ICACHE
1041         depends on (BF54x || BF561 || BF60x) && !SMP
1042         default n
1043
1044 config BFIN_DCACHE
1045         bool "Enable DCACHE"
1046         default y
1047 config BFIN_DCACHE_BANKA
1048         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
1049         depends on BFIN_DCACHE && !BF531
1050         default n
1051 config BFIN_EXTMEM_DCACHEABLE
1052         bool "Enable DCACHE for external memory"
1053         depends on BFIN_DCACHE
1054         default y
1055 choice
1056         prompt "External memory DCACHE policy"
1057         depends on BFIN_EXTMEM_DCACHEABLE
1058         default BFIN_EXTMEM_WRITEBACK if !SMP
1059         default BFIN_EXTMEM_WRITETHROUGH if SMP
1060 config BFIN_EXTMEM_WRITEBACK
1061         bool "Write back"
1062         depends on !SMP
1063         help
1064           Write Back Policy:
1065             Cached data will be written back to SDRAM only when needed.
1066             This can give a nice increase in performance, but beware of
1067             broken drivers that do not properly invalidate/flush their
1068             cache.
1069
1070           Write Through Policy:
1071             Cached data will always be written back to SDRAM when the
1072             cache is updated.  This is a completely safe setting, but
1073             performance is worse than Write Back.
1074
1075           If you are unsure of the options and you want to be safe,
1076           then go with Write Through.
1077
1078 config BFIN_EXTMEM_WRITETHROUGH
1079         bool "Write through"
1080         help
1081           Write Back Policy:
1082             Cached data will be written back to SDRAM only when needed.
1083             This can give a nice increase in performance, but beware of
1084             broken drivers that do not properly invalidate/flush their
1085             cache.
1086
1087           Write Through Policy:
1088             Cached data will always be written back to SDRAM when the
1089             cache is updated.  This is a completely safe setting, but
1090             performance is worse than Write Back.
1091
1092           If you are unsure of the options and you want to be safe,
1093           then go with Write Through.
1094
1095 endchoice
1096
1097 config BFIN_L2_DCACHEABLE
1098         bool "Enable DCACHE for L2 SRAM"
1099         depends on BFIN_DCACHE
1100         depends on (BF54x || BF561 || BF60x) && !SMP
1101         default n
1102 choice
1103         prompt "L2 SRAM DCACHE policy"
1104         depends on BFIN_L2_DCACHEABLE
1105         default BFIN_L2_WRITEBACK
1106 config BFIN_L2_WRITEBACK
1107         bool "Write back"
1108
1109 config BFIN_L2_WRITETHROUGH
1110         bool "Write through"
1111 endchoice
1112
1113
1114 comment "Memory Protection Unit"
1115 config MPU
1116         bool "Enable the memory protection unit"
1117         default n
1118         help
1119           Use the processor's MPU to protect applications from accessing
1120           memory they do not own.  This comes at a performance penalty
1121           and is recommended only for debugging.
1122
1123 comment "Asynchronous Memory Configuration"
1124
1125 menu "EBIU_AMGCTL Global Control"
1126         depends on !BF60x
1127 config C_AMCKEN
1128         bool "Enable CLKOUT"
1129         default y
1130
1131 config C_CDPRIO
1132         bool "DMA has priority over core for ext. accesses"
1133         default n
1134
1135 config C_B0PEN
1136         depends on BF561
1137         bool "Bank 0 16 bit packing enable"
1138         default y
1139
1140 config C_B1PEN
1141         depends on BF561
1142         bool "Bank 1 16 bit packing enable"
1143         default y
1144
1145 config C_B2PEN
1146         depends on BF561
1147         bool "Bank 2 16 bit packing enable"
1148         default y
1149
1150 config C_B3PEN
1151         depends on BF561
1152         bool "Bank 3 16 bit packing enable"
1153         default n
1154
1155 choice
1156         prompt "Enable Asynchronous Memory Banks"
1157         default C_AMBEN_ALL
1158
1159 config C_AMBEN
1160         bool "Disable All Banks"
1161
1162 config C_AMBEN_B0
1163         bool "Enable Bank 0"
1164
1165 config C_AMBEN_B0_B1
1166         bool "Enable Bank 0 & 1"
1167
1168 config C_AMBEN_B0_B1_B2
1169         bool "Enable Bank 0 & 1 & 2"
1170
1171 config C_AMBEN_ALL
1172         bool "Enable All Banks"
1173 endchoice
1174 endmenu
1175
1176 menu "EBIU_AMBCTL Control"
1177         depends on !BF60x
1178 config BANK_0
1179         hex "Bank 0 (AMBCTL0.L)"
1180         default 0x7BB0
1181         help
1182           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1183           used to control the Asynchronous Memory Bank 0 settings.
1184
1185 config BANK_1
1186         hex "Bank 1 (AMBCTL0.H)"
1187         default 0x7BB0
1188         default 0x5558 if BF54x
1189         help
1190           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1191           used to control the Asynchronous Memory Bank 1 settings.
1192
1193 config BANK_2
1194         hex "Bank 2 (AMBCTL1.L)"
1195         default 0x7BB0
1196         help
1197           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1198           used to control the Asynchronous Memory Bank 2 settings.
1199
1200 config BANK_3
1201         hex "Bank 3 (AMBCTL1.H)"
1202         default 0x99B3
1203         help
1204           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1205           used to control the Asynchronous Memory Bank 3 settings.
1206
1207 endmenu
1208
1209 config EBIU_MBSCTLVAL
1210         hex "EBIU Bank Select Control Register"
1211         depends on BF54x
1212         default 0
1213
1214 config EBIU_MODEVAL
1215         hex "Flash Memory Mode Control Register"
1216         depends on BF54x
1217         default 1
1218
1219 config EBIU_FCTLVAL
1220         hex "Flash Memory Bank Control Register"
1221         depends on BF54x
1222         default 6
1223 endmenu
1224
1225 #############################################################################
1226 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1227
1228 config PCI
1229         bool "PCI support"
1230         depends on BROKEN
1231         help
1232           Support for PCI bus.
1233
1234 source "drivers/pci/Kconfig"
1235
1236 source "drivers/pcmcia/Kconfig"
1237
1238 endmenu
1239
1240 menu "Executable file formats"
1241
1242 source "fs/Kconfig.binfmt"
1243
1244 endmenu
1245
1246 menu "Power management options"
1247
1248 source "kernel/power/Kconfig"
1249
1250 config ARCH_SUSPEND_POSSIBLE
1251         def_bool y
1252
1253 choice
1254         prompt "Standby Power Saving Mode"
1255         depends on PM && !BF60x
1256         default PM_BFIN_SLEEP_DEEPER
1257 config  PM_BFIN_SLEEP_DEEPER
1258         bool "Sleep Deeper"
1259         help
1260           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1261           power dissipation by disabling the clock to the processor core (CCLK).
1262           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1263           to 0.85 V to provide the greatest power savings, while preserving the
1264           processor state.
1265           The PLL and system clock (SCLK) continue to operate at a very low
1266           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1267           the SDRAM is put into Self Refresh Mode. Typically an external event
1268           such as GPIO interrupt or RTC activity wakes up the processor.
1269           Various Peripherals such as UART, SPORT, PPI may not function as
1270           normal during Sleep Deeper, due to the reduced SCLK frequency.
1271           When in the sleep mode, system DMA access to L1 memory is not supported.
1272
1273           If unsure, select "Sleep Deeper".
1274
1275 config  PM_BFIN_SLEEP
1276         bool "Sleep"
1277         help
1278           Sleep Mode (High Power Savings) - The sleep mode reduces power
1279           dissipation by disabling the clock to the processor core (CCLK).
1280           The PLL and system clock (SCLK), however, continue to operate in
1281           this mode. Typically an external event or RTC activity will wake
1282           up the processor. When in the sleep mode, system DMA access to L1
1283           memory is not supported.
1284
1285           If unsure, select "Sleep Deeper".
1286 endchoice
1287
1288 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1289         depends on PM
1290
1291 config PM_BFIN_WAKE_PH6
1292         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1293         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1294         default n
1295         help
1296           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1297
1298 config PM_BFIN_WAKE_GP
1299         bool "Allow Wake-Up from GPIOs"
1300         depends on PM && BF54x
1301         default n
1302         help
1303           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1304           (all processors, except ADSP-BF549). This option sets
1305           the general-purpose wake-up enable (GPWE) control bit to enable
1306           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1307           On ADSP-BF549 this option enables the same functionality on the
1308           /MRXON pin also PH7.
1309
1310 config PM_BFIN_WAKE_PA15
1311         bool "Allow Wake-Up from PA15"
1312         depends on PM && BF60x
1313         default n
1314         help
1315           Enable PA15 Wake-Up
1316
1317 config PM_BFIN_WAKE_PA15_POL
1318         int "Wake-up priority"
1319         depends on PM_BFIN_WAKE_PA15
1320         default 0
1321         help
1322           Wake-Up priority 0(low) 1(high)
1323
1324 config PM_BFIN_WAKE_PB15
1325         bool "Allow Wake-Up from PB15"
1326         depends on PM && BF60x
1327         default n
1328         help
1329           Enable PB15 Wake-Up
1330
1331 config PM_BFIN_WAKE_PB15_POL
1332         int "Wake-up priority"
1333         depends on PM_BFIN_WAKE_PB15
1334         default 0
1335         help
1336           Wake-Up priority 0(low) 1(high)
1337
1338 config PM_BFIN_WAKE_PC15
1339         bool "Allow Wake-Up from PC15"
1340         depends on PM && BF60x
1341         default n
1342         help
1343           Enable PC15 Wake-Up
1344
1345 config PM_BFIN_WAKE_PC15_POL
1346         int "Wake-up priority"
1347         depends on PM_BFIN_WAKE_PC15
1348         default 0
1349         help
1350           Wake-Up priority 0(low) 1(high)
1351
1352 config PM_BFIN_WAKE_PD06
1353         bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1354         depends on PM && BF60x
1355         default n
1356         help
1357           Enable PD06(ETH0_PHYINT) Wake-up
1358
1359 config PM_BFIN_WAKE_PD06_POL
1360         int "Wake-up priority"
1361         depends on PM_BFIN_WAKE_PD06
1362         default 0
1363         help
1364           Wake-Up priority 0(low) 1(high)
1365
1366 config PM_BFIN_WAKE_PE12
1367         bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1368         depends on PM && BF60x
1369         default n
1370         help
1371           Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1372
1373 config PM_BFIN_WAKE_PE12_POL
1374         int "Wake-up priority"
1375         depends on PM_BFIN_WAKE_PE12
1376         default 0
1377         help
1378           Wake-Up priority 0(low) 1(high)
1379
1380 config PM_BFIN_WAKE_PG04
1381         bool "Allow Wake-Up from PG04(CAN0_RX)"
1382         depends on PM && BF60x
1383         default n
1384         help
1385           Enable PG04(CAN0_RX) Wake-up
1386
1387 config PM_BFIN_WAKE_PG04_POL
1388         int "Wake-up priority"
1389         depends on PM_BFIN_WAKE_PG04
1390         default 0
1391         help
1392           Wake-Up priority 0(low) 1(high)
1393
1394 config PM_BFIN_WAKE_PG13
1395         bool "Allow Wake-Up from PG13"
1396         depends on PM && BF60x
1397         default n
1398         help
1399           Enable PG13 Wake-Up
1400
1401 config PM_BFIN_WAKE_PG13_POL
1402         int "Wake-up priority"
1403         depends on PM_BFIN_WAKE_PG13
1404         default 0
1405         help
1406           Wake-Up priority 0(low) 1(high)
1407
1408 config PM_BFIN_WAKE_USB
1409         bool "Allow Wake-Up from (USB)"
1410         depends on PM && BF60x
1411         default n
1412         help
1413           Enable (USB) Wake-up
1414
1415 config PM_BFIN_WAKE_USB_POL
1416         int "Wake-up priority"
1417         depends on PM_BFIN_WAKE_USB
1418         default 0
1419         help
1420           Wake-Up priority 0(low) 1(high)
1421
1422 endmenu
1423
1424 menu "CPU Frequency scaling"
1425
1426 source "drivers/cpufreq/Kconfig"
1427
1428 config BFIN_CPU_FREQ
1429         bool
1430         depends on CPU_FREQ
1431         default y
1432
1433 config CPU_VOLTAGE
1434         bool "CPU Voltage scaling"
1435         depends on CPU_FREQ
1436         default n
1437         help
1438           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1439           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1440           manuals. There is a theoretical risk that during VDDINT transitions
1441           the PLL may unlock.
1442
1443 endmenu
1444
1445 source "net/Kconfig"
1446
1447 source "drivers/Kconfig"
1448
1449 source "drivers/firmware/Kconfig"
1450
1451 source "fs/Kconfig"
1452
1453 source "arch/blackfin/Kconfig.debug"
1454
1455 source "security/Kconfig"
1456
1457 source "crypto/Kconfig"
1458
1459 source "lib/Kconfig"