arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29
  30 config ZONE_DMA
  31         bool
  32         default y
  33
  34 config GENERIC_FIND_NEXT_BIT
  35         bool
  36         default y
  37
  38 config GENERIC_HWEIGHT
  39         bool
  40         default y
  41
  42 config GENERIC_HARDIRQS
  43         bool
  44         default y
  45
  46 config GENERIC_IRQ_PROBE
  47         bool
  48         default y
  49
  50 config GENERIC_GPIO
  51         bool
  52         default y
  53
  54 config FORCE_MAX_ZONEORDER
  55         int
  56         default "14"
  57
  58 config GENERIC_CALIBRATE_DELAY
  59         bool
  60         default y
  61
  62 config HARDWARE_PM
  63         def_bool y
  64         depends on OPROFILE
  65
  66 source "init/Kconfig"
  67 source "kernel/Kconfig.preempt"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF522
  78         bool "BF522"
  79         help
  80           BF522 Processor Support.
  81
  82 config BF523
  83         bool "BF523"
  84         help
  85           BF523 Processor Support.
  86
  87 config BF524
  88         bool "BF524"
  89         help
  90           BF524 Processor Support.
  91
  92 config BF525
  93         bool "BF525"
  94         help
  95           BF525 Processor Support.
  96
  97 config BF526
  98         bool "BF526"
  99         help
 100           BF526 Processor Support.
 101
 102 config BF527
 103         bool "BF527"
 104         help
 105           BF527 Processor Support.
 106
 107 config BF531
 108         bool "BF531"
 109         help
 110           BF531 Processor Support.
 111
 112 config BF532
 113         bool "BF532"
 114         help
 115           BF532 Processor Support.
 116
 117 config BF533
 118         bool "BF533"
 119         help
 120           BF533 Processor Support.
 121
 122 config BF534
 123         bool "BF534"
 124         help
 125           BF534 Processor Support.
 126
 127 config BF536
 128         bool "BF536"
 129         help
 130           BF536 Processor Support.
 131
 132 config BF537
 133         bool "BF537"
 134         help
 135           BF537 Processor Support.
 136
 137 config BF542
 138         bool "BF542"
 139         help
 140           BF542 Processor Support.
 141
 142 config BF544
 143         bool "BF544"
 144         help
 145           BF544 Processor Support.
 146
 147 config BF547
 148         bool "BF547"
 149         help
 150           BF547 Processor Support.
 151
 152 config BF548
 153         bool "BF548"
 154         help
 155           BF548 Processor Support.
 156
 157 config BF549
 158         bool "BF549"
 159         help
 160           BF549 Processor Support.
 161
 162 config BF561
 163         bool "BF561"
 164         help
 165           BF561 Processor Support.
 166
 167 endchoice
 168
 169 choice
 170         prompt "Silicon Rev"
 171         default BF_REV_0_1 if (BF52x || BF54x)
 172         default BF_REV_0_2 if (BF534 || BF536 || BF537)
 173         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
 174
 175 config BF_REV_0_0
 176         bool "0.0"
 177         depends on (BF52x || BF54x)
 178
 179 config BF_REV_0_1
 180         bool "0.1"
 181         depends on (BF52x || BF54x)
 182
 183 config BF_REV_0_2
 184         bool "0.2"
 185         depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
 186
 187 config BF_REV_0_3
 188         bool "0.3"
 189         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 190
 191 config BF_REV_0_4
 192         bool "0.4"
 193         depends on (BF561 || BF533 || BF532 || BF531)
 194
 195 config BF_REV_0_5
 196         bool "0.5"
 197         depends on (BF561 || BF533 || BF532 || BF531)
 198
 199 config BF_REV_0_6
 200         bool "0.6"
 201         depends on (BF533 || BF532 || BF531)
 202
 203 config BF_REV_ANY
 204         bool "any"
 205
 206 config BF_REV_NONE
 207         bool "none"
 208
 209 endchoice
 210
 211 config BF52x
 212         bool
 213         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 214         default y
 215
 216 config BF53x
 217         bool
 218         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 219         default y
 220
 221 config BF54x
 222         bool
 223         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 224         default y
 225
 226 config MEM_GENERIC_BOARD
 227         bool
 228         depends on GENERIC_BOARD
 229         default y
 230
 231 config MEM_MT48LC64M4A2FB_7E
 232         bool
 233         depends on (BFIN533_STAMP)
 234         default y
 235
 236 config MEM_MT48LC16M16A2TG_75
 237         bool
 238         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 239                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 240                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 241         default y
 242
 243 config MEM_MT48LC32M8A2_75
 244         bool
 245         depends on (BFIN537_STAMP || PNAV10)
 246         default y
 247
 248 config MEM_MT48LC8M32B2B5_7
 249         bool
 250         depends on (BFIN561_BLUETECHNIX_CM)
 251         default y
 252
 253 config MEM_MT48LC32M16A2TG_75
 254         bool
 255         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
 256         default y
 257
 258 source "arch/blackfin/mach-bf527/Kconfig"
 259 source "arch/blackfin/mach-bf533/Kconfig"
 260 source "arch/blackfin/mach-bf561/Kconfig"
 261 source "arch/blackfin/mach-bf537/Kconfig"
 262 source "arch/blackfin/mach-bf548/Kconfig"
 263
 264 menu "Board customizations"
 265
 266 config CMDLINE_BOOL
 267         bool "Default bootloader kernel arguments"
 268
 269 config CMDLINE
 270         string "Initial kernel command string"
 271         depends on CMDLINE_BOOL
 272         default "console=ttyBF0,57600"
 273         help
 274           If you don't have a boot loader capable of passing a command line string
 275           to the kernel, you may specify one here. As a minimum, you should specify
 276           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 277
 278 config BOOT_LOAD
 279         hex "Kernel load address for booting"
 280         default "0x1000"
 281         range 0x1000 0x20000000
 282         help
 283           This option allows you to set the load address of the kernel.
 284           This can be useful if you are on a board which has a small amount
 285           of memory or you wish to reserve some memory at the beginning of
 286           the address space.
 287
 288           Note that you need to keep this value above 4k (0x1000) as this
 289           memory region is used to capture NULL pointer references as well
 290           as some core kernel functions.
 291
 292 config ROM_BASE
 293         hex "Kernel ROM Base"
 294         default "0x20040000"
 295         range 0x20000000 0x20400000 if !(BF54x || BF561)
 296         range 0x20000000 0x30000000 if (BF54x || BF561)
 297         help
 298
 299 comment "Clock/PLL Setup"
 300
 301 config CLKIN_HZ
 302         int "Frequency of the crystal on the board in Hz"
 303         default "11059200" if BFIN533_STAMP
 304         default "27000000" if BFIN533_EZKIT
 305         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
 306         default "30000000" if BFIN561_EZKIT
 307         default "24576000" if PNAV10
 308         default "10000000" if BFIN532_IP0X
 309         help
 310           The frequency of CLKIN crystal oscillator on the board in Hz.
 311           Warning: This value should match the crystal on the board. Otherwise,
 312           peripherals won't work properly.
 313
 314 config BFIN_KERNEL_CLOCK
 315         bool "Re-program Clocks while Kernel boots?"
 316         default n
 317         help
 318           This option decides if kernel clocks are re-programed from the
 319           bootloader settings. If the clocks are not set, the SDRAM settings
 320           are also not changed, and the Bootloader does 100% of the hardware
 321           configuration.
 322
 323 config PLL_BYPASS
 324         bool "Bypass PLL"
 325         depends on BFIN_KERNEL_CLOCK
 326         default n
 327
 328 config CLKIN_HALF
 329         bool "Half Clock In"
 330         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 331         default n
 332         help
 333           If this is set the clock will be divided by 2, before it goes to the PLL.
 334
 335 config VCO_MULT
 336         int "VCO Multiplier"
 337         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 338         range 1 64
 339         default "22" if BFIN533_EZKIT
 340         default "45" if BFIN533_STAMP
 341         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
 342         default "22" if BFIN533_BLUETECHNIX_CM
 343         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 344         default "20" if BFIN561_EZKIT
 345         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
 346         help
 347           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 348           PLL Frequency = (Crystal Frequency) * (this setting)
 349
 350 choice
 351         prompt "Core Clock Divider"
 352         depends on BFIN_KERNEL_CLOCK
 353         default CCLK_DIV_1
 354         help
 355           This sets the frequency of the core. It can be 1, 2, 4 or 8
 356           Core Frequency = (PLL frequency) / (this setting)
 357
 358 config CCLK_DIV_1
 359         bool "1"
 360
 361 config CCLK_DIV_2
 362         bool "2"
 363
 364 config CCLK_DIV_4
 365         bool "4"
 366
 367 config CCLK_DIV_8
 368         bool "8"
 369 endchoice
 370
 371 config SCLK_DIV
 372         int "System Clock Divider"
 373         depends on BFIN_KERNEL_CLOCK
 374         range 1 15
 375         default 5
 376         help
 377           This sets the frequency of the system clock (including SDRAM or DDR).
 378           This can be between 1 and 15
 379           System Clock = (PLL frequency) / (this setting)
 380
 381 choice
 382         prompt "DDR SDRAM Chip Type"
 383         depends on BFIN_KERNEL_CLOCK
 384         depends on BF54x
 385         default MEM_MT46V32M16_5B
 386
 387 config MEM_MT46V32M16_6T
 388         bool "MT46V32M16_6T"
 389
 390 config MEM_MT46V32M16_5B
 391         bool "MT46V32M16_5B"
 392 endchoice
 393
 394 config MAX_MEM_SIZE
 395         int "Max SDRAM Memory Size in MBytes"
 396         depends on !MPU
 397         default 512
 398         help
 399           This is the max memory size that the kernel will create CPLB
 400           tables for.  Your system will not be able to handle any more.
 401
 402 #
 403 # Max & Min Speeds for various Chips
 404 #
 405 config MAX_VCO_HZ
 406         int
 407         default 600000000 if BF522
 408         default 400000000 if BF523
 409         default 400000000 if BF524
 410         default 600000000 if BF525
 411         default 400000000 if BF526
 412         default 600000000 if BF527
 413         default 400000000 if BF531
 414         default 400000000 if BF532
 415         default 750000000 if BF533
 416         default 500000000 if BF534
 417         default 400000000 if BF536
 418         default 600000000 if BF537
 419         default 533333333 if BF538
 420         default 533333333 if BF539
 421         default 600000000 if BF542
 422         default 533333333 if BF544
 423         default 600000000 if BF547
 424         default 600000000 if BF548
 425         default 533333333 if BF549
 426         default 600000000 if BF561
 427
 428 config MIN_VCO_HZ
 429         int
 430         default 50000000
 431
 432 config MAX_SCLK_HZ
 433         int
 434         default 133333333
 435
 436 config MIN_SCLK_HZ
 437         int
 438         default 27000000
 439
 440 comment "Kernel Timer/Scheduler"
 441
 442 source kernel/Kconfig.hz
 443
 444 config GENERIC_TIME
 445         bool "Generic time"
 446         default y
 447
 448 config GENERIC_CLOCKEVENTS
 449         bool "Generic clock events"
 450         depends on GENERIC_TIME
 451         default y
 452
 453 config CYCLES_CLOCKSOURCE
 454         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 455         depends on EXPERIMENTAL
 456         depends on GENERIC_CLOCKEVENTS
 457         depends on !BFIN_SCRATCH_REG_CYCLES
 458         default n
 459         help
 460           If you say Y here, you will enable support for using the 'cycles'
 461           registers as a clock source.  Doing so means you will be unable to
 462           safely write to the 'cycles' register during runtime.  You will
 463           still be able to read it (such as for performance monitoring), but
 464           writing the registers will most likely crash the kernel.
 465
 466 source kernel/time/Kconfig
 467
 468 comment "Misc"
 469
 470 choice
 471         prompt "Blackfin Exception Scratch Register"
 472         default BFIN_SCRATCH_REG_RETN
 473         help
 474           Select the resource to reserve for the Exception handler:
 475             - RETN: Non-Maskable Interrupt (NMI)
 476             - RETE: Exception Return (JTAG/ICE)
 477             - CYCLES: Performance counter
 478
 479           If you are unsure, please select "RETN".
 480
 481 config BFIN_SCRATCH_REG_RETN
 482         bool "RETN"
 483         help
 484           Use the RETN register in the Blackfin exception handler
 485           as a stack scratch register.  This means you cannot
 486           safely use NMI on the Blackfin while running Linux, but
 487           you can debug the system with a JTAG ICE and use the
 488           CYCLES performance registers.
 489
 490           If you are unsure, please select "RETN".
 491
 492 config BFIN_SCRATCH_REG_RETE
 493         bool "RETE"
 494         help
 495           Use the RETE register in the Blackfin exception handler
 496           as a stack scratch register.  This means you cannot
 497           safely use a JTAG ICE while debugging a Blackfin board,
 498           but you can safely use the CYCLES performance registers
 499           and the NMI.
 500
 501           If you are unsure, please select "RETN".
 502
 503 config BFIN_SCRATCH_REG_CYCLES
 504         bool "CYCLES"
 505         help
 506           Use the CYCLES register in the Blackfin exception handler
 507           as a stack scratch register.  This means you cannot
 508           safely use the CYCLES performance registers on a Blackfin
 509           board at anytime, but you can debug the system with a JTAG
 510           ICE and use the NMI.
 511
 512           If you are unsure, please select "RETN".
 513
 514 endchoice
 515
 516 endmenu
 517
 518
 519 menu "Blackfin Kernel Optimizations"
 520
 521 comment "Memory Optimizations"
 522
 523 config I_ENTRY_L1
 524         bool "Locate interrupt entry code in L1 Memory"
 525         default y
 526         help
 527           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 528           into L1 instruction memory. (less latency)
 529
 530 config EXCPT_IRQ_SYSC_L1
 531         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 532         default y
 533         help
 534           If enabled, the entire ASM lowlevel exception and interrupt entry code
 535           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 536           (less latency)
 537
 538 config DO_IRQ_L1
 539         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 540         default y
 541         help
 542           If enabled, the frequently called do_irq dispatcher function is linked
 543           into L1 instruction memory. (less latency)
 544
 545 config CORE_TIMER_IRQ_L1
 546         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 547         default y
 548         help
 549           If enabled, the frequently called timer_interrupt() function is linked
 550           into L1 instruction memory. (less latency)
 551
 552 config IDLE_L1
 553         bool "Locate frequently idle function in L1 Memory"
 554         default y
 555         help
 556           If enabled, the frequently called idle function is linked
 557           into L1 instruction memory. (less latency)
 558
 559 config SCHEDULE_L1
 560         bool "Locate kernel schedule function in L1 Memory"
 561         default y
 562         help
 563           If enabled, the frequently called kernel schedule is linked
 564           into L1 instruction memory. (less latency)
 565
 566 config ARITHMETIC_OPS_L1
 567         bool "Locate kernel owned arithmetic functions in L1 Memory"
 568         default y
 569         help
 570           If enabled, arithmetic functions are linked
 571           into L1 instruction memory. (less latency)
 572
 573 config ACCESS_OK_L1
 574         bool "Locate access_ok function in L1 Memory"
 575         default y
 576         help
 577           If enabled, the access_ok function is linked
 578           into L1 instruction memory. (less latency)
 579
 580 config MEMSET_L1
 581         bool "Locate memset function in L1 Memory"
 582         default y
 583         help
 584           If enabled, the memset function is linked
 585           into L1 instruction memory. (less latency)
 586
 587 config MEMCPY_L1
 588         bool "Locate memcpy function in L1 Memory"
 589         default y
 590         help
 591           If enabled, the memcpy function is linked
 592           into L1 instruction memory. (less latency)
 593
 594 config SYS_BFIN_SPINLOCK_L1
 595         bool "Locate sys_bfin_spinlock function in L1 Memory"
 596         default y
 597         help
 598           If enabled, sys_bfin_spinlock function is linked
 599           into L1 instruction memory. (less latency)
 600
 601 config IP_CHECKSUM_L1
 602         bool "Locate IP Checksum function in L1 Memory"
 603         default n
 604         help
 605           If enabled, the IP Checksum function is linked
 606           into L1 instruction memory. (less latency)
 607
 608 config CACHELINE_ALIGNED_L1
 609         bool "Locate cacheline_aligned data to L1 Data Memory"
 610         default y if !BF54x
 611         default n if BF54x
 612         depends on !BF531
 613         help
 614           If enabled, cacheline_anligned data is linked
 615           into L1 data memory. (less latency)
 616
 617 config SYSCALL_TAB_L1
 618         bool "Locate Syscall Table L1 Data Memory"
 619         default n
 620         depends on !BF531
 621         help
 622           If enabled, the Syscall LUT is linked
 623           into L1 data memory. (less latency)
 624
 625 config CPLB_SWITCH_TAB_L1
 626         bool "Locate CPLB Switch Tables L1 Data Memory"
 627         default n
 628         depends on !BF531
 629         help
 630           If enabled, the CPLB Switch Tables are linked
 631           into L1 data memory. (less latency)
 632
 633 config APP_STACK_L1
 634         bool "Support locating application stack in L1 Scratch Memory"
 635         default y
 636         help
 637           If enabled the application stack can be located in L1
 638           scratch memory (less latency).
 639
 640           Currently only works with FLAT binaries.
 641
 642 comment "Speed Optimizations"
 643 config BFIN_INS_LOWOVERHEAD
 644         bool "ins[bwl] low overhead, higher interrupt latency"
 645         default y
 646         help
 647           Reads on the Blackfin are speculative. In Blackfin terms, this means
 648           they can be interrupted at any time (even after they have been issued
 649           on to the external bus), and re-issued after the interrupt occurs.
 650           For memory - this is not a big deal, since memory does not change if
 651           it sees a read.
 652
 653           If a FIFO is sitting on the end of the read, it will see two reads,
 654           when the core only sees one since the FIFO receives both the read
 655           which is cancelled (and not delivered to the core) and the one which
 656           is re-issued (which is delivered to the core).
 657
 658           To solve this, interrupts are turned off before reads occur to
 659           I/O space. This option controls which the overhead/latency of
 660           controlling interrupts during this time
 661            "n" turns interrupts off every read
 662                 (higher overhead, but lower interrupt latency)
 663            "y" turns interrupts off every loop
 664                 (low overhead, but longer interrupt latency)
 665
 666           default behavior is to leave this set to on (type "Y"). If you are experiencing
 667           interrupt latency issues, it is safe and OK to turn this off.
 668
 669 endmenu
 670
 671
 672 choice
 673         prompt "Kernel executes from"
 674         help
 675           Choose the memory type that the kernel will be running in.
 676
 677 config RAMKERNEL
 678         bool "RAM"
 679         help
 680           The kernel will be resident in RAM when running.
 681
 682 config ROMKERNEL
 683         bool "ROM"
 684         help
 685           The kernel will be resident in FLASH/ROM when running.
 686
 687 endchoice
 688
 689 source "mm/Kconfig"
 690
 691 config BFIN_GPTIMERS
 692         tristate "Enable Blackfin General Purpose Timers API"
 693         default n
 694         help
 695           Enable support for the General Purpose Timers API.  If you
 696           are unsure, say N.
 697
 698           To compile this driver as a module, choose M here: the module
 699           will be called gptimers.ko.
 700
 701 config BFIN_DMA_5XX
 702         bool "Enable DMA Support"
 703         depends on (BF52x || BF53x || BF561 || BF54x)
 704         default y
 705         help
 706           DMA driver for BF5xx.
 707
 708 choice
 709         prompt "Uncached SDRAM region"
 710         default DMA_UNCACHED_1M
 711         depends on BFIN_DMA_5XX
 712 config DMA_UNCACHED_4M
 713         bool "Enable 4M DMA region"
 714 config DMA_UNCACHED_2M
 715         bool "Enable 2M DMA region"
 716 config DMA_UNCACHED_1M
 717         bool "Enable 1M DMA region"
 718 config DMA_UNCACHED_NONE
 719         bool "Disable DMA region"
 720 endchoice
 721
 722
 723 comment "Cache Support"
 724 config BFIN_ICACHE
 725         bool "Enable ICACHE"
 726 config BFIN_DCACHE
 727         bool "Enable DCACHE"
 728 config BFIN_DCACHE_BANKA
 729         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 730         depends on BFIN_DCACHE && !BF531
 731         default n
 732 config BFIN_ICACHE_LOCK
 733         bool "Enable Instruction Cache Locking"
 734
 735 choice
 736         prompt "Policy"
 737         depends on BFIN_DCACHE
 738         default BFIN_WB
 739 config BFIN_WB
 740         bool "Write back"
 741         help
 742           Write Back Policy:
 743             Cached data will be written back to SDRAM only when needed.
 744             This can give a nice increase in performance, but beware of
 745             broken drivers that do not properly invalidate/flush their
 746             cache.
 747
 748           Write Through Policy:
 749             Cached data will always be written back to SDRAM when the
 750             cache is updated.  This is a completely safe setting, but
 751             performance is worse than Write Back.
 752
 753           If you are unsure of the options and you want to be safe,
 754           then go with Write Through.
 755
 756 config BFIN_WT
 757         bool "Write through"
 758         help
 759           Write Back Policy:
 760             Cached data will be written back to SDRAM only when needed.
 761             This can give a nice increase in performance, but beware of
 762             broken drivers that do not properly invalidate/flush their
 763             cache.
 764
 765           Write Through Policy:
 766             Cached data will always be written back to SDRAM when the
 767             cache is updated.  This is a completely safe setting, but
 768             performance is worse than Write Back.
 769
 770           If you are unsure of the options and you want to be safe,
 771           then go with Write Through.
 772
 773 endchoice
 774
 775 config MPU
 776         bool "Enable the memory protection unit (EXPERIMENTAL)"
 777         default n
 778         help
 779           Use the processor's MPU to protect applications from accessing
 780           memory they do not own.  This comes at a performance penalty
 781           and is recommended only for debugging.
 782
 783 comment "Asynchonous Memory Configuration"
 784
 785 menu "EBIU_AMGCTL Global Control"
 786 config C_AMCKEN
 787         bool "Enable CLKOUT"
 788         default y
 789
 790 config C_CDPRIO
 791         bool "DMA has priority over core for ext. accesses"
 792         default n
 793
 794 config C_B0PEN
 795         depends on BF561
 796         bool "Bank 0 16 bit packing enable"
 797         default y
 798
 799 config C_B1PEN
 800         depends on BF561
 801         bool "Bank 1 16 bit packing enable"
 802         default y
 803
 804 config C_B2PEN
 805         depends on BF561
 806         bool "Bank 2 16 bit packing enable"
 807         default y
 808
 809 config C_B3PEN
 810         depends on BF561
 811         bool "Bank 3 16 bit packing enable"
 812         default n
 813
 814 choice
 815         prompt"Enable Asynchonous Memory Banks"
 816         default C_AMBEN_ALL
 817
 818 config C_AMBEN
 819         bool "Disable All Banks"
 820
 821 config C_AMBEN_B0
 822         bool "Enable Bank 0"
 823
 824 config C_AMBEN_B0_B1
 825         bool "Enable Bank 0 & 1"
 826
 827 config C_AMBEN_B0_B1_B2
 828         bool "Enable Bank 0 & 1 & 2"
 829
 830 config C_AMBEN_ALL
 831         bool "Enable All Banks"
 832 endchoice
 833 endmenu
 834
 835 menu "EBIU_AMBCTL Control"
 836 config BANK_0
 837         hex "Bank 0"
 838         default 0x7BB0
 839
 840 config BANK_1
 841         hex "Bank 1"
 842         default 0x7BB0
 843         default 0x5558 if BF54x
 844
 845 config BANK_2
 846         hex "Bank 2"
 847         default 0x7BB0
 848
 849 config BANK_3
 850         hex "Bank 3"
 851         default 0x99B3
 852 endmenu
 853
 854 config EBIU_MBSCTLVAL
 855         hex "EBIU Bank Select Control Register"
 856         depends on BF54x
 857         default 0
 858
 859 config EBIU_MODEVAL
 860         hex "Flash Memory Mode Control Register"
 861         depends on BF54x
 862         default 1
 863
 864 config EBIU_FCTLVAL
 865         hex "Flash Memory Bank Control Register"
 866         depends on BF54x
 867         default 6
 868 endmenu
 869
 870 #############################################################################
 871 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
 872
 873 config PCI
 874         bool "PCI support"
 875         depends on BROKEN
 876         help
 877           Support for PCI bus.
 878
 879 source "drivers/pci/Kconfig"
 880
 881 config HOTPLUG
 882         bool "Support for hot-pluggable device"
 883           help
 884           Say Y here if you want to plug devices into your computer while
 885           the system is running, and be able to use them quickly.  In many
 886           cases, the devices can likewise be unplugged at any time too.
 887
 888           One well known example of this is PCMCIA- or PC-cards, credit-card
 889           size devices such as network cards, modems or hard drives which are
 890           plugged into slots found on all modern laptop computers.  Another
 891           example, used on modern desktops as well as laptops, is USB.
 892
 893           Enable HOTPLUG and build a modular kernel.  Get agent software
 894           (from <http://linux-hotplug.sourceforge.net/>) and install it.
 895           Then your kernel will automatically call out to a user mode "policy
 896           agent" (/sbin/hotplug) to load modules and set up software needed
 897           to use devices as you hotplug them.
 898
 899 source "drivers/pcmcia/Kconfig"
 900
 901 source "drivers/pci/hotplug/Kconfig"
 902
 903 endmenu
 904
 905 menu "Executable file formats"
 906
 907 source "fs/Kconfig.binfmt"
 908
 909 endmenu
 910
 911 menu "Power management options"
 912 source "kernel/power/Kconfig"
 913
 914 config ARCH_SUSPEND_POSSIBLE
 915         def_bool y
 916         depends on !SMP
 917
 918 choice
 919         prompt "Standby Power Saving Mode"
 920         depends on PM
 921         default PM_BFIN_SLEEP_DEEPER
 922 config  PM_BFIN_SLEEP_DEEPER
 923         bool "Sleep Deeper"
 924         help
 925           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
 926           power dissipation by disabling the clock to the processor core (CCLK).
 927           Furthermore, Standby sets the internal power supply voltage (VDDINT)
 928           to 0.85 V to provide the greatest power savings, while preserving the
 929           processor state.
 930           The PLL and system clock (SCLK) continue to operate at a very low
 931           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
 932           the SDRAM is put into Self Refresh Mode. Typically an external event
 933           such as GPIO interrupt or RTC activity wakes up the processor.
 934           Various Peripherals such as UART, SPORT, PPI may not function as
 935           normal during Sleep Deeper, due to the reduced SCLK frequency.
 936           When in the sleep mode, system DMA access to L1 memory is not supported.
 937
 938           If unsure, select "Sleep Deeper".
 939
 940 config  PM_BFIN_SLEEP
 941         bool "Sleep"
 942         help
 943           Sleep Mode (High Power Savings) - The sleep mode reduces power
 944           dissipation by disabling the clock to the processor core (CCLK).
 945           The PLL and system clock (SCLK), however, continue to operate in
 946           this mode. Typically an external event or RTC activity will wake
 947           up the processor. When in the sleep mode, system DMA access to L1
 948           memory is not supported.
 949
 950           If unsure, select "Sleep Deeper".
 951 endchoice
 952
 953 config PM_WAKEUP_BY_GPIO
 954         bool "Allow Wakeup from Standby by GPIO"
 955
 956 config PM_WAKEUP_GPIO_NUMBER
 957         int "GPIO number"
 958         range 0 47
 959         depends on PM_WAKEUP_BY_GPIO
 960         default 2 if BFIN537_STAMP
 961
 962 choice
 963         prompt "GPIO Polarity"
 964         depends on PM_WAKEUP_BY_GPIO
 965         default PM_WAKEUP_GPIO_POLAR_H
 966 config  PM_WAKEUP_GPIO_POLAR_H
 967         bool "Active High"
 968 config  PM_WAKEUP_GPIO_POLAR_L
 969         bool "Active Low"
 970 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
 971         bool "Falling EDGE"
 972 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
 973         bool "Rising EDGE"
 974 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
 975         bool "Both EDGE"
 976 endchoice
 977
 978 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
 979         depends on PM
 980
 981 config PM_BFIN_WAKE_PH6
 982         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
 983         depends on PM && (BF52x || BF534 || BF536 || BF537)
 984         default n
 985         help
 986           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
 987
 988 config PM_BFIN_WAKE_GP
 989         bool "Allow Wake-Up from GPIOs"
 990         depends on PM && BF54x
 991         default n
 992         help
 993           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
 994 endmenu
 995
 996 menu "CPU Frequency scaling"
 997
 998 source "drivers/cpufreq/Kconfig"
 999
1000 config CPU_VOLTAGE
1001         bool "CPU Voltage scaling"
1002         depends on EXPERIMENTAL
1003         depends on CPU_FREQ
1004         default n
1005         help
1006           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1007           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1008           manuals. There is a theoretical risk that during VDDINT transitions
1009           the PLL may unlock.
1010
1011 endmenu
1012
1013 source "net/Kconfig"
1014
1015 source "drivers/Kconfig"
1016
1017 source "fs/Kconfig"
1018
1019 source "arch/blackfin/Kconfig.debug"
1020
1021 source "security/Kconfig"
1022
1023 source "crypto/Kconfig"
1024
1025 source "lib/Kconfig"