arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config MMU
   9         bool
  10         default n
  11
  12 config FPU
  13         bool
  14         default n
  15
  16 config RWSEM_GENERIC_SPINLOCK
  17         bool
  18         default y
  19
  20 config RWSEM_XCHGADD_ALGORITHM
  21         bool
  22         default n
  23
  24 config BLACKFIN
  25         bool
  26         default y
  27         select HAVE_IDE
  28         select HAVE_OPROFILE
  29
  30 config ZONE_DMA
  31         bool
  32         default y
  33
  34 config GENERIC_FIND_NEXT_BIT
  35         bool
  36         default y
  37
  38 config GENERIC_HWEIGHT
  39         bool
  40         default y
  41
  42 config GENERIC_HARDIRQS
  43         bool
  44         default y
  45
  46 config GENERIC_IRQ_PROBE
  47         bool
  48         default y
  49
  50 config GENERIC_GPIO
  51         bool
  52         default y
  53
  54 config FORCE_MAX_ZONEORDER
  55         int
  56         default "14"
  57
  58 config GENERIC_CALIBRATE_DELAY
  59         bool
  60         default y
  61
  62 config HARDWARE_PM
  63         def_bool y
  64         depends on OPROFILE
  65
  66 source "init/Kconfig"
  67 source "kernel/Kconfig.preempt"
  68
  69 menu "Blackfin Processor Options"
  70
  71 comment "Processor and Board Settings"
  72
  73 choice
  74         prompt "CPU"
  75         default BF533
  76
  77 config BF522
  78         bool "BF522"
  79         help
  80           BF522 Processor Support.
  81
  82 config BF523
  83         bool "BF523"
  84         help
  85           BF523 Processor Support.
  86
  87 config BF524
  88         bool "BF524"
  89         help
  90           BF524 Processor Support.
  91
  92 config BF525
  93         bool "BF525"
  94         help
  95           BF525 Processor Support.
  96
  97 config BF526
  98         bool "BF526"
  99         help
 100           BF526 Processor Support.
 101
 102 config BF527
 103         bool "BF527"
 104         help
 105           BF527 Processor Support.
 106
 107 config BF531
 108         bool "BF531"
 109         help
 110           BF531 Processor Support.
 111
 112 config BF532
 113         bool "BF532"
 114         help
 115           BF532 Processor Support.
 116
 117 config BF533
 118         bool "BF533"
 119         help
 120           BF533 Processor Support.
 121
 122 config BF534
 123         bool "BF534"
 124         help
 125           BF534 Processor Support.
 126
 127 config BF536
 128         bool "BF536"
 129         help
 130           BF536 Processor Support.
 131
 132 config BF537
 133         bool "BF537"
 134         help
 135           BF537 Processor Support.
 136
 137 config BF542
 138         bool "BF542"
 139         help
 140           BF542 Processor Support.
 141
 142 config BF544
 143         bool "BF544"
 144         help
 145           BF544 Processor Support.
 146
 147 config BF547
 148         bool "BF547"
 149         help
 150           BF547 Processor Support.
 151
 152 config BF548
 153         bool "BF548"
 154         help
 155           BF548 Processor Support.
 156
 157 config BF549
 158         bool "BF549"
 159         help
 160           BF549 Processor Support.
 161
 162 config BF561
 163         bool "BF561"
 164         help
 165           BF561 Processor Support.
 166
 167 endchoice
 168
 169 config BF_REV_MIN
 170         int
 171         default 0 if (BF52x || BF54x)
 172         default 2 if (BF537 || BF536 || BF534)
 173         default 3 if (BF561 ||BF533 || BF532 || BF531)
 174
 175 config BF_REV_MAX
 176         int
 177         default 2 if (BF52x || BF54x)
 178         default 3 if (BF537 || BF536 || BF534)
 179         default 5 if (BF561)
 180         default 6 if (BF533 || BF532 || BF531)
 181
 182 choice
 183         prompt "Silicon Rev"
 184         default BF_REV_0_1 if (BF52x || BF54x)
 185         default BF_REV_0_2 if (BF534 || BF536 || BF537)
 186         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
 187
 188 config BF_REV_0_0
 189         bool "0.0"
 190         depends on (BF52x || BF54x)
 191
 192 config BF_REV_0_1
 193         bool "0.1"
 194         depends on (BF52x || BF54x)
 195
 196 config BF_REV_0_2
 197         bool "0.2"
 198         depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
 199
 200 config BF_REV_0_3
 201         bool "0.3"
 202         depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 203
 204 config BF_REV_0_4
 205         bool "0.4"
 206         depends on (BF561 || BF533 || BF532 || BF531)
 207
 208 config BF_REV_0_5
 209         bool "0.5"
 210         depends on (BF561 || BF533 || BF532 || BF531)
 211
 212 config BF_REV_0_6
 213         bool "0.6"
 214         depends on (BF533 || BF532 || BF531)
 215
 216 config BF_REV_ANY
 217         bool "any"
 218
 219 config BF_REV_NONE
 220         bool "none"
 221
 222 endchoice
 223
 224 config BF52x
 225         bool
 226         depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
 227         default y
 228
 229 config BF53x
 230         bool
 231         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 232         default y
 233
 234 config BF54x
 235         bool
 236         depends on (BF542 || BF544 || BF547 || BF548 || BF549)
 237         default y
 238
 239 config MEM_GENERIC_BOARD
 240         bool
 241         depends on GENERIC_BOARD
 242         default y
 243
 244 config MEM_MT48LC64M4A2FB_7E
 245         bool
 246         depends on (BFIN533_STAMP)
 247         default y
 248
 249 config MEM_MT48LC16M16A2TG_75
 250         bool
 251         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 252                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
 253                 || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
 254         default y
 255
 256 config MEM_MT48LC32M8A2_75
 257         bool
 258         depends on (BFIN537_STAMP || PNAV10)
 259         default y
 260
 261 config MEM_MT48LC8M32B2B5_7
 262         bool
 263         depends on (BFIN561_BLUETECHNIX_CM)
 264         default y
 265
 266 config MEM_MT48LC32M16A2TG_75
 267         bool
 268         depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
 269         default y
 270
 271 source "arch/blackfin/mach-bf527/Kconfig"
 272 source "arch/blackfin/mach-bf533/Kconfig"
 273 source "arch/blackfin/mach-bf561/Kconfig"
 274 source "arch/blackfin/mach-bf537/Kconfig"
 275 source "arch/blackfin/mach-bf548/Kconfig"
 276
 277 menu "Board customizations"
 278
 279 config CMDLINE_BOOL
 280         bool "Default bootloader kernel arguments"
 281
 282 config CMDLINE
 283         string "Initial kernel command string"
 284         depends on CMDLINE_BOOL
 285         default "console=ttyBF0,57600"
 286         help
 287           If you don't have a boot loader capable of passing a command line string
 288           to the kernel, you may specify one here. As a minimum, you should specify
 289           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 290
 291 config BOOT_LOAD
 292         hex "Kernel load address for booting"
 293         default "0x1000"
 294         range 0x1000 0x20000000
 295         help
 296           This option allows you to set the load address of the kernel.
 297           This can be useful if you are on a board which has a small amount
 298           of memory or you wish to reserve some memory at the beginning of
 299           the address space.
 300
 301           Note that you need to keep this value above 4k (0x1000) as this
 302           memory region is used to capture NULL pointer references as well
 303           as some core kernel functions.
 304
 305 config ROM_BASE
 306         hex "Kernel ROM Base"
 307         default "0x20040000"
 308         range 0x20000000 0x20400000 if !(BF54x || BF561)
 309         range 0x20000000 0x30000000 if (BF54x || BF561)
 310         help
 311
 312 comment "Clock/PLL Setup"
 313
 314 config CLKIN_HZ
 315         int "Frequency of the crystal on the board in Hz"
 316         default "11059200" if BFIN533_STAMP
 317         default "27000000" if BFIN533_EZKIT
 318         default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
 319         default "30000000" if BFIN561_EZKIT
 320         default "24576000" if PNAV10
 321         default "10000000" if BFIN532_IP0X
 322         help
 323           The frequency of CLKIN crystal oscillator on the board in Hz.
 324           Warning: This value should match the crystal on the board. Otherwise,
 325           peripherals won't work properly.
 326
 327 config BFIN_KERNEL_CLOCK
 328         bool "Re-program Clocks while Kernel boots?"
 329         default n
 330         help
 331           This option decides if kernel clocks are re-programed from the
 332           bootloader settings. If the clocks are not set, the SDRAM settings
 333           are also not changed, and the Bootloader does 100% of the hardware
 334           configuration.
 335
 336 config PLL_BYPASS
 337         bool "Bypass PLL"
 338         depends on BFIN_KERNEL_CLOCK
 339         default n
 340
 341 config CLKIN_HALF
 342         bool "Half Clock In"
 343         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 344         default n
 345         help
 346           If this is set the clock will be divided by 2, before it goes to the PLL.
 347
 348 config VCO_MULT
 349         int "VCO Multiplier"
 350         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 351         range 1 64
 352         default "22" if BFIN533_EZKIT
 353         default "45" if BFIN533_STAMP
 354         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
 355         default "22" if BFIN533_BLUETECHNIX_CM
 356         default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 357         default "20" if BFIN561_EZKIT
 358         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
 359         help
 360           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 361           PLL Frequency = (Crystal Frequency) * (this setting)
 362
 363 choice
 364         prompt "Core Clock Divider"
 365         depends on BFIN_KERNEL_CLOCK
 366         default CCLK_DIV_1
 367         help
 368           This sets the frequency of the core. It can be 1, 2, 4 or 8
 369           Core Frequency = (PLL frequency) / (this setting)
 370
 371 config CCLK_DIV_1
 372         bool "1"
 373
 374 config CCLK_DIV_2
 375         bool "2"
 376
 377 config CCLK_DIV_4
 378         bool "4"
 379
 380 config CCLK_DIV_8
 381         bool "8"
 382 endchoice
 383
 384 config SCLK_DIV
 385         int "System Clock Divider"
 386         depends on BFIN_KERNEL_CLOCK
 387         range 1 15
 388         default 5
 389         help
 390           This sets the frequency of the system clock (including SDRAM or DDR).
 391           This can be between 1 and 15
 392           System Clock = (PLL frequency) / (this setting)
 393
 394 choice
 395         prompt "DDR SDRAM Chip Type"
 396         depends on BFIN_KERNEL_CLOCK
 397         depends on BF54x
 398         default MEM_MT46V32M16_5B
 399
 400 config MEM_MT46V32M16_6T
 401         bool "MT46V32M16_6T"
 402
 403 config MEM_MT46V32M16_5B
 404         bool "MT46V32M16_5B"
 405 endchoice
 406
 407 config MAX_MEM_SIZE
 408         int "Max SDRAM Memory Size in MBytes"
 409         depends on !MPU
 410         default 512
 411         help
 412           This is the max memory size that the kernel will create CPLB
 413           tables for.  Your system will not be able to handle any more.
 414
 415 #
 416 # Max & Min Speeds for various Chips
 417 #
 418 config MAX_VCO_HZ
 419         int
 420         default 600000000 if BF522
 421         default 400000000 if BF523
 422         default 400000000 if BF524
 423         default 600000000 if BF525
 424         default 400000000 if BF526
 425         default 600000000 if BF527
 426         default 400000000 if BF531
 427         default 400000000 if BF532
 428         default 750000000 if BF533
 429         default 500000000 if BF534
 430         default 400000000 if BF536
 431         default 600000000 if BF537
 432         default 533333333 if BF538
 433         default 533333333 if BF539
 434         default 600000000 if BF542
 435         default 533333333 if BF544
 436         default 600000000 if BF547
 437         default 600000000 if BF548
 438         default 533333333 if BF549
 439         default 600000000 if BF561
 440
 441 config MIN_VCO_HZ
 442         int
 443         default 50000000
 444
 445 config MAX_SCLK_HZ
 446         int
 447         default 133333333
 448
 449 config MIN_SCLK_HZ
 450         int
 451         default 27000000
 452
 453 comment "Kernel Timer/Scheduler"
 454
 455 source kernel/Kconfig.hz
 456
 457 config GENERIC_TIME
 458         bool "Generic time"
 459         default y
 460
 461 config GENERIC_CLOCKEVENTS
 462         bool "Generic clock events"
 463         depends on GENERIC_TIME
 464         default y
 465
 466 config CYCLES_CLOCKSOURCE
 467         bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
 468         depends on EXPERIMENTAL
 469         depends on GENERIC_CLOCKEVENTS
 470         depends on !BFIN_SCRATCH_REG_CYCLES
 471         default n
 472         help
 473           If you say Y here, you will enable support for using the 'cycles'
 474           registers as a clock source.  Doing so means you will be unable to
 475           safely write to the 'cycles' register during runtime.  You will
 476           still be able to read it (such as for performance monitoring), but
 477           writing the registers will most likely crash the kernel.
 478
 479 source kernel/time/Kconfig
 480
 481 comment "Misc"
 482
 483 choice
 484         prompt "Blackfin Exception Scratch Register"
 485         default BFIN_SCRATCH_REG_RETN
 486         help
 487           Select the resource to reserve for the Exception handler:
 488             - RETN: Non-Maskable Interrupt (NMI)
 489             - RETE: Exception Return (JTAG/ICE)
 490             - CYCLES: Performance counter
 491
 492           If you are unsure, please select "RETN".
 493
 494 config BFIN_SCRATCH_REG_RETN
 495         bool "RETN"
 496         help
 497           Use the RETN register in the Blackfin exception handler
 498           as a stack scratch register.  This means you cannot
 499           safely use NMI on the Blackfin while running Linux, but
 500           you can debug the system with a JTAG ICE and use the
 501           CYCLES performance registers.
 502
 503           If you are unsure, please select "RETN".
 504
 505 config BFIN_SCRATCH_REG_RETE
 506         bool "RETE"
 507         help
 508           Use the RETE register in the Blackfin exception handler
 509           as a stack scratch register.  This means you cannot
 510           safely use a JTAG ICE while debugging a Blackfin board,
 511           but you can safely use the CYCLES performance registers
 512           and the NMI.
 513
 514           If you are unsure, please select "RETN".
 515
 516 config BFIN_SCRATCH_REG_CYCLES
 517         bool "CYCLES"
 518         help
 519           Use the CYCLES register in the Blackfin exception handler
 520           as a stack scratch register.  This means you cannot
 521           safely use the CYCLES performance registers on a Blackfin
 522           board at anytime, but you can debug the system with a JTAG
 523           ICE and use the NMI.
 524
 525           If you are unsure, please select "RETN".
 526
 527 endchoice
 528
 529 endmenu
 530
 531
 532 menu "Blackfin Kernel Optimizations"
 533
 534 comment "Memory Optimizations"
 535
 536 config I_ENTRY_L1
 537         bool "Locate interrupt entry code in L1 Memory"
 538         default y
 539         help
 540           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 541           into L1 instruction memory. (less latency)
 542
 543 config EXCPT_IRQ_SYSC_L1
 544         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 545         default y
 546         help
 547           If enabled, the entire ASM lowlevel exception and interrupt entry code
 548           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 549           (less latency)
 550
 551 config DO_IRQ_L1
 552         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 553         default y
 554         help
 555           If enabled, the frequently called do_irq dispatcher function is linked
 556           into L1 instruction memory. (less latency)
 557
 558 config CORE_TIMER_IRQ_L1
 559         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 560         default y
 561         help
 562           If enabled, the frequently called timer_interrupt() function is linked
 563           into L1 instruction memory. (less latency)
 564
 565 config IDLE_L1
 566         bool "Locate frequently idle function in L1 Memory"
 567         default y
 568         help
 569           If enabled, the frequently called idle function is linked
 570           into L1 instruction memory. (less latency)
 571
 572 config SCHEDULE_L1
 573         bool "Locate kernel schedule function in L1 Memory"
 574         default y
 575         help
 576           If enabled, the frequently called kernel schedule is linked
 577           into L1 instruction memory. (less latency)
 578
 579 config ARITHMETIC_OPS_L1
 580         bool "Locate kernel owned arithmetic functions in L1 Memory"
 581         default y
 582         help
 583           If enabled, arithmetic functions are linked
 584           into L1 instruction memory. (less latency)
 585
 586 config ACCESS_OK_L1
 587         bool "Locate access_ok function in L1 Memory"
 588         default y
 589         help
 590           If enabled, the access_ok function is linked
 591           into L1 instruction memory. (less latency)
 592
 593 config MEMSET_L1
 594         bool "Locate memset function in L1 Memory"
 595         default y
 596         help
 597           If enabled, the memset function is linked
 598           into L1 instruction memory. (less latency)
 599
 600 config MEMCPY_L1
 601         bool "Locate memcpy function in L1 Memory"
 602         default y
 603         help
 604           If enabled, the memcpy function is linked
 605           into L1 instruction memory. (less latency)
 606
 607 config SYS_BFIN_SPINLOCK_L1
 608         bool "Locate sys_bfin_spinlock function in L1 Memory"
 609         default y
 610         help
 611           If enabled, sys_bfin_spinlock function is linked
 612           into L1 instruction memory. (less latency)
 613
 614 config IP_CHECKSUM_L1
 615         bool "Locate IP Checksum function in L1 Memory"
 616         default n
 617         help
 618           If enabled, the IP Checksum function is linked
 619           into L1 instruction memory. (less latency)
 620
 621 config CACHELINE_ALIGNED_L1
 622         bool "Locate cacheline_aligned data to L1 Data Memory"
 623         default y if !BF54x
 624         default n if BF54x
 625         depends on !BF531
 626         help
 627           If enabled, cacheline_anligned data is linked
 628           into L1 data memory. (less latency)
 629
 630 config SYSCALL_TAB_L1
 631         bool "Locate Syscall Table L1 Data Memory"
 632         default n
 633         depends on !BF531
 634         help
 635           If enabled, the Syscall LUT is linked
 636           into L1 data memory. (less latency)
 637
 638 config CPLB_SWITCH_TAB_L1
 639         bool "Locate CPLB Switch Tables L1 Data Memory"
 640         default n
 641         depends on !BF531
 642         help
 643           If enabled, the CPLB Switch Tables are linked
 644           into L1 data memory. (less latency)
 645
 646 config APP_STACK_L1
 647         bool "Support locating application stack in L1 Scratch Memory"
 648         default y
 649         help
 650           If enabled the application stack can be located in L1
 651           scratch memory (less latency).
 652
 653           Currently only works with FLAT binaries.
 654
 655 comment "Speed Optimizations"
 656 config BFIN_INS_LOWOVERHEAD
 657         bool "ins[bwl] low overhead, higher interrupt latency"
 658         default y
 659         help
 660           Reads on the Blackfin are speculative. In Blackfin terms, this means
 661           they can be interrupted at any time (even after they have been issued
 662           on to the external bus), and re-issued after the interrupt occurs.
 663           For memory - this is not a big deal, since memory does not change if
 664           it sees a read.
 665
 666           If a FIFO is sitting on the end of the read, it will see two reads,
 667           when the core only sees one since the FIFO receives both the read
 668           which is cancelled (and not delivered to the core) and the one which
 669           is re-issued (which is delivered to the core).
 670
 671           To solve this, interrupts are turned off before reads occur to
 672           I/O space. This option controls which the overhead/latency of
 673           controlling interrupts during this time
 674            "n" turns interrupts off every read
 675                 (higher overhead, but lower interrupt latency)
 676            "y" turns interrupts off every loop
 677                 (low overhead, but longer interrupt latency)
 678
 679           default behavior is to leave this set to on (type "Y"). If you are experiencing
 680           interrupt latency issues, it is safe and OK to turn this off.
 681
 682 endmenu
 683
 684
 685 choice
 686         prompt "Kernel executes from"
 687         help
 688           Choose the memory type that the kernel will be running in.
 689
 690 config RAMKERNEL
 691         bool "RAM"
 692         help
 693           The kernel will be resident in RAM when running.
 694
 695 config ROMKERNEL
 696         bool "ROM"
 697         help
 698           The kernel will be resident in FLASH/ROM when running.
 699
 700 endchoice
 701
 702 source "mm/Kconfig"
 703
 704 config BFIN_GPTIMERS
 705         tristate "Enable Blackfin General Purpose Timers API"
 706         default n
 707         help
 708           Enable support for the General Purpose Timers API.  If you
 709           are unsure, say N.
 710
 711           To compile this driver as a module, choose M here: the module
 712           will be called gptimers.ko.
 713
 714 config BFIN_DMA_5XX
 715         bool "Enable DMA Support"
 716         depends on (BF52x || BF53x || BF561 || BF54x)
 717         default y
 718         help
 719           DMA driver for BF5xx.
 720
 721 choice
 722         prompt "Uncached SDRAM region"
 723         default DMA_UNCACHED_1M
 724         depends on BFIN_DMA_5XX
 725 config DMA_UNCACHED_4M
 726         bool "Enable 4M DMA region"
 727 config DMA_UNCACHED_2M
 728         bool "Enable 2M DMA region"
 729 config DMA_UNCACHED_1M
 730         bool "Enable 1M DMA region"
 731 config DMA_UNCACHED_NONE
 732         bool "Disable DMA region"
 733 endchoice
 734
 735
 736 comment "Cache Support"
 737 config BFIN_ICACHE
 738         bool "Enable ICACHE"
 739 config BFIN_DCACHE
 740         bool "Enable DCACHE"
 741 config BFIN_DCACHE_BANKA
 742         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 743         depends on BFIN_DCACHE && !BF531
 744         default n
 745 config BFIN_ICACHE_LOCK
 746         bool "Enable Instruction Cache Locking"
 747
 748 choice
 749         prompt "Policy"
 750         depends on BFIN_DCACHE
 751         default BFIN_WB
 752 config BFIN_WB
 753         bool "Write back"
 754         help
 755           Write Back Policy:
 756             Cached data will be written back to SDRAM only when needed.
 757             This can give a nice increase in performance, but beware of
 758             broken drivers that do not properly invalidate/flush their
 759             cache.
 760
 761           Write Through Policy:
 762             Cached data will always be written back to SDRAM when the
 763             cache is updated.  This is a completely safe setting, but
 764             performance is worse than Write Back.
 765
 766           If you are unsure of the options and you want to be safe,
 767           then go with Write Through.
 768
 769 config BFIN_WT
 770         bool "Write through"
 771         help
 772           Write Back Policy:
 773             Cached data will be written back to SDRAM only when needed.
 774             This can give a nice increase in performance, but beware of
 775             broken drivers that do not properly invalidate/flush their
 776             cache.
 777
 778           Write Through Policy:
 779             Cached data will always be written back to SDRAM when the
 780             cache is updated.  This is a completely safe setting, but
 781             performance is worse than Write Back.
 782
 783           If you are unsure of the options and you want to be safe,
 784           then go with Write Through.
 785
 786 endchoice
 787
 788 config BFIN_L2_CACHEABLE
 789         bool "Cache L2 SRAM"
 790         depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
 791         default n
 792         help
 793           Select to make L2 SRAM cacheable in L1 data and instruction cache.
 794
 795 config MPU
 796         bool "Enable the memory protection unit (EXPERIMENTAL)"
 797         default n
 798         help
 799           Use the processor's MPU to protect applications from accessing
 800           memory they do not own.  This comes at a performance penalty
 801           and is recommended only for debugging.
 802
 803 comment "Asynchonous Memory Configuration"
 804
 805 menu "EBIU_AMGCTL Global Control"
 806 config C_AMCKEN
 807         bool "Enable CLKOUT"
 808         default y
 809
 810 config C_CDPRIO
 811         bool "DMA has priority over core for ext. accesses"
 812         default n
 813
 814 config C_B0PEN
 815         depends on BF561
 816         bool "Bank 0 16 bit packing enable"
 817         default y
 818
 819 config C_B1PEN
 820         depends on BF561
 821         bool "Bank 1 16 bit packing enable"
 822         default y
 823
 824 config C_B2PEN
 825         depends on BF561
 826         bool "Bank 2 16 bit packing enable"
 827         default y
 828
 829 config C_B3PEN
 830         depends on BF561
 831         bool "Bank 3 16 bit packing enable"
 832         default n
 833
 834 choice
 835         prompt"Enable Asynchonous Memory Banks"
 836         default C_AMBEN_ALL
 837
 838 config C_AMBEN
 839         bool "Disable All Banks"
 840
 841 config C_AMBEN_B0
 842         bool "Enable Bank 0"
 843
 844 config C_AMBEN_B0_B1
 845         bool "Enable Bank 0 & 1"
 846
 847 config C_AMBEN_B0_B1_B2
 848         bool "Enable Bank 0 & 1 & 2"
 849
 850 config C_AMBEN_ALL
 851         bool "Enable All Banks"
 852 endchoice
 853 endmenu
 854
 855 menu "EBIU_AMBCTL Control"
 856 config BANK_0
 857         hex "Bank 0"
 858         default 0x7BB0
 859
 860 config BANK_1
 861         hex "Bank 1"
 862         default 0x7BB0
 863         default 0x5558 if BF54x
 864
 865 config BANK_2
 866         hex "Bank 2"
 867         default 0x7BB0
 868
 869 config BANK_3
 870         hex "Bank 3"
 871         default 0x99B3
 872 endmenu
 873
 874 config EBIU_MBSCTLVAL
 875         hex "EBIU Bank Select Control Register"
 876         depends on BF54x
 877         default 0
 878
 879 config EBIU_MODEVAL
 880         hex "Flash Memory Mode Control Register"
 881         depends on BF54x
 882         default 1
 883
 884 config EBIU_FCTLVAL
 885         hex "Flash Memory Bank Control Register"
 886         depends on BF54x
 887         default 6
 888 endmenu
 889
 890 #############################################################################
 891 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
 892
 893 config PCI
 894         bool "PCI support"
 895         depends on BROKEN
 896         help
 897           Support for PCI bus.
 898
 899 source "drivers/pci/Kconfig"
 900
 901 config HOTPLUG
 902         bool "Support for hot-pluggable device"
 903           help
 904           Say Y here if you want to plug devices into your computer while
 905           the system is running, and be able to use them quickly.  In many
 906           cases, the devices can likewise be unplugged at any time too.
 907
 908           One well known example of this is PCMCIA- or PC-cards, credit-card
 909           size devices such as network cards, modems or hard drives which are
 910           plugged into slots found on all modern laptop computers.  Another
 911           example, used on modern desktops as well as laptops, is USB.
 912
 913           Enable HOTPLUG and build a modular kernel.  Get agent software
 914           (from <http://linux-hotplug.sourceforge.net/>) and install it.
 915           Then your kernel will automatically call out to a user mode "policy
 916           agent" (/sbin/hotplug) to load modules and set up software needed
 917           to use devices as you hotplug them.
 918
 919 source "drivers/pcmcia/Kconfig"
 920
 921 source "drivers/pci/hotplug/Kconfig"
 922
 923 endmenu
 924
 925 menu "Executable file formats"
 926
 927 source "fs/Kconfig.binfmt"
 928
 929 endmenu
 930
 931 menu "Power management options"
 932 source "kernel/power/Kconfig"
 933
 934 config ARCH_SUSPEND_POSSIBLE
 935         def_bool y
 936         depends on !SMP
 937
 938 choice
 939         prompt "Standby Power Saving Mode"
 940         depends on PM
 941         default PM_BFIN_SLEEP_DEEPER
 942 config  PM_BFIN_SLEEP_DEEPER
 943         bool "Sleep Deeper"
 944         help
 945           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
 946           power dissipation by disabling the clock to the processor core (CCLK).
 947           Furthermore, Standby sets the internal power supply voltage (VDDINT)
 948           to 0.85 V to provide the greatest power savings, while preserving the
 949           processor state.
 950           The PLL and system clock (SCLK) continue to operate at a very low
 951           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
 952           the SDRAM is put into Self Refresh Mode. Typically an external event
 953           such as GPIO interrupt or RTC activity wakes up the processor.
 954           Various Peripherals such as UART, SPORT, PPI may not function as
 955           normal during Sleep Deeper, due to the reduced SCLK frequency.
 956           When in the sleep mode, system DMA access to L1 memory is not supported.
 957
 958           If unsure, select "Sleep Deeper".
 959
 960 config  PM_BFIN_SLEEP
 961         bool "Sleep"
 962         help
 963           Sleep Mode (High Power Savings) - The sleep mode reduces power
 964           dissipation by disabling the clock to the processor core (CCLK).
 965           The PLL and system clock (SCLK), however, continue to operate in
 966           this mode. Typically an external event or RTC activity will wake
 967           up the processor. When in the sleep mode, system DMA access to L1
 968           memory is not supported.
 969
 970           If unsure, select "Sleep Deeper".
 971 endchoice
 972
 973 config PM_WAKEUP_BY_GPIO
 974         bool "Allow Wakeup from Standby by GPIO"
 975
 976 config PM_WAKEUP_GPIO_NUMBER
 977         int "GPIO number"
 978         range 0 47
 979         depends on PM_WAKEUP_BY_GPIO
 980         default 2 if BFIN537_STAMP
 981
 982 choice
 983         prompt "GPIO Polarity"
 984         depends on PM_WAKEUP_BY_GPIO
 985         default PM_WAKEUP_GPIO_POLAR_H
 986 config  PM_WAKEUP_GPIO_POLAR_H
 987         bool "Active High"
 988 config  PM_WAKEUP_GPIO_POLAR_L
 989         bool "Active Low"
 990 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
 991         bool "Falling EDGE"
 992 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
 993         bool "Rising EDGE"
 994 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
 995         bool "Both EDGE"
 996 endchoice
 997
 998 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
 999         depends on PM
1000
1001 config PM_BFIN_WAKE_PH6
1002         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1003         depends on PM && (BF52x || BF534 || BF536 || BF537)
1004         default n
1005         help
1006           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1007
1008 config PM_BFIN_WAKE_GP
1009         bool "Allow Wake-Up from GPIOs"
1010         depends on PM && BF54x
1011         default n
1012         help
1013           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1014 endmenu
1015
1016 menu "CPU Frequency scaling"
1017
1018 source "drivers/cpufreq/Kconfig"
1019
1020 config CPU_VOLTAGE
1021         bool "CPU Voltage scaling"
1022         depends on EXPERIMENTAL
1023         depends on CPU_FREQ
1024         default n
1025         help
1026           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1027           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1028           manuals. There is a theoretical risk that during VDDINT transitions
1029           the PLL may unlock.
1030
1031 endmenu
1032
1033 source "net/Kconfig"
1034
1035 source "drivers/Kconfig"
1036
1037 source "fs/Kconfig"
1038
1039 source "arch/blackfin/Kconfig.debug"
1040
1041 source "security/Kconfig"
1042
1043 source "crypto/Kconfig"
1044
1045 source "lib/Kconfig"