2 * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
3 * (C) 2002 Padraig Brady. <padraig@antefacto.com>
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon datasheets & sample CPUs kindly provided by VIA.
8 * VIA have currently 3 different versions of Longhaul.
9 * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10 * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11 * Version 2 of longhaul is the same as v1, but adds voltage scaling.
12 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C)
13 * voltage scaling support has currently been disabled in this driver
14 * until we have code that gets it right.
15 * Version 3 of longhaul got renamed to Powersaver and redesigned
16 * to use the POWERSAVER MSR at 0x110a.
17 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
18 * It's pretty much the same feature wise to longhaul v2, though
19 * there is provision for scaling FSB too, but this doesn't work
20 * too well in practice so we don't even try to use this.
22 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/init.h>
29 #include <linux/cpufreq.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/string.h>
35 #include <asm/timex.h>
38 #include <linux/acpi.h>
39 #include <acpi/processor.h>
43 #define PFX "longhaul: "
45 #define TYPE_LONGHAUL_V1 1
46 #define TYPE_LONGHAUL_V2 2
47 #define TYPE_POWERSAVER 3
53 #define CPU_NEHEMIAH 5
56 #define USE_ACPI_C3 (1 << 1)
57 #define USE_NORTHBRIDGE (1 << 2)
60 static unsigned int numscales
=16;
61 static unsigned int fsb
;
63 static struct mV_pos
*vrm_mV_table
;
64 static unsigned char *mV_vrm_table
;
68 static struct f_msr f_msr_table
[32];
70 static unsigned int highest_speed
, lowest_speed
; /* kHz */
71 static unsigned int minmult
, maxmult
;
72 static int can_scale_voltage
;
73 static struct acpi_processor
*pr
= NULL
;
74 static struct acpi_processor_cx
*cx
= NULL
;
75 static u8 longhaul_flags
;
77 /* Module parameters */
78 static int scale_voltage
;
79 static int ignore_latency
;
81 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
84 /* Clock ratios multiplied by 10 */
85 static int clock_ratio
[32];
86 static int eblcr_table
[32];
87 static int longhaul_version
;
88 static struct cpufreq_frequency_table
*longhaul_table
;
90 #ifdef CONFIG_CPU_FREQ_DEBUG
91 static char speedbuffer
[8];
93 static char *print_speed(int speed
)
96 snprintf(speedbuffer
, sizeof(speedbuffer
),"%dMHz", speed
);
101 snprintf(speedbuffer
, sizeof(speedbuffer
),
102 "%dGHz", speed
/1000);
104 snprintf(speedbuffer
, sizeof(speedbuffer
),
105 "%d.%dGHz", speed
/1000, (speed
%1000)/100);
112 static unsigned int calc_speed(int mult
)
123 static int longhaul_get_cpu_mult(void)
125 unsigned long invalue
=0,lo
, hi
;
127 rdmsr (MSR_IA32_EBL_CR_POWERON
, lo
, hi
);
128 invalue
= (lo
& (1<<22|1<<23|1<<24|1<<25)) >>22;
129 if (longhaul_version
==TYPE_LONGHAUL_V2
|| longhaul_version
==TYPE_POWERSAVER
) {
133 return eblcr_table
[invalue
];
136 /* For processor with BCR2 MSR */
138 static void do_longhaul1(unsigned int clock_ratio_index
)
142 rdmsrl(MSR_VIA_BCR2
, bcr2
.val
);
143 /* Enable software clock multiplier */
144 bcr2
.bits
.ESOFTBF
= 1;
145 bcr2
.bits
.CLOCKMUL
= clock_ratio_index
;
147 /* Sync to timer tick */
149 /* Change frequency on next halt or sleep */
150 wrmsrl(MSR_VIA_BCR2
, bcr2
.val
);
151 /* Invoke transition */
152 ACPI_FLUSH_CPU_CACHE();
155 /* Disable software clock multiplier */
157 rdmsrl(MSR_VIA_BCR2
, bcr2
.val
);
158 bcr2
.bits
.ESOFTBF
= 0;
159 wrmsrl(MSR_VIA_BCR2
, bcr2
.val
);
162 /* For processor with Longhaul MSR */
164 static void do_powersaver(int cx_address
, unsigned int clock_ratio_index
)
166 union msr_longhaul longhaul
;
169 rdmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
170 longhaul
.bits
.RevisionKey
= longhaul
.bits
.RevisionID
;
171 longhaul
.bits
.SoftBusRatio
= clock_ratio_index
& 0xf;
172 longhaul
.bits
.SoftBusRatio4
= (clock_ratio_index
& 0x10) >> 4;
173 longhaul
.bits
.EnableSoftBusRatio
= 1;
175 if (can_scale_voltage
) {
176 longhaul
.bits
.SoftVID
= f_msr_table
[clock_ratio_index
].vrm
;
177 longhaul
.bits
.EnableSoftVID
= 1;
180 /* Sync to timer tick */
182 /* Change frequency on next halt or sleep */
183 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
185 ACPI_FLUSH_CPU_CACHE();
189 ACPI_FLUSH_CPU_CACHE();
192 /* Dummy op - must do something useless after P_LVL3 read */
193 t
= inl(acpi_fadt
.xpm_tmr_blk
.address
);
195 /* Disable bus ratio bit */
197 longhaul
.bits
.RevisionKey
= longhaul
.bits
.RevisionID
;
198 longhaul
.bits
.EnableSoftBusRatio
= 0;
199 longhaul
.bits
.EnableSoftBSEL
= 0;
200 longhaul
.bits
.EnableSoftVID
= 0;
201 wrmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
205 * longhaul_set_cpu_frequency()
206 * @clock_ratio_index : bitpattern of the new multiplier.
208 * Sets a new clock ratio.
211 static void longhaul_setstate(unsigned int clock_ratio_index
)
214 struct cpufreq_freqs freqs
;
215 static unsigned int old_ratio
=-1;
217 unsigned int pic1_mask
, pic2_mask
;
219 if (old_ratio
== clock_ratio_index
)
221 old_ratio
= clock_ratio_index
;
223 mult
= clock_ratio
[clock_ratio_index
];
227 speed
= calc_speed(mult
);
228 if ((speed
> highest_speed
) || (speed
< lowest_speed
))
231 freqs
.old
= calc_speed(longhaul_get_cpu_mult());
233 freqs
.cpu
= 0; /* longhaul.c is UP only driver */
235 cpufreq_notify_transition(&freqs
, CPUFREQ_PRECHANGE
);
237 dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
238 fsb
, mult
/10, mult
%10, print_speed(speed
/1000));
241 local_irq_save(flags
);
243 pic2_mask
= inb(0xA1);
244 pic1_mask
= inb(0x21); /* works on C3. save mask. */
245 outb(0xFF,0xA1); /* Overkill */
246 outb(0xFE,0x21); /* TMR0 only */
248 if (longhaul_flags
& USE_NORTHBRIDGE
) {
249 /* Disable AGP and PCI arbiters */
251 } else if ((pr
!= NULL
) && pr
->flags
.bm_control
) {
252 /* Disable bus master arbitration */
253 acpi_set_register(ACPI_BITREG_ARB_DISABLE
, 1,
254 ACPI_MTX_DO_NOT_LOCK
);
256 switch (longhaul_version
) {
259 * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
260 * Software controlled multipliers only.
262 * *NB* Until we get voltage scaling working v1 & v2 are the same code.
263 * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C]
265 case TYPE_LONGHAUL_V1
:
266 case TYPE_LONGHAUL_V2
:
267 do_longhaul1(clock_ratio_index
);
271 * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
272 * We can scale voltage with this too, but that's currently
273 * disabled until we come up with a decent 'match freq to voltage'
275 * When we add voltage scaling, we will also need to do the
276 * voltage/freq setting in order depending on the direction
277 * of scaling (like we do in powernow-k7.c)
278 * Nehemiah can do FSB scaling too, but this has never been proven
279 * to work in practice.
281 case TYPE_POWERSAVER
:
282 if (longhaul_flags
& USE_ACPI_C3
) {
283 /* Don't allow wakeup */
284 acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD
, 0,
285 ACPI_MTX_DO_NOT_LOCK
);
286 do_powersaver(cx
->address
, clock_ratio_index
);
288 do_powersaver(0, clock_ratio_index
);
293 if (longhaul_flags
& USE_NORTHBRIDGE
) {
294 /* Enable arbiters */
296 } else if ((pr
!= NULL
) && pr
->flags
.bm_control
) {
297 /* Enable bus master arbitration */
298 acpi_set_register(ACPI_BITREG_ARB_DISABLE
, 0,
299 ACPI_MTX_DO_NOT_LOCK
);
301 outb(pic2_mask
,0xA1); /* restore mask */
302 outb(pic1_mask
,0x21);
304 local_irq_restore(flags
);
307 cpufreq_notify_transition(&freqs
, CPUFREQ_POSTCHANGE
);
311 * Centaur decided to make life a little more tricky.
312 * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
313 * Samuel2 and above have to try and guess what the FSB is.
314 * We do this by assuming we booted at maximum multiplier, and interpolate
315 * between that value multiplied by possible FSBs and cpu_mhz which
316 * was calculated at boot time. Really ugly, but no other way to do this.
321 static int _guess(int guess
, int mult
)
325 target
= ((mult
/10)*guess
);
328 target
+= ROUNDING
/2;
334 static int guess_fsb(int mult
)
336 int speed
= (cpu_khz
/1000);
338 int speeds
[] = { 66, 100, 133, 200 };
343 for (i
=0; i
<4; i
++) {
344 if (_guess(speeds
[i
], mult
) == speed
)
351 static int __init
longhaul_get_ranges(void)
353 unsigned long invalue
;
354 unsigned int ezra_t_multipliers
[32]= {
355 90, 30, 40, 100, 55, 35, 45, 95,
356 50, 70, 80, 60, 120, 75, 85, 65,
357 -1, 110, 120, -1, 135, 115, 125, 105,
358 130, 150, 160, 140, -1, 155, -1, 145 };
359 unsigned int j
, k
= 0;
360 union msr_longhaul longhaul
;
363 switch (longhaul_version
) {
364 case TYPE_LONGHAUL_V1
:
365 case TYPE_LONGHAUL_V2
:
366 /* Ugh, Longhaul v1 didn't have the min/max MSRs.
367 Assume min=3.0x & max = whatever we booted at. */
369 maxmult
= mult
= longhaul_get_cpu_mult();
372 case TYPE_POWERSAVER
:
374 if (cpu_model
==CPU_EZRA_T
) {
376 rdmsrl (MSR_VIA_LONGHAUL
, longhaul
.val
);
377 invalue
= longhaul
.bits
.MaxMHzBR
;
378 if (longhaul
.bits
.MaxMHzBR4
)
380 maxmult
= mult
= ezra_t_multipliers
[invalue
];
385 if (cpu_model
==CPU_NEHEMIAH
) {
386 rdmsrl (MSR_VIA_LONGHAUL
, longhaul
.val
);
389 * TODO: This code works, but raises a lot of questions.
390 * - Some Nehemiah's seem to have broken Min/MaxMHzBR's.
391 * We get around this by using a hardcoded multiplier of 4.0x
392 * for the minimimum speed, and the speed we booted up at for the max.
393 * This is done in longhaul_get_cpu_mult() by reading the EBLCR register.
394 * - According to some VIA documentation EBLCR is only
395 * in pre-Nehemiah C3s. How this still works is a mystery.
396 * We're possibly using something undocumented and unsupported,
397 * But it works, so we don't grumble.
400 maxmult
= mult
= longhaul_get_cpu_mult();
404 fsb
= guess_fsb(mult
);
406 dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
407 minmult
/10, minmult
%10, maxmult
/10, maxmult
%10);
410 printk (KERN_INFO PFX
"Invalid (reserved) FSB!\n");
414 highest_speed
= calc_speed(maxmult
);
415 lowest_speed
= calc_speed(minmult
);
416 dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb
,
417 print_speed(lowest_speed
/1000),
418 print_speed(highest_speed
/1000));
420 if (lowest_speed
== highest_speed
) {
421 printk (KERN_INFO PFX
"highestspeed == lowest, aborting.\n");
424 if (lowest_speed
> highest_speed
) {
425 printk (KERN_INFO PFX
"nonsense! lowest (%d > %d) !\n",
426 lowest_speed
, highest_speed
);
430 longhaul_table
= kmalloc((numscales
+ 1) * sizeof(struct cpufreq_frequency_table
), GFP_KERNEL
);
434 for (j
=0; j
< numscales
; j
++) {
436 ratio
= clock_ratio
[j
];
439 if (ratio
> maxmult
|| ratio
< minmult
)
441 longhaul_table
[k
].frequency
= calc_speed(ratio
);
442 longhaul_table
[k
].index
= j
;
446 longhaul_table
[k
].frequency
= CPUFREQ_TABLE_END
;
448 kfree (longhaul_table
);
456 static void __init
longhaul_setup_voltagescaling(void)
458 union msr_longhaul longhaul
;
459 struct mV_pos minvid
, maxvid
;
460 unsigned int j
, speed
, pos
, kHz_step
, numvscales
;
462 rdmsrl(MSR_VIA_LONGHAUL
, longhaul
.val
);
463 if (!(longhaul
.bits
.RevisionID
& 1)) {
464 printk(KERN_INFO PFX
"Voltage scaling not supported by CPU.\n");
468 if (!longhaul
.bits
.VRMRev
) {
469 printk (KERN_INFO PFX
"VRM 8.5\n");
470 vrm_mV_table
= &vrm85_mV
[0];
471 mV_vrm_table
= &mV_vrm85
[0];
473 printk (KERN_INFO PFX
"Mobile VRM\n");
474 vrm_mV_table
= &mobilevrm_mV
[0];
475 mV_vrm_table
= &mV_mobilevrm
[0];
478 minvid
= vrm_mV_table
[longhaul
.bits
.MinimumVID
];
479 maxvid
= vrm_mV_table
[longhaul
.bits
.MaximumVID
];
480 numvscales
= maxvid
.pos
- minvid
.pos
+ 1;
481 kHz_step
= (highest_speed
- lowest_speed
) / numvscales
;
483 if (minvid
.mV
== 0 || maxvid
.mV
== 0 || minvid
.mV
> maxvid
.mV
) {
484 printk (KERN_INFO PFX
"Bogus values Min:%d.%03d Max:%d.%03d. "
485 "Voltage scaling disabled.\n",
486 minvid
.mV
/1000, minvid
.mV
%1000, maxvid
.mV
/1000, maxvid
.mV
%1000);
490 if (minvid
.mV
== maxvid
.mV
) {
491 printk (KERN_INFO PFX
"Claims to support voltage scaling but min & max are "
492 "both %d.%03d. Voltage scaling disabled\n",
493 maxvid
.mV
/1000, maxvid
.mV
%1000);
497 printk(KERN_INFO PFX
"Max VID=%d.%03d Min VID=%d.%03d, %d possible voltage scales\n",
498 maxvid
.mV
/1000, maxvid
.mV
%1000,
499 minvid
.mV
/1000, minvid
.mV
%1000,
503 while (longhaul_table
[j
].frequency
!= CPUFREQ_TABLE_END
) {
504 speed
= longhaul_table
[j
].frequency
;
505 pos
= (speed
- lowest_speed
) / kHz_step
+ minvid
.pos
;
506 f_msr_table
[longhaul_table
[j
].index
].vrm
= mV_vrm_table
[pos
];
510 can_scale_voltage
= 1;
514 static int longhaul_verify(struct cpufreq_policy
*policy
)
516 return cpufreq_frequency_table_verify(policy
, longhaul_table
);
520 static int longhaul_target(struct cpufreq_policy
*policy
,
521 unsigned int target_freq
, unsigned int relation
)
523 unsigned int table_index
= 0;
524 unsigned int new_clock_ratio
= 0;
526 if (cpufreq_frequency_table_target(policy
, longhaul_table
, target_freq
, relation
, &table_index
))
529 new_clock_ratio
= longhaul_table
[table_index
].index
& 0xFF;
531 longhaul_setstate(new_clock_ratio
);
537 static unsigned int longhaul_get(unsigned int cpu
)
541 return calc_speed(longhaul_get_cpu_mult());
544 static acpi_status
longhaul_walk_callback(acpi_handle obj_handle
,
546 void *context
, void **return_value
)
548 struct acpi_device
*d
;
550 if ( acpi_bus_get_device(obj_handle
, &d
) ) {
553 *return_value
= (void *)acpi_driver_data(d
);
557 /* VIA don't support PM2 reg, but have something similar */
558 static int enable_arbiter_disable(void)
564 /* Find PLE133 host bridge */
566 dev
= pci_find_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8601_0
, NULL
);
567 /* Find CLE266 host bridge */
570 dev
= pci_find_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_862X_0
, NULL
);
571 /* Find CN400 V-Link host bridge */
573 dev
= pci_find_device(PCI_VENDOR_ID_VIA
, 0x7259, NULL
);
577 /* Enable access to port 0x22 */
578 pci_read_config_byte(dev
, reg
, &pci_cmd
);
579 if ( !(pci_cmd
& 1<<7) ) {
581 pci_write_config_byte(dev
, reg
, pci_cmd
);
588 static int __init
longhaul_cpu_init(struct cpufreq_policy
*policy
)
590 struct cpuinfo_x86
*c
= cpu_data
;
594 /* Check what we have on this motherboard */
595 switch (c
->x86_model
) {
597 cpu_model
= CPU_SAMUEL
;
598 cpuname
= "C3 'Samuel' [C5A]";
599 longhaul_version
= TYPE_LONGHAUL_V1
;
600 memcpy (clock_ratio
, samuel1_clock_ratio
, sizeof(samuel1_clock_ratio
));
601 memcpy (eblcr_table
, samuel1_eblcr
, sizeof(samuel1_eblcr
));
605 longhaul_version
= TYPE_LONGHAUL_V1
;
606 switch (c
->x86_mask
) {
608 cpu_model
= CPU_SAMUEL2
;
609 cpuname
= "C3 'Samuel 2' [C5B]";
610 /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
611 memcpy (clock_ratio
, samuel1_clock_ratio
, sizeof(samuel1_clock_ratio
));
612 memcpy (eblcr_table
, samuel2_eblcr
, sizeof(samuel2_eblcr
));
615 if (c
->x86_mask
< 8) {
616 cpu_model
= CPU_SAMUEL2
;
617 cpuname
= "C3 'Samuel 2' [C5B]";
619 cpu_model
= CPU_EZRA
;
620 cpuname
= "C3 'Ezra' [C5C]";
622 memcpy (clock_ratio
, ezra_clock_ratio
, sizeof(ezra_clock_ratio
));
623 memcpy (eblcr_table
, ezra_eblcr
, sizeof(ezra_eblcr
));
629 cpu_model
= CPU_EZRA_T
;
630 cpuname
= "C3 'Ezra-T' [C5M]";
631 longhaul_version
= TYPE_POWERSAVER
;
633 memcpy (clock_ratio
, ezrat_clock_ratio
, sizeof(ezrat_clock_ratio
));
634 memcpy (eblcr_table
, ezrat_eblcr
, sizeof(ezrat_eblcr
));
638 cpu_model
= CPU_NEHEMIAH
;
639 longhaul_version
= TYPE_POWERSAVER
;
641 switch (c
->x86_mask
) {
643 cpuname
= "C3 'Nehemiah A' [C5N]";
644 memcpy (clock_ratio
, nehemiah_a_clock_ratio
, sizeof(nehemiah_a_clock_ratio
));
645 memcpy (eblcr_table
, nehemiah_a_eblcr
, sizeof(nehemiah_a_eblcr
));
648 cpuname
= "C3 'Nehemiah B' [C5N]";
649 memcpy (clock_ratio
, nehemiah_b_clock_ratio
, sizeof(nehemiah_b_clock_ratio
));
650 memcpy (eblcr_table
, nehemiah_b_eblcr
, sizeof(nehemiah_b_eblcr
));
653 cpuname
= "C3 'Nehemiah C' [C5N]";
654 memcpy (clock_ratio
, nehemiah_c_clock_ratio
, sizeof(nehemiah_c_clock_ratio
));
655 memcpy (eblcr_table
, nehemiah_c_eblcr
, sizeof(nehemiah_c_eblcr
));
665 printk (KERN_INFO PFX
"VIA %s CPU detected. ", cpuname
);
666 switch (longhaul_version
) {
667 case TYPE_LONGHAUL_V1
:
668 case TYPE_LONGHAUL_V2
:
669 printk ("Longhaul v%d supported.\n", longhaul_version
);
671 case TYPE_POWERSAVER
:
672 printk ("Powersaver supported.\n");
676 /* Find ACPI data for processor */
677 acpi_walk_namespace(ACPI_TYPE_PROCESSOR
, ACPI_ROOT_OBJECT
, ACPI_UINT32_MAX
,
678 &longhaul_walk_callback
, NULL
, (void *)&pr
);
680 /* Check ACPI support for C3 state */
681 if ((pr
!= NULL
) && (longhaul_version
== TYPE_POWERSAVER
)) {
682 cx
= &pr
->power
.states
[ACPI_STATE_C3
];
683 if (cx
->address
> 0 &&
684 (cx
->latency
<= 1000 || ignore_latency
!= 0) ) {
685 longhaul_flags
|= USE_ACPI_C3
;
686 goto print_support_type
;
689 /* Check if northbridge is friendly */
690 if (enable_arbiter_disable()) {
691 longhaul_flags
|= USE_NORTHBRIDGE
;
692 goto print_support_type
;
695 /* No ACPI C3 or we can't use it */
696 /* Check ACPI support for bus master arbiter disable */
697 if ((pr
== NULL
) || !(pr
->flags
.bm_control
)) {
699 "No ACPI support. Unsupported northbridge.\n");
704 if (!(longhaul_flags
& USE_NORTHBRIDGE
)) {
705 printk (KERN_INFO PFX
"Using ACPI support.\n");
707 printk (KERN_INFO PFX
"Using northbridge support.\n");
710 ret
= longhaul_get_ranges();
714 if ((longhaul_version
==TYPE_LONGHAUL_V2
|| longhaul_version
==TYPE_POWERSAVER
) &&
715 (scale_voltage
!= 0))
716 longhaul_setup_voltagescaling();
718 policy
->governor
= CPUFREQ_DEFAULT_GOVERNOR
;
719 policy
->cpuinfo
.transition_latency
= 200000; /* nsec */
720 policy
->cur
= calc_speed(longhaul_get_cpu_mult());
722 ret
= cpufreq_frequency_table_cpuinfo(policy
, longhaul_table
);
726 cpufreq_frequency_table_get_attr(longhaul_table
, policy
->cpu
);
731 static int __devexit
longhaul_cpu_exit(struct cpufreq_policy
*policy
)
733 cpufreq_frequency_table_put_attr(policy
->cpu
);
737 static struct freq_attr
* longhaul_attr
[] = {
738 &cpufreq_freq_attr_scaling_available_freqs
,
742 static struct cpufreq_driver longhaul_driver
= {
743 .verify
= longhaul_verify
,
744 .target
= longhaul_target
,
746 .init
= longhaul_cpu_init
,
747 .exit
= __devexit_p(longhaul_cpu_exit
),
749 .owner
= THIS_MODULE
,
750 .attr
= longhaul_attr
,
754 static int __init
longhaul_init(void)
756 struct cpuinfo_x86
*c
= cpu_data
;
758 if (c
->x86_vendor
!= X86_VENDOR_CENTAUR
|| c
->x86
!= 6)
762 if (num_online_cpus() > 1) {
763 printk(KERN_ERR PFX
"More than 1 CPU detected, longhaul disabled.\n");
767 #ifdef CONFIG_X86_IO_APIC
769 printk(KERN_ERR PFX
"APIC detected. Longhaul is currently broken in this configuration.\n");
773 switch (c
->x86_model
) {
775 return cpufreq_register_driver(&longhaul_driver
);
777 printk(KERN_ERR PFX
"Use acpi-cpufreq driver for VIA C7\n");
786 static void __exit
longhaul_exit(void)
790 for (i
=0; i
< numscales
; i
++) {
791 if (clock_ratio
[i
] == maxmult
) {
792 longhaul_setstate(i
);
797 cpufreq_unregister_driver(&longhaul_driver
);
798 kfree(longhaul_table
);
801 module_param (scale_voltage
, int, 0644);
802 MODULE_PARM_DESC(scale_voltage
, "Scale voltage of processor");
803 module_param(ignore_latency
, int, 0644);
804 MODULE_PARM_DESC(ignore_latency
, "Skip ACPI C3 latency test");
806 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
807 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
808 MODULE_LICENSE ("GPL");
810 late_initcall(longhaul_init
);
811 module_exit(longhaul_exit
);