arch/m68k/coldfire/m523x.c

   1 /***************************************************************************/
   2
   3 /*
   4  *      m523x.c  -- platform support for ColdFire 523x based boards
   5  *
   6  *      Sub-architcture dependent initialization code for the Freescale
   7  *      523x CPUs.
   8  *
   9  *      Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
  10  *      Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  11  */
  12
  13 /***************************************************************************/
  14
  15 #include <linux/kernel.h>
  16 #include <linux/param.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <asm/machdep.h>
  20 #include <asm/coldfire.h>
  21 #include <asm/mcfsim.h>
  22 #include <asm/mcfclk.h>
  23
  24 /***************************************************************************/
  25
  26 DEFINE_CLK(pll, "pll.0", MCF_CLK);
  27 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  28 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
  29 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
  30 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
  31 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
  32 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  33 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  34 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
  35 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
  36 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
  37 DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
  38
  39 struct clk *mcf_clks[] = {
  40         &clk_pll,
  41         &clk_sys,
  42         &clk_mcfpit0,
  43         &clk_mcfpit1,
  44         &clk_mcfpit2,
  45         &clk_mcfpit3,
  46         &clk_mcfuart0,
  47         &clk_mcfuart1,
  48         &clk_mcfuart2,
  49         &clk_mcfqspi0,
  50         &clk_fec0,
  51         &clk_mcfi2c0,
  52         NULL
  53 };
  54
  55 /***************************************************************************/
  56
  57 static void __init m523x_qspi_init(void)
  58 {
  59 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  60         u16 par;
  61
  62         /* setup QSPS pins for QSPI with gpio CS control */
  63         writeb(0x1f, MCFGPIO_PAR_QSPI);
  64         /* and CS2 & CS3 as gpio */
  65         par = readw(MCFGPIO_PAR_TIMER);
  66         par &= 0x3f3f;
  67         writew(par, MCFGPIO_PAR_TIMER);
  68 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  69 }
  70
  71 /***************************************************************************/
  72
  73 static void __init m523x_i2c_init(void)
  74 {
  75 #if IS_ENABLED(CONFIG_I2C_IMX)
  76         u8 par;
  77
  78         /* setup Port AS Pin Assignment Register for I2C */
  79         /*  set PASPA0 to SCL and PASPA1 to SDA */
  80         par = readb(MCFGPIO_PAR_FECI2C);
  81         par |= 0x0f;
  82         writeb(par, MCFGPIO_PAR_FECI2C);
  83 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
  84 }
  85
  86 /***************************************************************************/
  87
  88 static void __init m523x_fec_init(void)
  89 {
  90         /* Set multi-function pins to ethernet use */
  91         writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
  92 }
  93
  94 /***************************************************************************/
  95
  96 void __init config_BSP(char *commandp, int size)
  97 {
  98         mach_sched_init = hw_timer_init;
  99         m523x_fec_init();
 100         m523x_qspi_init();
 101         m523x_i2c_init();
 102 }
 103
 104 /***************************************************************************/